JPS59104788A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To facilitate an easy design of a circuit and to attain a high-speed operation and a low power consumption by starting immediately the reading and writing operations with an address signal and having automatically a reset state at a time point when said reading and writing operations advance to some extent. CONSTITUTION:In a read mode the time from an address change to the data latch is previously set to a timer circuit 10, and therefore a clock generating circuit 11 does not deliver a clock signal phiDE any more at a latch time point and is set at a prescribed level. Thus a row decoder 8 is inactive, and a selection word line WL is reset to a non-selection state. As a result, a transfer gate within a memory cell 1 is closed, and a bit line is charged by a load circuit 2 to be reset. The sense lines are also reset successively. In other words, the read- out time tRD overlaps the reset time tRS, and a reset state is obtained when a reading cycle tRC starts. The read-out state is shifted to a reset state as if it run after a read-out signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor memory devices, and particularly to random access static type memories.

[Technical background of the invention]

Various methods have been proposed to increase the speed and reduce power consumption of random-access static memory (read/write RAM, read-only ROM) that accesses any address at the same speed. There is. FIG. 1 shows the operation of read cycle tRC in one of these methods. This detects a change in an address signal, generates a clock signal, and causes the memory circuit to operate in synchronization with this clock signal. That is, first, the potential of the bit line is reset, and then the data of the memory cell corresponding to the set address signal is read. This kind of reset operation enables a read operation, and since it does not use a DC intermediate potential (an intermediate voltage between two memory power supply voltages), there is no DC power consumption, resulting in lower power consumption. be able to.

[Problems with background technology]

By the way, in the method shown in Figure 1, each circuit operates in synchronization with a clock signal, and speeding up is achieved by providing a margin for each control clock and shifting the phase so that each circuit block does not malfunction. This requires a difficult design technique. Furthermore, large amplitude operations are performed on the main signal lines, and as the operation speed increases, charging and discharging the capacitance of the signal lines becomes the main power consumption, so there is a limit to how much power can be reduced.

[Purpose of Prophecy]

The present invention has been made in view of the above-mentioned circumstances, and provides a semiconductor memory device in which circuit design regarding the operation timing of each circuit block is easy, and it is possible to achieve high-speed operation and low power consumption. be.

[Summary of the invention]

That is, the present invention provides a random access type semiconductor memory device that has a normally on-state load circuit between a bit line connected to a static type memory cell and a power supply, and detects a change in an address signal to generate an internal control signal. means to immediately activate a row decoder to select a specific lead line and a memory cell connected thereto and start a read or write operation thereof; After a period of time or after the sensing by the sense amplifier is completed, the internal control signal is returned to the inactive state, thereby deactivating the row decoder and returning the selected word line to the unselected state, thereby controlling the pair of bit lines. The present invention is characterized by comprising a reset means for automatically shifting to a reset state by a load circuit that is normally on.

Therefore, a read operation or a write operation is started immediately upon a change in the address signal, and when the read operation or write operation has progressed beyond a certain level, the device automatically shifts to the reset state. However, since the device is in a reset state in advance for a read or write operation, the read or write operation can be started immediately, making high-speed operation possible. Further, since no direct current flows in the reset state, almost no power is consumed, and since the reset state is entered immediately after a read operation or a write operation, power consumption is significantly reduced.

In addition, only one type of internal control signal is required, and there is no need to take margins for each circuit operation, which simplifies circuit design and enables high-speed operation.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. Figure 2 shows a part of a random access type read/write memory (RAM), in which 1 indicates one static type memory cell in the memory cell array, WL and B.
L and BL are a word line and a pair of bit lines connected to the memory cell 1, and 2 is a pair of bit lines BL.

A normally on-state load circuit is connected to each of the bit lines BL, and 3 is a pit line selection transfer r-) (MOS) runnostar) connected to each of the pair of bit lines BL, BL.
, s and 100 are a pair of sense lines, 4 is a sense amplifier, 5
is a latch circuit. 6 is address signal A. -An is the input address buffer, 7 is the address signal input 0~
This is an address change detection circuit that detects changes in An.

8 receives an address signal from the address buffer 6, becomes activated when a clock signal φDE (to be described later) is input, and performs a Tetecode operation, and when the clock signal φDI is no longer input, decodes the decode operation and disables it. A static row decoder that becomes active,
A specific word line is selected and activated from among a large number of word lines. Reference numeral 9 denotes a control circuit υ, which includes a timer circuit (or delay circuit) 10 that starts operating as soon as the detection signal from the address change detection circuit 7 is input, and a timer circuit (or delay circuit) 10 that starts operating as soon as the detection signal from the address change detection circuit 7 is input; ! ! It has a clock generation circuit 11 that generates a clock. The timer circuit 10 generates a timer output signal after a certain period of time from the start of operation, which causes the clock generation circuit 11 to generate a clock signal φD! It is designed to output a predetermined level without causing any noise.

Incidentally, vDD is a power supply potential, for example, 5V is used, and the load circuit 2 has an N-channel MO8) transistor inserted in series with the bit line, and VDD is connected to the dirt of the load circuit 2.
It is turned on by applying D.

Next, the read mode of the memory will be explained with reference to FIG. When address signals A, ~An change,
A detection signal is output from the address change detection circuit 7, and thereby a clock signal φDI is generated from the clock generation circuit 11, the row decoder 8 is activated, and the address signal Ao-
A specific word line WL corresponding to An is selected.

As a result, the signal of the memory cell 1 connected to this selected word line WL is read out to the bit lines BL, BL, and this signal passes through the bit line selection transfer f-3 and the sense lines s and 1 to the sense amplifier. 4.
This sense output data is latched by a latch circuit 5, and the latch data of this latch circuit 5 is sent to an output buffer (not shown) and becomes a data output. Therefore, if the time required from the address change described above to the data latch is assumed to be constant and set in advance in the timer circuit 10, the clock generation circuit 11 will stop outputting the clock signal φDI at the time of data latch. Predetermined level (row decoder 8
If the inhibit signal is not present, the row decoder 8 is deactivated and the selected word line WL is returned to the unselected state. This closes the transfer date in memory cell 1,
The bit lines BL and BL are charged by the load circuit 2 and enter a reset state, and accordingly, the sense lines s and s also sequentially shift to a reset state.

That is, in the memory of the above embodiment, the read operation starts immediately upon a change in the address signal, the read data is latched, and the bit line is automatically reset to the reset state after a certain period of time has elapsed from the start of the read operation. In other words, during the read operation time tRD, the reset operation time tR8
At the beginning t, b, the read operation and the reset operation overlap and are performed simultaneously, and are in the reset state in advance at the start of the read cycle tRC. Further, the transition from the read operation to the reset operation is not performed in synchronization with a certain clock signal, but the transition to the reset state follows the read signal.

FIG. 4 shows the sense amplifier 4 and latch circuit 5 of FIG.
A specific example is shown. In sense an f4, P
l and P2 are P-channel MO8) transistors, N1
~N3 is an N-channel MOS transistor. The transistors Pl and P2 have their respective sources connected to the first power supply of VOO potential, and the respective darts correspond to the sense lines S and S.
each drain is connected to a corresponding transistor NJ,
N.? It is connected to the drive. The sources of the transistors N1 and N2 are connected to a second power source at VSS potential (ground potential), the respective darts are connected to each other, and the r-) and drains of one transistor N2 are connected to each other.

Furthermore, a transistor x N is connected in parallel to the transistor N2.
3 is connected, and the r-to of this transistor N3 is connected between one sense line.

The drain connection point of the transistors Pl and Nl serves as an output node NDI. On the other hand, the latch circuit 5 is
Two inverters Gl and G2 are connected in parallel, and their human power node ND2 is connected to the output node NDI of the sense amplifier 4.

In FIG. 4, the read operation causes the complementary data of sense line S, 100 to be changed to ``V'', ``o'' (here, 1'' is VD).
D potential, 1o# is vgs potential), transistors P1 and N3 are off, transistors P2 and N, 1
．． N2 is turned on and the output node ND2 becomes 0''.

Therefore, the latch circuit 5 latches the "0" input and
1" data is output. Contrary to the above, when the complementary data of the sense line s and 100 becomes 60" and "bi", the transistor P
1 and N3 are on, transistors P2 and Nl, N
2 is turned off, the output node ND2 becomes ``1'', and the latch circuit 5 latches the tt1m input and outputs 0'' data. On the other hand, when the read operation shifts to the reset operation and the sense lines S and S both shift to the 1'' level, the potentials of the sense lines S and S are both KVDn.
-I VTRP 1 (However, vTHP is a P-channel transistor PI.

(threshold voltage of P2) to a higher level, transistors PI, P2. Nl and N2 are turned off and output node ND1 is in a high impedance state. therefore,
The reset has no effect on the stage subsequent to the sense amplifier 04, and the latch circuit 5 continues to hold the latched data up to that point.

Note that in the latch circuit 5, the inverter G2 whose output end is connected to the input capacitor RND2 has an extremely low driving capacity and is set to the minimum capacity that can withstand noise and leakage current. It does not interfere with data read operations.

Note that for the sense amplifier 4 in FIG. 4, the sense lines S,
The connection may be made by replacing S.

Note that in the RAM, a write circuit (not shown) is connected to the sense lines s and 100, and in the write mode, the write operation is started immediately after the address signal changes, and the row decoder 8 is deactivated after a certain period of time. to automatically reset. In addition, in the case of read-modify-write mode, as shown in Figure 5, the high level period of the R/W (read/write) signal input to the memory chip is the read mode, and the low level period is the write mode. For example, data can be written by setting the n/v signal to a low level, ie, write mode, after a sufficiently long time tAW after the address signal changes (a period that guarantees a read operation). To ensure this kind of operation, when the Ft/W signal goes low, if a word line has been selected, it remains in that state, and if the word line has already been selected, the word line is selected again. It is necessary to control the system so that it is carried out. For this purpose, the R and Ayt signals may be input to the control circuit 9 to control the clock signal φDI.

In addition, as mentioned above, in a memory that performs a read operation or a write operation before a reset operation, if there is a skew (phase shift) in the address signal (
(usually there is skew) may cause malfunction.

That is, if a new address signal is input immediately after starting an operation regarding a certain address signal, the correct operation cannot be performed with respect to the new address signal. In order to prevent this malfunction, the present invention uses a completely asynchronous static decoder. FIG. 6 shows a specific example of a row decoder for one row of the static type row decoder 8 of FIG. The decoder 61 connects in parallel a group of P-channel transistors 122 to which the address signal input from the address nozzle is applied to f-), and an N group of N-channel transistors to which the address signal input is also applied to the dart. The 22 groups of transistors and the N group of transistors are connected in series between the vDD power source and the V88 power source. Therefore, the decoding operation is performed completely asynchronously. This decoded output is input to a driving section 62 using a CMOS inverter, and this driving section 62 is connected to the vDD power supply via a P-channel transistor 63 that is turned on by the clock signal φDE at the '0'' level. The word line WL is activated by the drive output. When the clock signal φDK is no longer input and an inhibit signal of the "1" level is input, the transistor 64 is turned off and the drive section 62 becomes inactive. Further, an N-channel transistor 64 is provided between the output terminal of the drive section 62 and the v88 potential, which is turned on by the above-mentioned prohibition signal and discharges the lead line WL to make it into a non-selected state.

According to the above-mentioned memory, since no DC current flows in the reset state, it consumes almost no power, and because it shifts to the reset state immediately after a read or write operation, power consumption is significantly reduced. Decrease. Further, since the device is in a reset state in advance for a read or write operation, the read or write operation can be performed immediately, and extremely high-speed read or write operations are possible. In addition, only one type of internal control signal, the clock signal φDffi, is required, and each circuit operation is automatically controlled by a combination of complementary signals, so there is no need to take operational margins, making it easy to use. High-speed operation can be achieved.

Furthermore, when the complementary data inputs of the sense amplifier 4 both exceed a predetermined level during transition to the reset state, the output node becomes a high impedance state, so that the effect of the reset does not appear in the subsequent stage of the sense amplifier 4, and the subsequent stage The circuit configuration becomes simpler.

Further, in the above embodiment, the clock signal φDI is not outputted after a certain period of time by the timer circuit 10 to shift to the reset state, but the pair of bit lines BL and BL (or the pair of sense lines S and S connected thereto) ) by detecting the point in time when the mutual logic levels of the signals become inconsistent, and controlling the output of the clock signal φDI using this detection signal, the reset is performed at a timing earlier than the elapse of the above-mentioned certain period of time. It may be possible to change the state to a higher speed and perform a higher speed operation. For this purpose, a pair of bit lines BL.

100 (or a pair of sense lines S, S) are inputted to, for example, an exclusive OR circuit, and the logic-established output is inputted to the control circuit 9, which outputs the clock signal φDE and is controlled to be dangerous. That's fine.

In addition, the transfer r-) for bit line selection in the above embodiment
A bit line sense amplifier is used instead of J, and the output of this sense amplifier is led to the main sense amplifier via a pair of data lines, or a memory cell has only one bit line connected to it. The present invention can also be applied to memories and the like.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention, one type of internal control signal is used to facilitate circuit design regarding the operation timing of each circuit block, thereby achieving faster operation and lower power consumption. can be realized.

[Brief explanation of drawings]

FIG. 1 is a timing diagram showing an example of read mode operation in a conventional semiconductor memory device, FIG. 2 is a configuration explanatory diagram showing main parts of an embodiment of the semiconductor memory device according to the present invention, and FIG. FIG. 4 is a timing diagram showing the read mode operation in the storage device shown in FIG. 2, FIG. 4 is a circuit diagram showing the sense amplifier and latch circuit shown in FIG. 2, and FIG. 5 is a read modify write in the storage device shown in FIG. 2. FIG. 6 is a timing diagram illustrating an example of the operation of the mode. FIG. 6 is a circuit diagram showing the negative part of the row decoder in FIG. 2. DESCRIPTION OF SYMBOLS 1... Memory cell, 2... Load circuit, 4... Sense angle, 7... Address change detection circuit, 8... Row decoder, 9... Control circuit, 1o... Timer circuit,
11... Clock generation circuit, BL, BL... Bit line, WL... Word line, φDI! ! ...clock signal.

Claims (1)

[Claims] (1) In a random access type semiconductor memory device having a normally on-state load circuit between a bit line connected to a static type memory cell and a power supply, an address change detection circuit for detecting a change in an address signal; A control circuit generates an internal control signal in response to the detection signal of the detection circuit, and receives the internal control signal (3) from this control circuit to decode the activated sear address signal input and select a specific word line and a static row decoder that selects a memory cell connected to it; a sense amplifier that detects a signal read out from the memory cell to the bit line; and a sense amplifier that deactivates the internal control signal after sensing by the sense amplifier is completed. (4) setting means, the row decoder is brought into an inactive state by the reset means, the selected word line is brought into a non-selected state, and the bit line is brought into a reset state by a load circuit. semiconductor storage device. The reset means regards the time from the generation of the detection signal of the address change detection circuit to the end of sensing as a constant, and deactivates the internal control signal by giving this constant time from a timer circuit or a delay circuit. The semiconductor memory device described in Patent No. 1, which is characterized in that it returns to the original state. The reset means deactivates the internal control signal by detecting a mismatch in logic levels between signals on a pair of bit lines in the memory cell array or between signals on a pair of signal lines connected to the pair of bit lines. 1. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is The sense amplifier receives each signal from a pair of bit lines or i pairs of signal lines connected to the pair of bit lines, and when the above-mentioned signals both exceed a predetermined potential at the time of transition to the reset state, 1. A semiconductor memory device according to item 1 of the patent, wherein the output is in a high impedance state.