JPS59104639U - Squelch noise canceling receiver - Google Patents
Squelch noise canceling receiverInfo
- Publication number
- JPS59104639U JPS59104639U JP19607882U JP19607882U JPS59104639U JP S59104639 U JPS59104639 U JP S59104639U JP 19607882 U JP19607882 U JP 19607882U JP 19607882 U JP19607882 U JP 19607882U JP S59104639 U JPS59104639 U JP S59104639U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- squelch
- receiving circuit
- noise canceling
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Noise Elimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のスケルチ雑音消去式受信機のブロン′り
図、第2図は本考案の一実施例のブロック図、第3図は
第2図に示した遅延回路24のブロック図である。
21・・・受信回路、2.2・・・電圧増幅器、23・
・・スケルチ回路、24・・・遅延回路、25・・・電
力増幅器、26・・・スピーカ、31−・・・A/Dコ
ンバニタ、32・・・シフトレジスタ、33・・・D/
Aコンバータ。Fig. 1 is a block diagram of a conventional squelch noise canceling receiver, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 3 is a block diagram of the delay circuit 24 shown in Fig. 2. . 21... Receiving circuit, 2.2... Voltage amplifier, 23.
... Squelch circuit, 24... Delay circuit, 25... Power amplifier, 26... Speaker, 31-... A/D converter, 32... Shift register, 33... D/
A converter.
Claims (1)
導く出力回路と、この受信回路からの音声信号中の雑音
レベルを検出し、この雑音レベルが所定のレベル以上で
あるとき、前記出力回路の出力を無効にする制御信号を
送出するスケルチ回路と前記受信回路と前記出力回路と
の間に前記スケルチ回路の雑音検出所要時間だけ受信回
路から出力回路への信号の伝達を遅延させる遅延手段と
を具備したことを特徴とするスケルチ雑音消去式a receiving circuit, an output circuit that guides an audio signal from the receiving circuit to a speaker, and detecting a noise level in the audio signal from the receiving circuit, and when the noise level is equal to or higher than a predetermined level, the output circuit A squelch circuit that sends out a control signal for disabling the output, and a delay means that delays the transmission of the signal from the receiving circuit to the output circuit by the time required for noise detection of the squelch circuit between the receiving circuit and the output circuit. A squelch noise canceling system featuring the following features:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19607882U JPS59104639U (en) | 1982-12-28 | 1982-12-28 | Squelch noise canceling receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19607882U JPS59104639U (en) | 1982-12-28 | 1982-12-28 | Squelch noise canceling receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59104639U true JPS59104639U (en) | 1984-07-14 |
Family
ID=30420870
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19607882U Pending JPS59104639U (en) | 1982-12-28 | 1982-12-28 | Squelch noise canceling receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59104639U (en) |
-
1982
- 1982-12-28 JP JP19607882U patent/JPS59104639U/en active Pending
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