JPS59101930A - Outputting circuit - Google Patents

Abstract

PURPOSE:To prevent a spike-like current from flowing to an outputting circuit by varying the threshold voltage of an input signal in case when two transistors of an input side circuit driven by an input signal conduct. CONSTITUTION:When a signal of a high level is applied to an input terminal I, transistors TR Q4, Q8 and Q7 become a conducting state, and TRs Q5, Q6 become a non-conducting state, therefore, a level of an output terminal 0 becomes low. On the other hand, when a signal of a low level is applied to the terminal I, the TRs Q4, Q8 and Q7 become a non-conducting state, and the TRs Q5, Q6 become a conducting state, therefore, a level of the terminal 0 becomes high. In this case, when threshold voltage of an input signal of the terminal I in case of the former and threshold voltage of the input signal of the terminal I in case of the latter are denoted as VT1 and VT2, respectively, they are in relation of VT1<VT2, and when an input signal level V1 is in relation of VT1<V1<VT2, only the TR Q4 conducts, therefore, it can be prevented that a spike-like current flows to an outputting circuit.

Description

[Detailed description of the invention] Industrial applications.

The present invention relates to an improved output circuit for a digital circuit that processes digital signals.

Conventional configuration and its problems Conventionally, this type of output circuit has been configured as shown in FIG. That is, resistor R1, transistor Q1
, an input side circuit in which resistor R21 is connected in series and the base of transistor Q1 is connected to input terminal l, resistor R3, transistor Q2 . Transistor Q3 is connected in series, and an output side circuit in which the collector of transistor Q3 is connected to output terminal 0 is connected in parallel to the power supply, and transistor Q2
The base of transistor Q1 is connected to the collector of transistor Q1, and the base of transistor Q3 is connected to the emitter of transistor Ql.

In the conventional example configured as described above, when a high-level signal is applied to the input terminal I, the transistor Q1 and the transistor Q3 become conductive, and the transistor Q2 becomes non-conductive, so that the level of the output terminal ◯ becomes a low level. In this state, a load (not shown) connected to output terminal 0 is connected to output terminal 0. ) Current is drawn through transistor Q3. Furthermore, when a low level signal is applied to input terminal I, transistor Q1 and transistor Q3 become non-conductive.
Transistor Q2 becomes conductive, so output terminal 0
/ Hell is at a high level. In this state, current is supplied to the load from a power supply (not shown) through resistor R3 and transistor Q2. However, when the signal applied to the input terminal I switches from high level to low level, that is, in the process in which transistors Q1 and Q3 respectively transition from a conductive state to a non-conductive state, transistors Q1 and Q3
A phenomenon occurs in which all of Q2 and Q2 become conductive. When such a phenomenon occurs, resistor R3, transistor Q2 . There is a drawback that a spike-like current flows through the transistor Q3, causing a malfunction in the circuit system.

OBJECTS OF THE INVENTION The present invention aims to eliminate the drawbacks of the conventional array described above, and provides an output circuit that prevents spike-like current from flowing through the output circuit.

Structure of the Invention The present invention comprises two transistors constituting an output side circuit,
That is, a transistor for supplying a high level to the output terminal and a transistor for an input side circuit that drives a transistor that draws the output terminal to a low level are provided respectively, and the transistor for the input side circuit driven by the input signal becomes conductive. In other words, the first transistor of the input circuit drives the third transistor of the output circuit which supplies a high level to the output terminal. Threshold voltage vT of the input signal when the second transistor conducts
1 and the fourth output side circuit that draws the output terminal to a low level.
By setting the threshold voltage vT2 of the input signal when the fifth transistor of the input side circuit which drives the transistor of the input side circuit conducts to be vTl<vT2, the third transistor of the output side circuit. This is an output circuit that prevents the fourth transistor from being conductive at the same time.

Description of examples FIG. 2 shows an embodiment of the present invention.

In Figure 2, the input side circuit has an nPn whose base is connected to the input terminal check via resistor R4, whose collector is connected to one end of the power supply via resistor R6, and whose emitter is connected to the other end of the power supply. an npn type transistor Q5 having a base connected to the collector of the npn type transistor Q4, a collector connected to the one end of the power supply via a resistor R6, and an emitter connected to the other end of the power supply. , an NPN type transistor Q8 whose base is connected to the input terminal I and whose collector is connected to the one end of the power supply, and the output side circuit has its base connected to the collector of the transistor Q5 of the input side circuit via the resistor R7. an NPN type transistor Q6 having an emitter connected to the one end of the power source and a collector connected to the output terminal O; is composed of an npn type transistor Q7 connected to the emitter of the transistor Q8 of the input side circuit. Of course, the resistor R6 may be a constant current circuit. In the above configuration, when a high level signal (2VBE or higher) is applied to the input terminal Che, the transistor Q4. Q8. Q
7 becomes conductive, and transistors Qs and Qe become non-conductive, so that the output terminal 00 level becomes a low level.

In this state, a load (not shown) connected to output terminal O
A current is drawn from the output terminal ○ through the transistor Q7. Furthermore, when a low level signal (below vBE) is applied to the input terminal Q, transistor Q4. Q8. Since Q7 becomes non-conductive and transistors Q6 and Qe become conductive, the level of the output terminal O becomes high level. In this state, current is supplied from the power supply to the load through transistor Q6.

In other words, transistor Q4 becomes conductive, and transistor Q5 becomes conductive.
When transistor Q6 becomes non-conductive and transistor Q6 becomes conductive, the threshold direct voltage vT1 of the input signal of input terminal Che is vT12vBE, and transistor Q8. When Q7 conducts, the threshold voltage of the input signal at input terminal l is V -2V.
BE 2 , and there is a relationship: ①T1<vT2. Here, ■BE is the base of the transistor.
is the emitter voltage. Therefore, when the signal applied to the input terminal Che switches from high level to low level or from low level to high level, that is, when the input signal level vl is ■T1<vl<vT2, only transistor Q4 is switched. The transistor Q6, Qe, Q7, and Qs become conductive, and the other transistors Q6, Qe, Q7, and Qs become nonconductive, thereby preventing spike-like current from flowing into the output circuit.

By adding a resistor R8 between the base and emitter of the transistor Q4 in the configuration shown in FIG.
T1 is , and vTl can be arbitrarily set by the ratio of the resistance values of resistors R4 and R8. When the input signal level of input terminal I 1 is T1<vl<vT2, that is, both transistors Q6 and Q7 are non-conducting. It is also possible to shorten the time required for the state to occur.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention has a very simple configuration that prevents spike-like current from flowing in the circuit when the output level transitions from a high level to a low level or from a low level to a high level. It has the characteristic of being able to prevent malfunctions of circuit systems.

[Brief explanation of drawings]

Figure 1 is an electrical circuit diagram showing the configuration of a conventional output circuit;
The figure is an electrical circuit diagram showing an output circuit according to an embodiment of the present invention. ■・Input terminal, 0...Output terminal, Ql,
Q2゜Qs, Q4. Qs, Q7. Qs...npn
type transistor, Qe...pnp type transistor, R1°R2, R3, R4, R5, R6, R7...resistor. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (2)

[Claims] (1) A first transistor whose base is connected to the input terminal via a first resistor, whose collector is connected to one end of the power supply, and whose base is connected to the other end of the power supply, and the output of the first transistor. a second transistor driven by a signal, the emitter of which is connected to the other end of the power source, and the base of which is connected to the collector of the second transistor through a second resistor, the emitter and collector of which are connected to the other end of the power source; a third transistor connected between the one end and the output terminal of the power supply, a base connected to the input terminal through at least one PN junction, and an emitter connected to the other end of the power supply; An output circuit comprising a fourth transistor having a collector connected to the output terminal. (2) The collector of the first transistor is connected to the base of the second transistor and one end of the power supply via a third resistance means, and the collector of the second transistor is connected to the base of the third transistor. The pN junction is connected through a second resistor and the one end of the power supply through a fourth resistor, and the pN junction is a sixth transistor, 2. The output circuit according to claim 1, wherein the collector of the transistor is connected to the one end of the power supply, the emitter is connected to the base of the fourth transistor, and the base is connected to the input terminal.