JPS59101612A - Storage time controlling circuit for focus detecting device - Google Patents

Abstract

PURPOSE:To reduce a storage time so that a focus detecting operation can be executed more quickly, in case when an illumination is executed by an artificial light, by providing a storage time mediating means for shortening a time when an integral output reaches a reference level, and operating the means when an auxiliary light is used. CONSTITUTION:An output of an AND gate A15 operates as a shift pulse phiT of sensors 15, 16, and when phiT becomes Lo, the sensors 15, 16 display a storage opration of an image pattern whose image is formed. Also, in this case, a transistor TR becomes off by a Q output Lo of an FF2, therefore, a capacitor C starts charging of an output current of a photodetector PD. When charging to the capacitor C is started as mentioned above, and its charging level reaches a reference level determined by resistances R2, R3 and R1, a comparator CP1 outputs Hi. As a result, Q of the FF2 becomes Hi from Lo. Therefore, an AND gate A15 sets its output phiT to Hi again, and sends out charge accumulated by the sensors 15, 16 to an analog shift register in the sensor. Accordingly, a level of an image pattern signal accumulated by the sensor is amplified and mediated automatically to a proper level, irrespective of a photographic luminance.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an accumulation time control circuit for a focus detection device that uses an accumulation type photoelectric conversion element as a light-receiving sensor and detects a distance to a subject based on the output of the light-receiving sensor.

BACKGROUND ART Focus detection devices have been known that form a subject image on an accumulation type photoelectric conversion element, such as a line image sensor using COD, and perform focus detection based on the image signal accumulated in the element. .

The storage type photoelectric conversion element described above has a narrow dynamic range with respect to the amount of light, and cannot be used as is under all brightness conditions that allow photography.The storage time is adjusted according to the brightness and the accumulated image signal is How to adjust the level of (
automatic gain control).

In addition, even at the same brightness, the image signal accumulated when the contrast is strong during focus detection operation becomes stronger when illuminated with artificial light rather than natural light. One possible method is to use light to strengthen the contrast. However, when the contrast is strengthened by illuminating with artificial light, the image level may become higher than necessary if the automatic gain control is performed in the same way as with natural light.

That is, in the case of an image illuminated with natural light and having weak contrast as shown in Figure 1A, if the accumulation time is controlled by the automatic gain control described above, the image signal will be amplified as shown in Figure 1A', and the image level will be lowered. is adjusted to an appropriate value, but if the above object is illuminated with artificial light and an image with a strong contrast as shown in Figure 1B is obtained, the same automatic gain control as in the case of a weak contrast case is performed. In cases such as B', unnecessary image level widening is performed. Therefore, for an image that is illuminated with artificial light and has a strong contrast, the image level will be appropriate even if the storage time is shortened. By doing this, the storage time can be shortened. It becomes possible to perform the focus detection operation at high speed.

The present invention has been made in view of the above matters, and includes a light receiving sensor consisting of a storage type photoelectric conversion element that receives a subject image and accumulates a signal corresponding to image formation, and an integrating circuit that integrates the amount of light of the subject. and a timer circuit that generates an output when the output reaches a predetermined reference level, prohibits the signal accumulation operation of the photoelectric conversion element, and adjusts the accumulation time of the photoelectric conversion element according to the subject brightness. In an accumulation time control circuit (automatic gain control circuit) for a focus detection device, an accumulation time adjustment means for shortening the time until the integrated output reaches the reference level is provided, and the means is activated when an auxiliary light is used. Particularly when illuminating with artificial light, the accumulation time is reduced so that a fast focus detection operation can be performed.

Next, a focus detection device to which the accumulation time control circuit according to the present invention is applied will be explained.

FIG. 2 is a configuration diagram showing the configuration of a camera system in which the focus detection device described above is employed. In the figure, reference numeral 2 denotes a camera, and an image from a subject 1 is guided to a main mirror 6 having a half mirror through a photographing lens (objective lens 12) of the camera. The image passing through the half mirror is formed on a part of the light receiving sensor via the auxiliary mirror 4 and the focus detection optical system 5. 6 is a flash device having an auxiliary light source 8 attached to the camera 2.

FIG. 3 is a configuration diagram showing the principle configuration of the focus detection optical system shown in FIG. 1. In the figure, reference numeral 13 indicates a position equivalent to the film surface, and during focusing, the image of the subject 1 that enters through the lens 12 is formed at the position 13. 14 is a secondary optical system, and the image is formed on the light receiving sensor 15, 16 of the light receiving sensor portion 20 via the optical system. The light receiving sensor 15 is a sensor for a reference field of view, and 16 is a sensor for a reference field of view.The image pattern formed on the sensor 15 is focused on a predetermined position on the sensor 16 when in focus. matches the pattern. Therefore, when the image is out of focus, the image pattern formed on the sensor 15 is formed at a position different from the position on the sensor 16.

FIG. 4 is a circuit diagram showing an embodiment of an automatic focus adjustment device to which the accumulation time control circuit according to the present invention is applied. In the figure, 2o is a part of the light receiving sensor, and 15 and 16 are the light receiving sensors, respectively. The sensor 15 is a reference visual field sensor that has eight photosensitive parts (15-1 to 15-8) and on which a subject image pattern is formed through the optical system. It consists of a line image sensor using storage type photoelectric conversion elements. In addition, there are 16 sensors 16 (16-1 to 16-1+
5) A reference visual field sensor having a photosensitive section, in which a subject image pattern is imaged at a position according to the focusing state of the lens through the optical system, and this sensor is also a line image sensor as described above. configured.

The same image pattern as the image pattern formed on the photosensitive parts 15-1 to 15-8 of the sensor 15 in the focused state is formed on the photosensitive parts 16-5 to 16-12 of the sensor 16. The optical system is arranged.

AD is sensor 15. From ↑6 onwards, the charges accumulated in each photosensitive section (photoelectric conversion signal) that are serially output in synchronization with the four clock CLKs described later are sequentially transferred to the sampling hold A.
This is an AD converter that performs D conversion.

Although this embodiment shows an example in which each charge is converted into a 2-bit digital value, it is of course possible to use an AD converter that converts into a multi-bit digital value in order to improve accuracy.

19R1 and SR2 are 8-bit and 16-bit shift registers, respectively, and each register SR4 and SR2 are respectively 5Ri-1, 5R1-2; 5R2-1, 8R2-
It is composed of two columns of shift registers, and sequentially inputs and stores information AD-converted by the AD converter in synchronization with a clock.

Note that the registers 8R1+1 and 5R2-1 constituting the registers EIR1 and SR2 are storage registers for the first bit information of the converted digital value.
Further, registers 5R1-2 and 5R2-2 form a storage register for second bit information of the digital value.

C24 is a counter that latches and outputs a high level signal (referred to as an elbow signal) by counting 24 pulses of the clock CLK. The output of the counter is input to the anti-gauge AI via the inverter A1, and in this configuration, A1 inputs 24 clock pulses directly or via ORGA-01 to the registers SR1 and sR2. Convey to end CLK. Therefore, the registers SRI and SR2 sequentially input the digital values from the AD converter in synchronization with the clock pulses inputted through the analog gate Aj, and shift to the right, and the first bit of register 8R2 is inputted by the 24 clock pulses. Digital values corresponding to the charges accumulated in the photosensitive sections 16-1 to 16-1 (S-15) are stored in the sections B-1 to 16th bit sections B-16, respectively, and the first bit sections A-, . . . Each photosensitive section 15 is in the 8th bit section A-8.
-1 to 15-8, store digital values corresponding to the accumulated charges.

CN1. CN2 is a 3-bit and 4-bit binary counter, respectively, and the clock input terminal of the counter CN1 is connected to the output terminal of the antgame 2. The input terminal of the AND gate A2 is connected to the output terminal of the counter C24, and the AND gate A2 is opened in response to the H1 signal from the counter C24, and the counter CN1 performs the counting operation of the clock CLK. Start.

SEL 1. BRL 2 is an 82-in-1 line data selector, and its input terminals A, B, and C are connected to the output terminals A, B, and C of the above-mentioned counter CIJl, and then connected to the above-mentioned registers SR1 and SR2 and sensors 15 and 16. Counter CN after the accumulated signals are transferred as described above
In a 10-count operation, selector sm:c,1 sequentially reads out the digital values stored in the first bit section A- to eighth pit section A-8 of register SR1, and selector EEL2 sequentially reads out the digital values stored in register 8R2. The digital values stored in the first bit section B-1 to the eighth bit section E-8 are read out. The output terminal C of the counter CNj is connected to the clock input terminal of the register SR2 via the inverter E 2 and the OR gate 01), and the register 8R2 receives the three signals Aλ and other low level signals (hereinafter referred to as (referred to as the LO signal). Therefore, the digital values corresponding to the charges accumulated in the photosensitive sections 15-1 to 15-8 stored in the first bit section A-j to the eighth bit section 1 of the selector 5ELi and register EIRj are repeatedly programmed. At the same time as outputting the return value, selector 511L2 selects the first bit part B of register SR2.
-Sequentially output the contents of the 1st to 8th bit parts B-8, :s-
Each time the contents of 1+++n-8 are output, shift register 8R2 is shifted by 1 bit to obtain the above B-1-B-8.
The output operation of the contents is executed repeatedly. Therefore, from the selector 〇EfL 2, the above-mentioned photosensitive parts 16-1 to 16-
Digital values corresponding to the charges accumulated in the photosensitive sections 16-2 to 16-9 are sequentially output, and then digital values corresponding to the charges accumulated on the photosensitive sections 16-2 to 16-9 are outputted.
The digital value reading operation is executed while shifting one by one.

Now, each digital value stored in the first bit part A-1 to the eighth bit part A-6 of register 8Ri is ACl, AC
9 and AC1 to AC8 are photosensitive parts 15-1 to 15-8.
The value corresponds to the accumulated charge of . ), and 1st bit part B-1 to 16th bit part B-1 of register SR2
Each digital value stored up to 6 is stored as BCj to BC16 (
BC1 to BC16 correspond to the charges accumulated in the photosensitive sections 16-1 to 16-16. ), then with the above configuration, the fifth
As shown in the table shown in the figure, each digital value is selected by the selector SEL.
i and SEL2.

(A series of read operations from the 1st bit part to the 8th bit part of registers 8R1 and SR2 is called a sense. In this embodiment, the 1st to 9th senses are executed.) CAL 1 is an absolute value subtracter and the above-described Selector 5) CLl
The outputs from 5EiL2 and 5EiL2 are compared, and the smaller value is subtracted from the larger value to generate an output as shown in Figure 5.

S/G is an adder which sequentially adds the outputs from the subtracters and generates an added output for each sense as shown in FIG.

As described above, since the same image pattern as the image pattern formed on the photosensitive sections 15-1 to 15-8 of the sensor 15 is formed on the predetermined eight consecutive photosensitive sections of the sensor 16, The above-mentioned addition output based on the charges accumulated in the photosensitive portions of the sensor 16 on which the same pattern as the imaged pattern of the sensor 15 is imaged becomes almost zero. Sensor 15 on 16-8
Assuming that the same image pattern is formed on the photosensitive sections 15-1 to 15-8, the digital values of the corresponding bit sections of registers SR1 and SR2 will show the same value, and the The result of the above subtraction and addition is zero. Furthermore, if the same image pattern as that of the sensor 15 is formed on the photosensitive parts 16-2 to 16-9 of the sensor 16, the addition output of the second sense becomes zero, and similarly, the addition output of the second sense becomes zero. The addition result obtained by sensing the photosensitive portion on the sensor 16 on which the same image pattern as the image pattern is formed becomes zero. Therefore, by detecting the sense number whose addition result is zero, the imaging position of the image pattern on the sensor 16 can be determined. Also, as mentioned above, when focusing, the photosensitive parts 16-5 to 16-1 (
Since the same pattern as the image pattern of the sensor 15 is formed on S-12, zero is output at the fifth sense when in focus, so the sense number when the above addition result becomes zero is and sense number when in focus (
The difference from the fifth) represents the amount of deviation from the in-focus state.

MIN detects the above output of the adder S and G, detects zero (minimum value) among the above added values at each sense output from the adder, and outputs the output signal T when the minimum value is detected. A minimum value detector is configured to generate the signal T and transmit the signal T to the latch LCH. The launch LCH is a binary counter CN
The output terminal G of the counter CN2 is connected to the input terminals D1-D4, and the output state of the counter CN2 is latched in response to the output signal T.

The counter CN2 connects the clock terminal to the counter CN.
The counter CN1 is connected to the output terminal C of the counter CN1, and the counting operation is performed in response to a change in the signal from the output terminal C of the counter CN1 (from the Hi signal to the Lo multiplication signal. Therefore, the output of the counter CN2 is the signal at the end of each sense. Each time, the output state shown in Figure 5 is shown.As mentioned above, the latch circuit receives the signal T from the minimum value detector.
In order to latte the output of counter CN2 in response to
During each sensing process, the output of the counter CN2 when zero (minimum value) detection is performed is latched. Therefore, the digital value corresponding to the sense number when the added value is the minimum (zero) is held. As mentioned above, when focusing, these registers SR1, 8R2, selector +:
vL1, 5BL2, counter CM2, subtractor CAL
A focus detection circuit is constituted by adder S, G1, minimum value detector M, and latch circuit LCH.

M is a motor as a driving means for driving the photographing lens and adjusting the distance based on the digital value latched in the latch circuit, and this motor is a transistor Tr.
It is driven by a drive circuit consisting of 1-Tra.

Steps 3 to 6 are inverters, A3 is AND gate, OR
2. OR4 is an OR gate, and these elements supply forward and reverse rotation signals for the motor M to the drive circuit based on the digital value as the distance information stored in the latch circuit LCHK, and control the distance adjustment operation by the lens 12. A control circuit is formed. Reference numeral 22 denotes a contact piece that moves in conjunction with the lens 12 and indicates a position corresponding to the position of the lens 12. 2
Reference numeral 1 designates a comb-tooth brush contact that comes into contact with the contact piece 22, and when the contact piece 22 slides on the contact piece 21, a pulse is generated.

The PD uses a light receiving element installed near the sensor 15 to detect the average amount of light received by the sensor 15 and performs AGC.
This is a detection light receiving element that outputs a signal.

CD is a drive circuit that generates drive pulses such as the clock CLK and controls the sequence of the entire device and the accumulation time of the sensor.

Only one selector SEL 1 is shown in the figure, but in reality, registers 5R1-1A, 5Ri-2
Two pits are provided for outputting the information of each pit of 5R1-1 and 13R1-2 in parallel according to the input of the counter CN1. Therefore, a 2-bit digital value as accumulated charge information of each photosensitive portion of the sensor is outputted next time. Also, like the selectors 5Eir and 1, there are actually two selectors SEL2, one for 5R2-i and one for 5R2-2.

FIG. 6 is a circuit diagram showing an embodiment of the drive circuit shown in FIG. 4. In the figure, CG is a pulse generator, CN3 is a 3-bit counter, DEC is a 3-8 line decoder, and plate is P
At LA, at the timing shown in FIG. 7, a driving pulse φ1 is applied to each sensor 15 and 16 shown in the sensor part 2o in FIG.
．． φ2. φR (here, the sensor is assumed to operate with a two-phase clock) is output to operate the sensor φ, and a sampling hold pulse SA is output to the AD converter AD, and the clock C1, Output +K.

It is assumed that the AD conversion time of the AD converter in FIG. 4 is approximately twice as long as the s7M pulse. Therefore, after the sensor outputs the output VOOT, it is sampled with the S/H pulse and AD converted, and digital information can be stored in the shift register SR1 at the next rising edge of the clock CLK.

5WiQ is a switch as a mode switching means that is connected to terminal O1 in natural light mode and terminal U in auxiliary light mode.

T1 is a connection terminal for the auxiliary light (S), and when the strobe is fully charged, T1 indicates Hl.

The PUE3 triggers the one-shot circuit ONj via the rear-OR gate 012 which outputs a signal upon power-on operation. Al O, l 1 is an AND gate that constitutes a switching gate between natural light mode and auxiliary light mode. When in auxiliary light mode (switch SW10 is on terminal U side), the AND gate A10 is connected to the charging completion signal from terminal T1. It outputs Hl in response to a pulse from the shot circuit ONi, and outputs Hl in response to a pulse from the one-shot circuit ON1 in the natural light mode.

FF1 is a flip-flop (referred to as FF'), and the n
is set in response to Hl from AID (Antogame), and sets the ζ output to Hl, transmitting a strobe trigger signal to terminal T3 and triggering the strobe. Hl of the AND gate A11 and FF, Hl of FF1 are applied to the D input end of the D-type FF, FF2 via the OR gate 011. The FF
2. Determine the output state according to the signal applied to the D input terminal in synchronization with the sensor drive pulse φ2. Accordingly, with the above configuration, the j5D FF-FF2 outputs Hl from the ζ output when the power is turned on in the natural light mode, and outputs El from the ζ output when charging of the strobe is completed in the auxiliary light mode. FF4 is an FF that is slightly reset by the pulse from the one-shot circuit ON1.
When the power is turned on, output is output from the output. A15 is the above FF, F'F4. With the AND gate connected to the ζ output of F'F2, when the ζ output of FF2 becomes <111 as described above, that is, the ζ output becomes LO, the shift pulse φT is set to Lo and the charge accumulation operation by the sensor 15.16 is performed. start.

A capacitor C is connected to the photodetector PD and constitutes an integrating circuit for charging the charge from the FD, and a transistor TR as an integration start switch is connected in parallel to the capacitor 〇. The transistor TR is connected to the Q output of FF2, and is turned off (by LO of Q of FF2), so that the integration operation by the above-mentioned integration circuit is started. CPl is a comparator circuit that compares the integrated output with the voltage level divided by resistors R1 and R5, and its output is connected to the above-mentioned FF'.
It is connected to the reset terminal of 1. Therefore, FF1 sets the Q output to LO at the output of the comparator circuit CP1, and sets the output of the AND gate A15, that is, φT t-Hl, to end the accumulation of the charges accumulated in the sensors 15 and 16. The integration circuit and comparison circuit constitute a timer circuit for controlling accumulation time. As is an analog switch that is turned on by the output of the FP1, and when this switch is turned on, it connects the resistor R2 to the electromotive resistor R6 and reduces the reference level for the comparison circuit cp1. R2 constitutes an accumulation time adjusting means for reducing the reference level and shortening the accumulation time.

FIG. 8 is a circuit diagram showing an embodiment of the adder BIG and the minimum value detector MN shown in FIG. 4.

The adders B and G have input terminals At, M2, and A20 to A2 connected to the output terminals of the subtractors CAI and I.
It has an adder ADD having input terminals B1 to B4 connected to the outputs Q1 to Q4 of the latch DLHj via 3. The adder ADD adds the digital values to the A and B input terminals and generates the above-mentioned addition output at the output terminals x1 to x4. The output terminals x1 to x4 of the adder ADD are connected to the input terminals D1 to D4 of the latch DLHi, and the latch latches the output of the adder in synchronization with the clock CLK. Further, the input terminals of the AND gates A20 to M23 are connected to the counter C.
It is connected to the output terminals A, B, and C of the counter M[, and is open when the count value of the counter CNl is 0 to 7, that is, when each of the above senses is executed, and the latch output is connected to the adder. It is transmitted to the input terminals B1 to B4 of.

In the above configuration, the addition unit ADD is the above A/toge) A20~
,, while A23 is open, that is, the counter (Jl count value is 0
7, the digital values output from the subtracter CAL i are added, and each time the first to ninth senses are completed, the addition output shown in FIG.

In the minimum value detection circuit M-N, DLH2 is a latch, and the outputs Q1-Q4 of the latch are connected to the data selector 5F.
Connected to the input end of iL20. The output of the adder S/G is also input to the data selector, and the output of the adder or the output of the latch circuit DLH2 is selected and transmitted to the latch circuit DLH2. The latch circuit DLR2 latches the input signal every time the signal changes from Hl to Lo at the C output terminal of the counter CN1, that is, every time the first to ninth senses are completed.

022 is an OR gate connected to the output G of the counter CN2, and this gate outputs Lo until the first sense ends, and outputs H1 after the second sense. Hl of the OR gate 022 is input to the selector 5EL20 via the OR gate 021. The or gate 02
1 is the adder S G that is input to the selector 8EL20.
A selection signal (
In the above configuration, the latch D
The digital value accumulated and added by the adder SG at the end of the first sense is latte into LH2.

A25 selects the output of the latte circuit: oi and R2 which is input to the selector EIKL20, and outputs the same latte circuit D.
This is an AND gate that outputs a selection signal (Hl) for returning to LH2.

COM compares the output of the adder and the output of the latch circuit DLH2, and when the output value of the adder > the output value of the latch circuit, outputs Hl from the a output, and if the output value of the adder ≦ the output value of the latch circuit. At times, Hl is output from the b output. Comparator CO
M compares the accumulated addition value at the end of each sense with the contents of the latch circuit, and only when the output value of the adder ≦ the output value of the latch circuit, Hl is input from the OR gate 021. Output selector 8EL20
The output of the adder is transmitted to the latch circuit, and the contents of the latch circuit are updated to the output value of the adder. Therefore, the latch circuit latches the minimum value among the accumulated sum values obtained by the adder S G for each of the first to ninth senses.

A26 is an AND gate, one input end of which is connected to the b output end of the comparator COM, and the other input end is connected to the OR game (022). In this configuration, the AND gate A26 outputs H every time the b output of the comparator COM becomes Hl at the end of each sense after the first sense.
Output l and DFF.

Tell FF20. Therefore, D FF and FF2o also output the output signal T every time H1 is output from the comparator COM, and transmit the contents of the counter CN2 at that time to the latch circuit LCH as described above. Therefore, the latch circuit IJCH
is the counter C when the minimum added value is detected among the accumulated added values from the 1st to 9th senses.
The contents of N2 are doubled.

FIG. 9 is a circuit diagram showing an embodiment of a strobe as an auxiliary light means applied to the focus detection device according to the present invention.

In the figure, 101 is a power supply, 1o2 is a power switch, 1
03 is a booster circuit, and the output of the booster circuit is charged to a main capacitor 105 via a rectifier diode 104. 106 and 107 are bleeder resistors that divide the charging voltage of the main capacitor, and 108 is a bleeder resistor that compares the output of the bleeder resistor with a reference voltage VRef, and when the main capacitor is charged at a predetermined level or higher, it outputs Hl as a charging completion signal. The output comparator 110 is an LED for indicating charging completion.

125 is an auxiliary discharge tube for generating the auxiliary light.

121 is a resistor, 123 is a capacitor, and 124 is a transformer, and these circuit elements form the trigger circuit for the sub-discharge tube. Reference numeral 122 denotes a thyristor, which is turned on in response to Hl from the terminal T3 in FIG.

Reference numeral 126 denotes a main discharge tube for flash photography, and the discharge tube 126 is triggered by a main light emission trigger circuit consisting of a resistor 115, a capacitor 117, and a transformer 11B to emit flash light. Reference numeral 116 denotes a thyristor for operating the main light emission trigger circuit, and the thyristor operates the above-mentioned trigger circuit in response to an on signal from a normal synchro switch of the camera inputted through the terminal T2. 11
1 is an inverter, 112 is a transistor, and these circuit elements constitute a safety circuit that allows the above-mentioned Cyrisk-116 to be turned on only when the output of the comparator 108 becomes Hl.

127 is a thyristor connected in series to the discharge tubes 126 and 125;
It turns on when triggered and enters the ionized state.
A flash of light from the discharge tube is started.

135.129 is a resistor, 130 is a capacitor, 134
Ha sire! - constitutes a known commutation circuit for stopping flashing by the discharge tube. Hl is applied from the comparator cpz of FIG. 6, which is generated at the upper terminal T4, and in response to H1, the circuit turns on and performs a commutation operation. Further, the thyristor 164 is turned on even when a light emission stop signal from a normal dimming circuit is applied to the thyristor 164 through the diode 143 and the terminal T5, and the amount of flash light emitted by the main light emission reaches a value that guarantees proper exposure. Performs a commutation operation to stop the flash.

169 is a capacitor, 140 and 141 are resistors, 138
is a diode, and 137 is a transistor. These circuit elements discharge the charge in the capacitor 139 during flash light emission through the discharge tube 125 or 126, Cyrisk-127, diode 158, and resistor 141, and the transistor 137 during this discharge time. is turned off and terminal T4.
A safety circuit is configured that allows the commutation circuit to respond to the light emission stop signal input to T5.

Next, the operation of the embodiment of the present invention shown in FIGS. 2 to 9 will be explained.

First, the auxiliary light mode will be explained.

In this mode, switch 5W10 in FIG. 6 is connected to terminal U. Assuming that charging of the strobe is now completed, Hl is applied to the terminal T1. When the power switch (not shown) of the camera is turned on in this state, a power-up clear signal is output from the PUC, and the one-shot circuit ON1 is activated as described above (FF, FF2...
FF4 is set to ν. Further, the pulse from the one-shot circuit sets FF'1 via AND gate A10, and Hl is output from the Q output of FF1. The H1 turns on the SIRISK-122 shown in FIG. 9 through the terminal T3, and the trigger circuit (125, 124) is activated to cause the discharge tube 125 to generate a flash of light, illuminating the subject.

On the other hand, the Q output (Hl) of the FF1 (FIG. 6) is transmitted to DFF and FF2 via the OR gate 011, and the
F2 outputs Hl from the Q output and Lo from the Q output.

Since the LO from the enable output of the 'FF2 is transmitted to the AND gate A15, the AND gate A15, which had been outputting H1 up to that point, outputs LO in synchronization with the flash light emission. (
FF4. In the initial state, FF2 is reset when the one-shot circuit 01J1 is activated by the PUC, and A15 outputs H1 when the power is turned on. ) The output of A15 is the sensor 15 in Fig. 4.
．． 16 shift pulses φT, and the above φT is L
By becoming υ, the sensor 15, 16 exhibits an accumulation operation of the image pattern to be imaged.

Also, at this time, the Q output LO of FF2 turns off the run sister TR (9) (FIG. 6), so the capacitor C starts charging with the output current of the light receiving element FD shown in FIG.

Charging of capacitor C is started as described above, and the charging level is set to the reference level determined by resistors R2, R5, and R1, /I/ (analog switch As is turned on by Q output (Hl) of FF'1). (The resistor R2 acts as the reference level determining factor.) When the comparator CP1 outputs Hl.

The Hl from the cp1 is transmitted to the diode 142 in FIG. 9 via the terminal T4, turning on the thyrisk-134, operating the above-mentioned commutation circuit, and turning off the thyrisk-127 in a known manner. The flash light emission by the discharge tube 125 is stopped. Also, Hl from the comparator CP1 is FFi
Reset FF1. Therefore, OR gate 011 also outputs LO (A13 also outputs Hl from comparator CP1).
Since the AND gate A11 also outputs LO, the inputs of the OR gate 011 all become Lo when the FF1 is reset. ), and as a result, the Q of FF2 jumps from LO to Hl. Therefore, A15 changes its output φτ to Hl again as shown in b of φT in FIG.
5. Send the accumulated charge in step 16 to the analog shift register in the sensor. Also, when the Q of FF2 becomes Hl, FF5 is clocked, and the q output becomes Hl, and the AND gate A12 is opened and the clock CLK (FIG. 7) is sent out from the AND gate A12. When the clock CLK is sent from the AND gate A12, FF4 is set and the Q output is set to LO, and the output φT of the AND gate A15 is set to LO again as shown in FIG. 7, and the accumulated charge is transferred to the register in the sensor. is prevented.

Through the above series of operations, the storage time control for the sensors 15.16 is executed, and the charges accumulated during the storage time are transferred to the registers in the sensors 15.16.

As mentioned above, the storage time of the image pattern by the sensor is the fourth
Since it corresponds to the time when the integrated value of the photocurrent from the photodetector FD in the figure reaches the reference level, the level of the image pattern signal (charge) accumulated in the sensor is low contrast regardless of the shooting brightness. The image level is automatically amplified and adjusted to an appropriate level even when using an image pattern of There is no need to perform similar level adjustment of the image signal. That is, as described above, since the contrast of the image itself increases when auxiliary light is used, a short accumulation time is sufficient as compared to when using natural light. Therefore, in the present invention, as described above, when using auxiliary light, the reference level of the integrating circuit is lowered compared to the natural light mode, there is no need for wasteful accumulation operation time, and the AP operation is speeded up. Wasted power consumption due to flash discharge is minimized.

As described above, when the image signal accumulation operation by the sensor is completed, the clock CLK is sent out as shown in FIG.
Signals corresponding to the charges accumulated in each photosensitive portion of the sensors 15 and 16 in the figure are converted into digital values by the AD converter AD and transferred to the shift registers SR1 and SR2 as described above. , SR2 are sequentially read out as described above, and each sense from the first sense to the ninth sense is executed. Also, the above subtraction (Fig. 5) and addition (Fig. 5) are performed for each sense. 5) is executed. Then, the adder B in the first to ninth senses
Among the addition outputs of the counter G, the minimum value is detected by the minimum value detection circuit M as described above, and the output state of the counter CN2 at that time is latched by the latte circuits I and CM.

As mentioned above, the contents of the latch circuit LCH are values representing the amount of deviation from the in-focus state, and in the in-focus state, the addition output at the time of the fifth sense is the minimum, and the value of the counter CN2 at this time is Output (D=o N=Q
Since F:=I G=0) is latched in the latch circuit, the lens is driven according to the amount of deviation and is automatically driven to the in-focus position.

That is, it is now in the front focus state, and the photosensitive part 1 of the sensor 16
Assuming that an image of the same pattern as the sensor 15 is formed on 6-3 to 15-10, the minimum value is detected as the addition output of adder B and G in the third sense, so the counter at that time Output of CN2 (D-0, E=1, F=Q
, G=Q) are applied twice to the latch circuit. Therefore, latch circuits I and CH output Q1 to Q4 respectively (', 1p
o+o), the OR gate 02 outputs LO indicating the front pin state, and the latch circuit enters the up-count mode. Also, the LO from the OR game) 02 is converted to Hl via the inverter E3 and transmitted to the base of the transistor Tr1 via the OR gate 04, turning off Trl and turning off pTr4 as well.

At this time, OR gate) O3 is Lo (02 is LO, A3 is also Lo, and Nando game) N4 is outputting -LO at the end of the 9th sense, so OR gate 06 is LO
to appear. ), so the transistor T
Since rz is on, Trs is also on. Therefore, the motor M rotates in the direction of arrow A and drives the lens 12 once in the direction of shifting from the front focus state to the rear focus state. When the lens moves in this manner, the brush contact 21 and the contact piece 22 generate a number of pulses corresponding to the amount of drive of the sliding lens during the movement of the lens, which is counted in the latching cycle Ha LCH. . As mentioned above, since the latte LCH is in the up mode, the pulses that are generated frequently as the lens moves are counted, and the counting result shows that the output of the two-way circuit is Q1 to Q, 4 = 0.0
, 1, 0, Antogame) A3 outputs H1, and sends H1 to OR gate o3. o4 to the tetran sister Tr1. Trs, Tr+ to Tra are turned off, and the lens drive is stopped.

Now, as mentioned above, the contents of the latch based on the sense result are Q1
~Q, 4 = 0 mountain 0, 0, so when the lens moves toward the bin after 2 pulses, the contents of the latch will be Ql-4
4=0.0,1, O, and the lens moves toward the focus after two pulses, moves to the in-focus position, and completes the distance adjustment operation.

In this way, the lens is driven by the amount of deviation from the in-focus state latched by the latch circuit, and automatically shifts to the in-focus state. In the case of rear pin, the photosensitive part 16-6 of the sensor 16
Since the same pattern as the sensor 15 is imaged on subsequent photosensitive parts, the minimum value is detected after the sixth sense. Therefore, in this case, the contents of the counter are latched in the latch circuit with the output F or G of the counter CN2 being El, so Hl is output from the OR gate 02, the latch circuit enters the down-count mode, and the transistor Tr1 Tr4 is turned on, the motor rotates in the direction opposite to the front focus state, and the lens dynamically moves toward the front focus by the amount of deviation from the in-focus state.

When the lens is in focus, Hl is output from the AND gate A6 as described above, and H1 is applied as CNT4 to the AND gate A14 in FIG.
4 outputs Hl. (After execution up to the 9th sense is shown in FIG. 4) IJ4 outputs LO and Hl is applied to the other input of the gate A14 via the I/verter 11, so the AND gate A14 is CNT4
=H1K to output Hi. ) The one-shot circuit ONi is triggered in response to Hl from the gate A14. Therefore, after the lens is driven to the in-focus state, the accumulation operation and lens drive operation by the sensor are performed again.

Next, the case of natural light mode will be explained.

In this case, the switch 5W10 in FIG. 6 is connected to the 0 side. Therefore, AND gate A10 is held at 1, 0 (D), and even if I'UC is activated by turning on the power, FF'
1 holds the reset state. Therefore, the strobe is prohibited from emitting light, the analog switch A8 is turned off, and the reference level is set to a normal level higher than that in the auxiliary light mode.

Also, when the one-shot circuit ON1 is activated (by turning on the power), Hl is output from the AND gate A11, and H1 outputs H1 as described above (the Q output of DFF and FF2 becomes R1, the Q output becomes LO, and the output of A15 φT becomes LO and the storage operation by the sensor starts as described above, and when the charging voltage of the capacitor C by the output of the light receiving element FD reaches the above reference level, Hl is output from the comparator CPI.
When in natural light mode, the accumulation time of the sensor is regulated based on the normal reference level, the level is automatically adjusted to the correct value, and from then on, the focus position is adjusted by the lens in the same way as in auxiliary light mode. is executed.

As described above, in the accumulation time control circuit for the focus detection device according to the present invention, the accumulation time is shortened when using the auxiliary light with the above configuration, so that the focus detection operation can be speeded up. This is something that can be done.

In the embodiment, the light receiving element FD is used to obtain luminance information for storage time control, but the luminance information may also be obtained using the sensor 15 or 16 itself. In this case, an image is stored in advance by a sensor for a certain period of time, the stored signal level is stored in a storage means such as a capacitor, and a current based on the stored value is formed by a transistor or the like. It is sufficient to charge the capacitor C (Fig. 6) with the current.

Furthermore, although a strobe is shown as the auxiliary light source, it is of course possible to use a spotlight (normal lamp, etc.) as the light source.

In this case, an FF is provided that is set in response to Hl from terminal T3 in Fig. 6, and the switch for supplying power to the light is turned on by setting 9FF. The above-mentioned FF may be reset by

In addition, as another example of the accumulation time adjustment means shown in FIG. 6, instead of providing a switch As and a resistor R2, the Q output (Hl) of FFi is used to control the output voltage between the light receiving element FD and the capacitor C. It is also possible to provide a transistor that reduces the amount of light, so that the capacitor is charged more quickly when using auxiliary light than when using natural light. In addition, as another example, instead of providing the switch As and the resistor R2, a filter that is linked to the switch sw10 is provided in front of the light receiving element FD, and in the case of natural light, light is irradiated to the light receiving element FD through the filter,
The filter may be removed from the front of the light receiving element FD during supplementary light, so that the capacitor C may be charged more quickly during supplementary light than in natural light.

[Brief explanation of the drawing]

Fig. 1 is a waveform diagram for explaining automatic gain control, Fig. 2 is a configuration diagram showing the configuration of a camera system to which the present invention is applied, and Fig. 3 is a configuration diagram showing the principle configuration of the focus detection optical system. , FIG. 4 is a circuit diagram showing an embodiment of a focus adjusting device to which the accumulation time control circuit according to the present invention is applied, FIG. 5 is an explanatory diagram for explaining the operation of FIG. 4, and FIG. 4 is a circuit diagram showing an embodiment of the drive circuit shown in FIG. 7. FIG. 7 is a waveform diagram explaining the operation of FIG. 6. FIG. 8 is a circuit diagram showing an embodiment of the adder and minimum value detector shown in FIG. 4. Circuit Diagram FIG. 9 is a circuit diagram showing one embodiment of a strobe as an auxiliary light source. FD...Light receiving element C...Capacitor CPI...Comparison circuit AEi...Analog switch R2...Resistor 4'-16

Claims (1)

[Claims] It includes a light receiving sensor consisting of a storage type photoelectric conversion element that receives a subject image and accumulates a signal corresponding to the image, and an integrating circuit that integrates the amount of light from the subject, and outputs when the integrated output reaches a predetermined reference level. an accumulation time control circuit for a focus detection device, comprising: a timer circuit that generates a signal, prohibits the signal accumulation operation of the photoelectric conversion element, and adjusts the accumulation time of the photoelectric conversion element according to subject brightness; An accumulation time control circuit characterized in that an accumulation time adjusting means for shortening the time until the integrated output reaches the reference level is provided, and the means is activated when an auxiliary light is used.