JPS59101530U - チユ−ナの段間複同調回路 - Google Patents

チユ−ナの段間複同調回路

Info

Publication number
JPS59101530U
JPS59101530U JP20237682U JP20237682U JPS59101530U JP S59101530 U JPS59101530 U JP S59101530U JP 20237682 U JP20237682 U JP 20237682U JP 20237682 U JP20237682 U JP 20237682U JP S59101530 U JPS59101530 U JP S59101530U
Authority
JP
Japan
Prior art keywords
tuner
tuning circuit
double tuning
interstage
interstage double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20237682U
Other languages
English (en)
Japanese (ja)
Other versions
JPH028437Y2 (enrdf_load_stackoverflow
Inventor
正喜 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP20237682U priority Critical patent/JPS59101530U/ja
Publication of JPS59101530U publication Critical patent/JPS59101530U/ja
Application granted granted Critical
Publication of JPH028437Y2 publication Critical patent/JPH028437Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Circuits Of Receivers In General (AREA)
JP20237682U 1982-12-24 1982-12-24 チユ−ナの段間複同調回路 Granted JPS59101530U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20237682U JPS59101530U (ja) 1982-12-24 1982-12-24 チユ−ナの段間複同調回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20237682U JPS59101530U (ja) 1982-12-24 1982-12-24 チユ−ナの段間複同調回路

Publications (2)

Publication Number Publication Date
JPS59101530U true JPS59101530U (ja) 1984-07-09
JPH028437Y2 JPH028437Y2 (enrdf_load_stackoverflow) 1990-02-28

Family

ID=30427847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20237682U Granted JPS59101530U (ja) 1982-12-24 1982-12-24 チユ−ナの段間複同調回路

Country Status (1)

Country Link
JP (1) JPS59101530U (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5356716U (enrdf_load_stackoverflow) * 1976-10-15 1978-05-15

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5356716U (enrdf_load_stackoverflow) * 1976-10-15 1978-05-15

Also Published As

Publication number Publication date
JPH028437Y2 (enrdf_load_stackoverflow) 1990-02-28

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