JPS5897031A - Flash photographing device - Google Patents

Abstract

PURPOSE:To shorten flash photographing wait time for a short-distance subject and to secure the enough amount of flashing for a long-distance subject, by setting a charging level according to the distance of a subject. CONSTITUTION:A light emitting circuit for distance measurement consists of a capacitor 6, discharge tube 7, trigger circuit 8, etc. Further, a transistor 24, resistances 21-23, etc., constitute a charge completion level setting circuit. Then, when a subject is relatively at short-distance, the charging level of a main capacitor 10 is set relatively low and flash photograph is held in readiness in a relatively short time. For a long-distance shot, the charging level is set high and the accurate amount of flashing is secured. Thus, flash photographing wait time for a short-distance subject is shortened and the sufficient amount of flashing for a long-distance subject is secured.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention detects the charge level of a flash photography device, particularly a main capacitor, and generates a charge completion signal when the charge level of the main capacitor reaches a predetermined value, thereby allowing the camera to The present invention relates to a flash photography device that performs flash photography by switching the photography mode from natural light to flash photography.

In the above-mentioned floating type flash photography device, flash photography is prohibited until the photoelectric level of the main capacitor reaches a predetermined detection level, and flash photography is allowed only after the charge level reaches the predetermined detection level. Therefore, proper flash photography can be carried out at all times, which is very convenient.

On the other hand, in this type of flash photography, on the other hand, flash photography is prohibited until the main capacitor is charged to a predetermined detection level, resulting in drawbacks such as missed photo opportunities for flash photography. In other words, in conventional devices of this type, the charge detection level was set regardless of the subject distance, so the main capacitor could not be charged to a level that could guarantee a sufficient amount of flash for a close-range subject, for example. Because the camera is set to the correct setting, flash photography cannot be performed immediately, and flash photography is continued until the charge level of the capacitor reaches a value that guarantees a sufficient amount of flash for the above-mentioned appropriate amount of subject. had to wait.

The present invention was made in view of the above-mentioned problems, and includes a detection means for detecting a subject distance in the above-mentioned shop-style flash photography device;
A level setting means is provided for setting the charge detection level based on the distance value detected by the detection means, and when the subject distance is short, the charge detection level is set to a relatively low level and flash photography is performed. In addition to shortening the standby time for long distances, the charging detection level is set to a high level,
This ensures a sufficient amount of flash for distant subjects.

Next, a flash photography device according to the present invention will be explained.

The first factor is a circuit diagram showing an embodiment of a flash device constituting a flash photography device according to the present invention. In Fig. 1, 1 is a battery, 2 is a power switch connected in series with 1, 3 is a diode that connects the low-voltage battery 1, and 6 is a sub-capacitor for making the distance-measuring fixed electric current tube 7 emit light. -, 8 is a known trigger circuit that connects the sub-discharge tube 7 to 1J1-1, and these capacitors 6 and discharge tube 7
, the trigger circuit 8 constitutes a light emitting circuit for distance measurement. 9 is a main capacitor for causing the flash photography main discharge tube 13 to emit light, 10 is a known trigger circuit for triggering the main discharge tube 13 and the main thyristor 18, and 11 is a resistor for charging the main discharge commutation capacitor 14. , 17 is a resistor connected to the gate of the main thyristor 18 and the cando gate, 20
is a resistor connected between the gate and cathode of the sub-thyristor 19, and these circuit elements constitute a flash light emission and light emission stop control circuit for a dimming strobe. 50 is a comparator which is bleeded by resistors 21 and 22 to detect the voltage of the main capacitor 9, and outputs a charge completion signal when the charge level of the main capacitor reaches a predetermined potential.

24 is a transistor whose base is connected to the output of the OR gate 99 via a resistor 25, and whose collector is connected to the connection point of the resistors 21 and 22 via the resistor 23; rater 5
A charge completion level setting circuit is configured to increase the charge completion detection level based on 0. Said resistance 21°22
The charging completion detection level set by 1 corresponds to the charging level l of the main capacitor required to guarantee the supply of flash light to obtain the correct exposure for a subject at a relatively short distance (do~ds). The value is as follows. Also, resistance 2
When 3 is connected in parallel to 22, the charging completion detection level is such that when there is a subject at a distance greater than the distance 1ads above, the amount of flash is sufficient to obtain proper exposure for the distant subject. The amount of charge of the main capacitor required for Furthermore, the charging completion signal when charged to level l guarantees proper exposure for a subject having a subject distance of mds or more. a is the constant voltage VC sent out from the camera side by the first stroke? 4, 54 is a buffer amplifier (54) that outputs the voltage from terminal a.
The following pack 7A responds to I as the first stroke signal.
- A comparator that outputs a high level (hereinafter referred to as HL). These comparators and a buffer amplifier constitute a first stroke signal forming circuit. 52 is a resistor connected in series to a light emitting diode 53, and the light emitting diode 52 emits light according to the output of the comparator 50 to constitute a charging completion display circuit for indicating that charging is completed. 56 is a resistor connected to the terminal 1 and the collector of the transistor 41, and 55 is a converter 50.
is a resistor connected to the output of the transistor 41 and the pace of the transistor 41. # transistor 41 is comparator 50
From 1! In response to the completion signal, a mode switching signal forming circuit is configured to apply the constant voltage applied to the terminal a to the resistor 56 to supply the mode switching It current to the terminal a. PT is a phototransistor "-" which acts as a light receiving element for distance measurement and dimming. This transistor is disposed, for example, on the front surface of a strobe device case, and receives reflected light from a flash.

24 is a known constant voltage circuit whose output is the reference voltage (hereinafter referred to as ref voltage) of the comparator 51.50.
give. Also, the output of the constant voltage circuit is the film sensitivity input volume 61. It is pre-pleated by resistors 72, 71, 70 and provides a ref voltage to comparators 73, 74, 75.

57.58, 59.60 are integrating capacitors that integrate the light flow of the phototransistor 23, 142°143,
144 is a comparator for measuring and converting high resistors for discharging connected to the integrating capacitors 58, 59, and 60, respectively, and the outputs thereof are connected to the AND gates 82 and 82, respectively.
It is connected to 83.84. The other input of the AND gate is connected to the input terminal of the output trigger circuit 8 of the monostable multivibrator 130 (hereinafter referred to as one shot) and to the input terminal of the OR gate 800. Said one shot 130 Fi) Activates the rigger circuit 8 to trigger the sub-discharge tube for distance measurement, and also performs the ant game) 82
, 83.84 are turned on and the comparator 73.7
A distance measurement signal forming circuit is configured to output a distance measurement operation signal for transmitting the output state of 4.75 to storage circuits (hereinafter referred to as latch circuits) 85, 86, and 87, respectively. The comparator 51 acts as a latch signal forming circuit that controls the operation of the latch circuits 85, 86, 87.
outputs the HL multiplied signal in response to the HL multiplied signal input to the latch circuit during the time when HL is output from the comparator 51, and the output of the HL multiplied signal comparator 51 is at a low level (hereinafter referred to as LL). ). 76, 77, 78 are AND gates, and the output of each AND gate is connected to the base of transistor 62, 63, 64 via resistors 65, 66, 67. The collectors of the transistors are connected to capacitors 58, 59, and 60, respectively, and the transistors and the AND gate constitute an integrating capacitor selection circuit for selecting the capacitors. Terminal C is a synchronization terminal connected to the camera's synchronization switch,
127 is an inverter, 132 is an input terminal of 10,000, which is connected to the inverter 127, and the other input terminal is connected to the comparator 50.
AND gate 131 is connected to the output terminal of AND gate 132, and its input is connected to the output terminal of AND gate 132.
This is a one-shot circuit that outputs a one-shot pulse as a light emission start signal in response to the output of 32, and connects its output end to the AND gates 76, 77, and 78. These one-shot circuits 131 and anchors 13
2. Construct a light emission start signal forming circuit for starting flash light emission in the inverter 127 and operating the selection circuit. 80 is the or gate, 79 is the inverter,
69 is a resistor, 68 is connected to the inverter 79 via the resistor 69, and the integrating capacitor 57.58°59.6 is connected between the emitter and collector.
0, and the transistor, inverter, and OR gate constitute an operation control circuit for operating the integrating circuit only during flash light emission.

94.95.96 is ANDGATE, 105. 106,
107° is a light emitting diode connected to the output terminal of 94, 95 and 96.
It constitutes a display circuit. The light emitting diode 107 that constitutes the display circuit is a display element for displaying that the subject distance is short and the specified aperture is F.; 106 is a display element that indicates that the subject distance is medium distance and the specified aperture is wider than F. A display element 105 is for displaying ◆, which is the Fl on the side, and 105 is the Fl where the subject distance is long and the designated aperture is more open than Fl.
It acts as a display element to display that.

121 is a resistor 119.121 which bleeds its non-inverting input to the output of the buffer 54. A buffer amplifier is connected to the connection point 120, and the input torque of the non-inverting input terminal is directly outputted to the output edge of the buffer amplifier 121 (hereinafter referred to as buffer 121). 123 is an operational amplifier whose non-inverting input terminal is connected to the output terminal of the buffer 121, and a resistor 124 is connected between the output terminal of 7 and the inverting input terminal, and the non-inverting input terminal voltage is connected to the inverting input terminal of the amplifier. is output as is. 116. 117. 118 are aperture 9 information resistors connected to the non-inverting input terminals of the buffer 121, respectively; 113. 114. 115 and said resistors 116, 117, 1 in their collectors, respectively.
This is a transistor that connects 18. These buffer 121, operational amplifier 123, resistor 119 . 120
．． 116°117, 118 and transistor 11
3. Reference numerals 114 and 115 constitute an aperture information forming circuit that forms a flash aperture 9 information voltage that is transmitted to the aperture control circuit of the camera via a terminal. a resistor 116 constituting the circuit;
117. The resistance value of 118 is the resistance value of resistor 116. 117゜1
18 are connected in parallel to the resistor 120, the potential at the non-inverting input terminal of the buffer 121 is such that the aperture information voltage sent to the terminal becomes a voltage o representing the aperture value F, and the resistor 117 ．． 118 is connected in series with the resistor 120, the aperture information voltage becomes voltage v1 representing the aperture value F, and when only the resistor 118 is connected in parallel with the resistor 120, the aperture information voltage becomes Each resistance value is set to be 4, which represents the aperture value F. The resistance values of the resistors 119 and 120 are determined by the maximum aperture value (for example, FL, 0) of the lens in which the aperture information voltage is normally used.
The resistance value is set so that the voltage vl representing FNoPs tl - is smaller than .

160, 109, 98 are ad/gates, 90,
91°92.93 is an inverter 88.89 is an OR gate, and these logic elements are a latch circuit 85
Based on the self-answer of 86.87, a control circuit for driving and controlling a selection circuit, an aperture display circuit, and an aperture information forming circuit for the -period integral circuit is constructed. 125 and 126 are bleeder resistors connected to the output end of the Aki amplifier 123, and 122 has one input end connected to the connection point of the bleeder resistor, and the other input end connected to the output end of the buffer 121. The comparator, the bleeder resistor, and the amplifier 123 constitute a detection circuit that detects the open FNo. information of the lens on the camera side. The terminal 6 is connected to the open FNo information source on the camera side, and the detection circuit line is connected to the open FNo.
It is configured to detect the open FNo of the lens by detecting the value of impedance 2 of the No information source,
The comparator 122 outputs LL when the lens opening FNo is smaller than the specified calibration value F, that is, the lens is brighter than the aperture value F, and when the lens is darker than the aperture value, the comparator 122 outputs LL. Output l(L,

104 is an interlocking distance out-of-range warning light emitting diode, dli
This is a ground terminal.

Figure 2 is a circuit diagram showing one embodiment of the electrical circuit of a camera used with the flash device shown in Figure 1.
．． /, b/, C/, and 4/ are contact terminals connected to terminals b, c, and d of the flash device shown in the first diagram, respectively. 301 is a constant voltage source that outputs the constant voltage Vcy, AR is a non-inverting input terminal K11ll is connected to the output of the constant voltage source, and a monitoring resistor &1 is connected between the inverting input terminal and the output terminal. The operational amplifier is connected to the inverting input terminal 1' of the amplifier. If the potential lines of the non-inverting input terminal and the inverting input 4 of the amplifier are the same, the constant voltage Vcy is outputted to the terminal a' in this configuration. CF2. C
Ps shall have its (-) input terminal connected to the output terminal to the amplifier via a resistor.
The comparator/ζ-lator connected to the inverting input terminal of the comparator constitutes the comparator shadow mode switching circuit. VR is a variable resistor that is linked to the shutter dial and shows a resistance value that corresponds to the preset shutter speed.

is a fixed resistor as 7 Yatsu 1 second time condition *S for flash photography, Cs is a capacitor that forms a time-setting circuit with the resistor vR or aSS, and SW4 is a counter that is turned off in conjunction with the movement of the shutter front curtain. The switch, CP, is a comparator to which a reference voltage is applied to the input end via the resistor path -I R1? (1) and the input end is connected to the output end of the timer circuit, and Mgs is a shutter trailing curtain hold. These circuit elements constitute a shutter speed control circuit.The switching circuit 302 is connected to variable resistors VR and all forming the shutter speed control circuit, and the combinator-CP In response to LL from @, connect resistor &31 and capacitor C1, and in response to HL from CP, connect variable resistor VR4 and capacitor Cs.
Connect to.

Island A is an operational amplifier whose non-inverting input terminal is connected to the inverting input terminal to the amplifier A, whose inverting input terminal is connected to ground via a resistor Rulo, and a resistor ALL is connected in its return path. An amplifier is constructed to double the constant voltage Vcte.

SPD is a silicon photodiode for photometry, R1 is an operational amplifier having a silicon photodiode connected between its inputs 4 and a diode for logarithmic power in its return path, and the core amplifier constitutes a photometry circuit. ARI
has a diode D! between its input terminals. The output terminal of the amplifier is connected to the non-inverting input terminal of the amplifier. These hodisters and amplifier ARC are connected to the output end of the photometering circuit.
The temperature compensation circuit of the photometry circuit is configured using the following. This is an operational amplifier that connects a variable resistor VR1m and a capacitor C4 connected in parallel to its inverting input terminal and output glabella (S), and this amplifier constitutes a compensation circuit that compensates for flicker included in the photometric output. VR, is a variable resistor to which the preset shutter speed and film sensitivity information are set, ARI is an operational amplifier having first and second inverting input terminals, and the first inverting input terminal of the amplifier is connected to the variable resistor. ■It is connected to R3 and the amplifier AR, and the second inverting input terminal is connected to the terminal b'.
Calculation of information input manually to the first input terminal in response to HL (
An arithmetic circuit is constructed that performs daylight calculation) and performs calculation of information input manually to the second r input terminal in response to LL (flash calculation). VEL4 is the maximum aperture of the attached lens.
The variable resistor for setting the No information, ABC is the variable resistor v
This operational amplifier is connected to R4 and has a resistor R31 connected in its feedback path, and constitutes an open aperture signal forming circuit that forms a voltage corresponding to the open aperture value. 8R and 8 are operational amplifiers that calculate the output of the amplifier A and AFL, and M is a display meter. Rs4 is a resistor having impedance Z, R34b is a fixed contact of the resistor, and RHa is a movable contact that operates in conjunction with the variable resistor VR4. The movable contact connects to the contact R14b when the open aperture value set to the resistor VB is smaller than F,
When the value is larger than PI, contact R54b is opened, and an open aperture information source is configured that transmits open FNo information to terminal b' as an impedance value. SWX is a synchro switch. The aperture control circuit performs aperture control based on the output of the APCCd amplifier AR, and this circuit adjusts the aperture to the aperture F number when input aperture information is smaller than the aperture F No. used.

The aperture control circuit is described in Japanese Patent Application Laid-Open No. 52-50722.
Since it is described in detail in the specification of the above issue, the explanation thereof will be omitted. In addition, the circuit portions surrounded by dotted lines in FIG. 2 are integrated circuits, and the circuits are powered by the first stroke, and each circuit is put into operation.

Next, the operation of the flash device according to the first aspect of the present invention will be explained. First, a case will be described in which photography is performed using a lens whose open FNo value is smaller than the above-mentioned aperture value F3.

When power switch 2 is turned on, the DC-DC The converter 3 operates and boosts the power supply voltage 1.

The boosted output is applied via the rectifier diode 5 to the illumination capacitor 9 via the rectifier diode 4, and the capacitor 9 is also charged.

Furthermore, before the first stroke of the camera release, a constant voltage is not applied to terminal a from the camera side, the output of the buffer 54 is at a low level, and the output of the comparator 51 is LL. ing. Therefore, Punto gate 97.98 also outputs LL and transistor 24
is in the off state. Therefore, the charging potential of the main capacitor 9 is detected by the resistor 21.22, and the charging potential of the main capacitor 9 is detected by the resistor 21.22.
When the charge level of the battery is charged at a relatively low level It, the comparator 50 outputs HL as a charge completion signal.

The light emitting diode 53 receives the HL from the comparator 50.
It lights up in response to the charging completion display 2. After the completion of charging is displayed in this way, when the first stroke of the release is performed, each circuit shown in FIG. Terminal 1 is transmitted. As a result, the output of the buffer 54 becomes a constant voltage potential applied to the terminal a. The constant voltage VCT from the camera side is set to a higher potential than the ref voltage from the constant voltage source 24, and the comparator 51 outputs HL in response to the output of the buffer 54, and the AND gate 12
HL is applied to all 8 input terminals. Therefore, AND gate 128 outputs HL, triggering one-shot circuit 130, and one-shot circuit 130 sends out a one-shot pulse. The trigger circuit 8 operates in response to the one-shot pulse, triggers the discharge 7, and a flash of light is generated from the discharge tube 7 (hereinafter, the flash of the discharge tube 7 is referred to as pre-flash). Since this is a flash for distance measurement, it is necessary to keep the flash level (light emission 1) constant, so the voltage at which the capacitor 6 is charged is set to a constant voltage.

When pre-emission is performed in this manner, the light reflected from the object by the flash is received by the phototransistor FT. If the amount of flash light emission is constant and the reflectance of the subject is constant, the photocurrent of the phototransistor PT has a charging current value that is inversely proportional to the square of the subject distance. -57 is charged.

That is, since the one-shot pulse is applied to the OR gate 80, the transistor 68 is turned off for the one-shot pulse width period, releasing the short-circuit state of the integrating circuit, and the capacitor 57 is turned off only for the one-shot pulse width period. It is charged by the charging current from the phototransistor PT. Furthermore, at this time, transistor 62
．． 63 and 64 are in the off state, and the photocurrent charges only the capacitor 57.

In this way, when the capacitor 57 is charged for the one-shot pulse width time (a certain period of time), the charging potential of the capacitor 57 becomes a voltage inversely proportional to the square of the subject distance.
A where the voltage consists of con/craters 73, 74, 75
It is converted into a digital value by a D converter.

Now, assuming that the subject distance is short do = dt (for example, 2 m from On), the charging potential of the capacitor 57 during the above pulse width time is
→The voltage applied to the input terminal is also at a high level.9, comparators 73, 74, and 75 both output HL, and the HL is transmitted to 82, 83, and 84. The AND gates 82, 83, and 84 are open in response to the one-shot signal and transmit the output state of the one-shot gate to the latch circuits 85, 86, and 87. is input to the leap to which HL from the comparator 51 is applied as described above) In response to ILK, t (as it is configured to output L, when the subject distance is d.~d1, AND GO) 82, Both latch circuits 85, 86, 87 output IL in response to the HL of input converters/ζ-lators 73, 74, 711, etc. via terminals 83, 84.

(When the subject distance is medium distance d1 to d (for example, 2 m to 4 m), the capacitor 570 charging voltage is the comparator 74's (→input terminal potential and co//crater-73's ()
→ becomes the intermediate potential of the input terminal potential, and the comparator 74.
75 outputs LL, and the state is latched by the latch circuit in the same way as in the short distance case, and HL is output from the latch circuits 86 and 87, and LL is output from 85. When the object distance is a speed ratio of 1ads to ds (for example, 4m to 8m), the charging voltage of the capacitor 57 is equal to the intermediate potential of the comparators 74 and 75 (→ the intermediate potential of the input terminal and the voltage, and the comparator 75 outputs HL. In this case, L is output only from the wrap circuit 87.

Furthermore, if the subject distance is shorter than ds, the speed ratio fill (e.g. 8
m or more), the charging potential of the capacitor 57 is equal to or higher than the input shoulder potential of the comparator 75, and the output of the circuit maintains LL.

As described above, the charging voltage of the capacitor 57 is AD converted, a signal corresponding to the subject distance is latched in the latch circuit, and at the same time, after the one-shot pulse width time, the AND gates 82, 83 and 84 are closed. , information input to the latch circuit is prohibited, and from now on the latch circuit is connected to comparator 5.
The output state is held until the output of 1 becomes LL.

Further, after the one-shot pulse width time, the transistor 68 is turned on, the charge in the capacitor 57 is reset, and the integration operation by the integration circuit is prohibited. Incidentally, the amount of light emitted by the pre-flash for distance measurement rounding may be small, and since the discharge time is regulated to 10 us or less, the one-shot pulse width is also about 1 Qus.

Now, assuming that the object distance is short (d.about.dx), the launch circuits 85, 86 and 87 are both outputting (L) as described above. Therefore, the AND gate 94
HL from the company latch circuit 85 is applied to one input terminal of the circuit. Also, the other input terminal of the AND gate 94 is
(The HL from the controller 51 is applied, and the ant game) 94 outputs the HL and causes the light emitting diode 107 to emit light. Is it a small pattern? F. (for example, F8) is displayed. At this time, the HL of the latch circuit 85 is applied to the AND gate 95 via the #i inverter 90, converted to L, and the H of the latch circuit 86 is applied to the AND gate 96 via the inverter 91 and the OR gate 88. ,L is converted to Ll and applied,
The light emitting diodes 106 and 105 remain in the off state.

Father, 5 times mB5, 86.87 to 0HLti transistors 113, 114, 115 are turned on, aperture information resistor 116. 117. 118 to resistor 12
Connect in parallel to 0. That is, the latch circuit 85)
IL is applied directly to the base of transistor 113,
The transistor 113 is turned on, and the HL of the latch circuit 86 is connected to the AND gate 16 via the OR gate 88.
6, and also the HL of the latch circuit 87.
is also applied to one input terminal of AND gate 109 via OR gate 89. On the other hand, HL of the latch circuit 86 is inverted and applied to LL via the inverter 92, and the AND gate 98 outputs LL, so the inverter 108 outputs HL. For this reason, the aforementioned Antogame) 160. HL is also applied to the other human power of 109, and the AND gates 160 and 109 also send out HL and the transistor 11
4. 115 is also turned on.

In this way, the distance is 1m! In the case of (do - ds), transistors 113, 114, and 115 are turned on, and resistors 116, 117, and 115 are connected in parallel to resistor 120.

By connecting the resistors 116, 117, and 118 in parallel to the resistor 120, the output voltage of the AND 121 becomes V, and the potential of the inverting input terminal of the AND 1230 also shows V, and this voltage V is applied to the terminal. blc is output.

On the other hand, as mentioned above, since the output of the controller 50 is HL, the transistor 41 turns on, and the first
Based on the constant voltage Vc sent to the terminal a from the camera by stroke operation, φ9 current flows through the resistor 56, and the current i=N'cy/BI@(Vc-r
is the constant voltage sent from the camera side to the terminal 1 by the first stroke operation, and a current flows (the resistance value of the resistor 56), and this current value is detected by the camera's detection circuit, The camera mode has been switched from daylight to flash. That is, the current i! is passed through the terminal a' in FIG. V
c! /R1. flows into the terminal a, so that the output potential of the amplifier ARI becomes higher by the resistor R15Xi, and the comparators CP, CP, output LL.

As a result, the amplifier is switched to the flash calculation mode, and the switching circuit 302 is connected to the resistor R12 and the capacitor CI.
to form a flash seconds circuit. When the amplifier AR is switched to the flash operation, the voltage vo input to the terminal b' via the terminal S and the open aperture information from the amplifier ARs are calculated, and the step number aperture value based on V is calculated. Aperture value information is input to the aperture control circuit APCC.

Therefore, the camera mode is switched to flash mode, the shutter timer circuit is switched to flash mode, and the aperture control circuit is set to VV.
・Inputs. The voltage value ■・ is the aperture value F・(for example, F
8). As described above, after the aperture and subject distance are displayed on the light emitting diode 107 and the camera mode is switched to flash mode, when the second stroke of the release is performed, the camera's aperture mechanism operates and (- PCC, which enters the aperture control circuit, adjusts the aperture based on the voltage at the terminal.The aperture is adjusted to the specified aperture F (for example, F8) for flashing at close range, and the shutter front curtain moves. As the shutter front curtain runs, the camera's count switch 8Wa is turned off, and the flash shutter second timing operation is started, and the sync switch SWX is activated, and the LL signal is input to terminal C. The LL signal is inverted by an inverter 127 and output as HL to one input terminal of the comparator 50.
to l(L is applied to the other input terminal of the AND gate to which L is applied, the AND gate 132 outputs HL, and the one-shot circuit 131t-) liquor L, and the one-shot circuit 131 sends out a one-shot pulse. The one-shot pulse is transmitted to the trigger circuit 10, which activates the trigger circuit to turn on the thyristor 1B, and also supplies the flash discharge tube 13 to the trigger nozzle to cause the flash tube 13 to emit light and emit a flash for photographing. Further, the one-shot signal is transmitted to the transistor 68 via the OR gate 80 and the inverter 79, and the transistor 6
8 is turned off, the integration circuit ↓ is activated, and the ant game is turned off.
) is transmitted to one input end of 76.77.78.

A latch circuit 85 is connected to the other input terminal of the AND gate 76.
) IL of the latch circuit 86 is applied to the other input terminal of the AND gate 77 via an OR gate 88 , and IL of the latch circuit 86 is applied to the other input terminal of the AND gate 78 via an OR gate 89 . Since 1-IL is applied, the outputs of the gates 76, 78 are all 1 (L), and the transistors 62, 63, and 64 are turned on.

Therefore, in the case of a short distance, the capacitors 58, 59, and 60 are all connected in parallel to the capacitor 57. Since the capacitance of each capacitor is set so that when the capacitors 57.58° and 59.60 are connected in parallel, the capacitance of the integrating circuit will be a value corresponding to the aperture value F@. The light adjustment line fIv- as an integral circuit is set to a value corresponding to the specified aperture value.

As described above, the capacity of the integrating circuit is adjusted according to the specified aperture value, and in the process of performing the integrating operation, the capacitor is charged by the photocurrent of the phototransistor PT that receives the subject light from the flash. Voltage is comparator 7
3 (→When the terminal potential is reached, the comparator 73 outputs HL and applies it to one input terminal of the AND gate 81) I
Tell me L. Since 7 (Rus) from the one-shot circuit 131 is applied to the other input terminal of the AND gate 81, HL is output in response to the HL from the AND gate 81 comparator 73.Thus, the thyristor 19 turns on, discharges the charge in the commutation capacitor 14, reverse biases the thyristor 18, turns off the thyristor 18, causes the flash discharge tube 13 to stop emitting flash light, and the flash operation of the flash device ends.

As shown above, when the subject distance is short, ts3 diagram (a)
As shown, the aperture is set to F, that is, the small aperture side, and the light control condition is also adjusted to a value corresponding to RA P (1), and the flash operation is executed. End flash photography.

Next, a case where the subject distance is a medium distance d1%d will be explained. In this case, HL is output from the latch circuits 86 and 87 and LL is output from the latch circuits 85 by pre-light emission for distance measurement as described above. Previously, in this case, LL was output from the AND gate 94, HL was output from the AND gate 95, and LL was output from the AND gate 96, and the light emitting diode 1 was output.
06 emits light instead of 107, and the subject distance is d1%d,
It is a middle distance, and the writing is on the more open side than the above F.
1 (for example, F4).

The transistor 113 is turned off by the LL of the latch circuit 85, and the transistor 114.11b is turned on in the same way as the short distance described above.

In this case, the resistance is 117. 118 is connected to a resistor 120, and a voltage 1 which is 4 higher than the above voltage is outputted to the terminal. Since the voltage is a voltage corresponding to the aperture of 100 million Fl,
Aperture value F! The information is as above and the camera aperture is fI8n.
It is transmitted to the circuit APCC. Thereafter, when the second stroke of the release is performed, the aperture of the camera is adjusted to 1i1F1 based on the voltage from the 7 terminals as described above, and the flash is emitted by the flash discharge tube 13 and the amount of flash is An integration operation is performed by the integration circuit of the integration circuit, and the terminal voltage of the capacitor of the integration circuit reaches a predetermined value ((→
When the terminal voltage (terminal voltage) is reached, the flash light emission stops, the flash operation is completed, and the shutter time is adjusted using the flash time. In the case of medium distance, the latch circuit 85 outputs LL, so the AND gate 76 outputs LL, the transistor 62 is turned off, and the AND gate 77 outputs LL.
．． 78 outputs HL as in the case of the short distance described above, and transistors 63 and 64 are turned on. Therefore, in this case, the capacitor 59. is the capacitor 57.
60 are connected in parallel, the capacity of the integrating circuit is smaller than that in the case of a short distance, and one light condition for the light amount integration operation by the integrating circuit is set in accordance with the aperture value F1.

As described above, in the case of intermediate distances d1 to dl, the aperture value is Fl in the light emitting diode 106, the subject distance is d1 to d,
At the same time, the aperture is set to the aperture value F1 (on the open side) from the aperture value F at close range as shown in Fig. 3 (1), and the light control conditions are also set to the aperture value F. It will be set to the appropriate value.

Next, a case where the subject distance is a long distance d3 to d will be described. In this case, as mentioned above, LL is output from the latch circuits 85 and 86 and LL is output from the latch circuits 87 through pre-flash for distance measurement.
IL is being output. In addition, since the shooting lens is used with a small aperture F number, for example, a large aperture lens such as Fl, 0, etc., the aperture F number of the camera can be adjusted as described later.
The impedance of the information source is detected and the comparator 122 outputs LL.

That is, let the resistance value of the resistor 125 be R1, the resistance value of the resistor 126 be R, and the resistance value of the resistor 124 be Rs, and the terminal b' in FIG.
The impedance between and ground is set to 2, the voltage at the b terminal is also set to V, and the output of the amplifier 123 is set to ■・-resistance 125.
, 126, Vr m Yo
u? Show 1 Vou? x VAV(I A ) island. The condition for the output of the comparator 122 to be HL is Vr < Vmuma, so Vmma <-! ! L->
<1+shi)<VAV, and the result is x+R*
Z then z〉−&det al.−Z>C (constant value). Also, the impedance of resistor 1 B-sa is set smaller than C, so the open FNo.
If a lens is attached, the resistance aSS is
is opened, so the con/(Retani 122 outputs HL. Also, if a lens whose open FNo is smaller than F3 is attached, a resistor ILsa is connected between terminals b' and ground. Therefore, the comparator 122 is LL
Output.

Since the comparator 122 a LL is output in this manner, the AND gate 94 outputs LL. Further, since the output of the OR gate 88 is also LL, the AND gate 95 also outputs LL. The input of the AND gate 96 is the I- from the comparator 51 of the OR gate 88.
Since IL is input manually, the AND gate 96 outputs HL.

Therefore, if the subject distance is far, the light emitting diode 10
5 is lit, the subject distance is from d snow to d, and the aperture is F! Even more open than ', 1cl)p
, (for example, F'2).

As mentioned above, only the latch circuit 87 outputs HL and the comparator 122 LL outputs the full output, so the transistors Δ113 and 114 are turned off, and only the transistor 115 is turned off.

That is, the transistor 113 is turned off because the latch circuit 85 is outputting LL, and the AND gate 160 is
As mentioned above, since the OR gate 88 outputs LL, L
The transistor 114 is also turned off by the LL output from the AND gate 160. Furthermore, the AND gate 98 has 1.1 of the comparator 122. Since L is input, AND gate 98 outputs LL, and LL from gate 98 is inverted to HL by inverter 108 and applied to one input terminal of AND gate 109. An OR gate 89 is connected to the other input terminal of the gate 109.
Since )IL of the latch circuit 87 is applied via the gate 109, the AND gate 109 outputs HL, and the transistor 115 is turned on by the IL from the gate 109. In this way, when the subject distance is long, the tiger/jis I'-116 and 117 are turned off and the transistor 1 is turned off.
Only the resistor 15 is turned on, only the resistor 118 is connected to the resistor 120, and the four resistors are connected to VmC, which has a higher potential than the voltage v1.
Aperture') Corresponds to III Fs. ) is output, and the voltage v1 is transmitted to the aperture control circuit APCC of the camera.

After that, when the second stroke of the release is performed, the aperture value FtKm of the camera is determined based on the voltage VS across the terminal as described above, and the aperture value FtKm is determined based on the flash light emission by the flash discharge tube 13 and the flash amount integration circuit. When the integral operation is performed and the terminal potential of the capacitor of the integrating circuit reaches the terminal potential of the comparator 73 (→terminal potential), the flash light emission stops, and at the same time the flash operation ends, the shutter time reaches the flash time. In this case, since the latch circuit 85 outputs LL and the OR gate 88 outputs LL as described above, the output of AND gates 76 and 77 becomes LL,
Only the AND gate 78 is H as in the short distance case described above.
Output L. Therefore, when transistors 62 and 63 are off and transistors 64 are on, only the capacitor 60 is connected in parallel to the capacitor 57, and the capacity of the integrating circuit is even smaller than in the case of the middle distance, which causes dimming in the light amount integration operation by the integrating circuit. The conditions are set according to the aperture value F.

As described above, when the appropriate amount fidm~d3, the aperture value of the light emitting diode 105 is F! , the subject distance is d! ~d
3, and the aperture value F at the above-mentioned medium range, as shown in No. 3 Kasumi (a), and the attack value F of the open reconnaissance,
The aperture value F3 is set, and the light control condition is also set to a value corresponding to the aperture value F3, and flash photography is executed.

Next, a case where the subject distance is d or more will be explained.

In this case, the latch circuits 85, 86, 87 both output LL due to the pre-emission of rounding for distance measurement as described above.

Therefore, the inverter 93 outputs HL and applies the HL to one input terminal of the AND gate 97. Further, the HL from the comparator 51 is applied to the other input terminal of the AND gate 97, and the AND gate 97 changes its output to HL in response to the HL from the inverter 93. The light emitting diode 104 is turned on via the HLU OR gate 99 from the AND gate 97 to indicate that proper exposure cannot be obtained at the charge level l.

The HL output through the OR gate 99 is applied to the base of the transistor 24, and
Turn on. As a result, the resistor 23 is connected in parallel to the resistor 22, and the charging completion detection level is set high and shifts from the level I to the level ■. When the charge level shifts to 1, the charge completion signal (HL times signal) output from the comparator 50 disappears, and LL is output from the comparator 50. Therefore, the light emitting diode 5
3 goes out and transistor 41 turns off,
The mode switching current flowing through terminal 1 also disappears, the camera's photography mode is switched to daylight photography, and flash photography is prohibited.

After shifting to the level (2) in this manner, the charging of the main capacitor 9 progresses, and when the charging level of the main capacitor 9 reaches the above-mentioned level (2), the comparator 50 again outputs a charge completion signal (HL multiplication signal). Therefore, if the first stroke of the release is held, the AND gate 128 outputs Hl in response to IL of the comparator 50, triggering the one-shot circuit 130 again, and again performing the distance measurement operation as described above. The discharge tube is made to emit light, a distance measuring operation is performed by pre-emission, and latch circuits 85, 86 .
The contents of 87 are determined.

Furthermore, the transistor 41 is turned on again, and the camera mode is again switched to the flash photography mode. Now, assume that the subject distance remains the same as the previous distance measurement, that is, d or more. In this case, as described above, the latch circuit 85,
All contents of 86.87 output LL. Therefore, the transistor 113 is turned off and the OR gate 88.
One input terminal of 89 has L from latch circuit 86, 87.
L inputs. Also, as mentioned above, since the comparator 122 outputs LL, the other human input signal of the above-mentioned ORG)88.89 is also LL, and the ORG)88.
89 is LL for anime) 160. Call 109. AND gate 160, 109 tiML, to output LL by transistor 114. 115
is also turned off. Therefore, in this case, the resistors 120, 119
A voltage Vs regulated by (corresponding to FNoFH which is smaller than the open FNo of a normally used lens) is output to the quadruplets.

After emitting a flash for re-measuring the distance in this way, when you perform the $2 stroke of the release, the amount of flash light for flash photography "Light is emitted from the discharge tube 13" in the same manner as after the $2 stroke described above. At the same time, the aperture of the camera is adjusted to the above v.
3, the aperture value is adjusted to F. At this time, when the aperture value FAvo of the lens in use is larger than F3, the aperture value is determined as the aperture value FNoKm.

Also, as mentioned above, or game) 88, 89 and latch circuit 85
Since outputs LL, AND gate 76.77.7
8 also outputs LL, transistor 62.63.6
4 is off. Therefore, if the subject distance is ds or more, the capacitor capacity of the integrating circuit is 57.
Since the capacitance of the capacitor 57 is set to a value corresponding to the aperture number normally used, the light control conditions are also set to a value corresponding to the aperture value during flash photography. That will happen.

Furthermore, the above-mentioned resistor 119. Set the resistance value of 120 to a value slightly larger than the open PNo of the commonly used lens or the corresponding F.
If the capacitor 570 is set to correspond to the same value as F No. and the capacitance of the capacitor 570 is set to a value corresponding to the above F No., when the subject distance is 41 or more, the aperture value at the edge will always be the same as the open F No. When the aperture value is adjusted to a value slightly larger than the maximum aperture value, the Km light condition is also set to a value corresponding to the above-mentioned FNoK, so that it is possible to always obtain an appropriate image display.

As described above, in the flash photography device according to the present invention, when the subject distance is d3 or less, which is relatively short distance 11, the charge level of the main capacitor is set to a relatively low level I,
In addition to completing preparations for flash photography in a relatively short time, the charge level can be set to a high level if the distance is longer than the above distance @ds where the flash amount at the charge level IK of the main capacitor is out of the interlocking range. Since it is transferred to the irises, it is possible to always achieve an accurate flash amount W*.

This is the case when the latch circuits 85, 86, and 87KLL are latched, but if the subject moves and the subject distance is less than ds when remeasuring the distance, the latch circuits 85, 86, and 87KLL will be latched according to the subject distance at the time of remeasuring the distance. Of course, the output state of the circuit is determined, and the aperture value is determined based on the subject distance as described above.

Next, a case will be described in which photography is performed using a lens with an aperture value larger than the aperture of 900 million F. In this case, the target distance is 'near 111 (d・~ds) and middle distance 4
1 (dt to da), the aperture and flash amount are controlled in exactly the same way as when the lens used has an open aperture value smaller than the aperture value F, so a description thereof will be omitted. If the subject distance is 48 or more, open the aperture to F.
The flash photography will be executed under the control of "No".

That is, in this case, since the latch circuit 86 outputs LL in the distance measuring operation by pre-emission, IL is applied to the first input terminal of the AND gate 98 via the inverter 92, and the AND gate 98 The output of the comparator 122.51 is applied to the other input terminal of the . The comparator 51 outputs HL as described above, and since a lens with an open FNo larger than F is used as described above, the comparator 1224HLli- is output, and all of the AND gates 98 The human signal becomes HL,
AND gate 98 sends out HL. HL from the gate 98 is transmitted to the transistor 24 via the OR gate 99, turning on the transistor 24. Therefore,
In this case, as described above, when the charge level shifts from I to I and the charge level of the main capacitor 9 reaches 1, the flash tube 7 is caused to emit light again to perform a pre-flash to perform a distance measuring operation. As a result of the distance measuring operation, when it is again determined that the subject distance is d or more, the contents of the latch circuit 85 are held at LL. Therefore, as mentioned above, the AND gate 98
The HL is sent out, and the HL is inverted to LL by the inverter 10B and transmitted to the AND gates 160 and 109.

Therefore, if the subject distance is 41 or more, AND gate 16
0. 109 is a transistor 114 for outputting LL. 115 is turned off, and the transistor -
LL from the 1134 latch circuit 85 turns off the paper.

Therefore, in the same way as in the above case, a voltage Vs corresponding to the aperture value Fs is sent to the terminal, and the second strike cylinder causes the flash tube 13 to emit light as described above to execute flash photography and adjust the aperture of the camera. The control circuit APCC fixes the go of the camera based on the voltage v1. As mentioned above, the aperture value of the camera lens used is larger than F, that is, the aperture value is also large, so the camera's aperture mechanism adjusts the aperture to the maximum aperture value. As a result, $3 figure (b)
If the subject distance is d or more, the aperture is open to F.
FhvoKtA is determined. In addition, at this time, AND gate 7
LL of the latch circuit 85 is transmitted to the AND gate 7.
Since the HL from the comparator 122 is transmitted to 7°78 via the OR gates 88 and 89, the transistor 62 is off and 63.64 is on, and the capacitor 59.60 is connected to the capacitor 57. ing. Therefore, when the subject distance is d or more, the capacity of the integrating circuit, ie, the light control condition, is fixed to a round value corresponding to the aperture value F1 as described above. 'i43 As shown in Figure (b), the aperture value F1 and F ATO are not the same value, but F
Since Avo takes a value between the above F and F, the dimming conditions are also almost constant directly according to FAVO.

As described above, in the flash photography device according to the present invention, the charging level can be set according to the subject distance.
It is possible to shorten the flash photography waiting time for close-up subjects.

[Brief explanation of drawings]

Section 1 is a circuit diagram showing an embodiment of a flash device constituting a flash photography device according to the present invention, and FIG. 2 is a circuit diagram showing an embodiment of an exposure control circuit in a camera used with the flash device shown in FIG. 1. 3(1) and 3(b) are explanatory diagrams for explaining the operation of the apparatus shown in FIG. 1. 21, 22.23--Resistor, 24--Transistor 50--Comparator 57.58.59.60--Capacitor 73.74.
75・-konno (lator-85, 86, 87... latch circuit

Claims (1)

[Claims] Distance detection means for detecting a subject distance and the distance detected by the means in a flash photography device that switches the shooting mode of a camera from a natural light mode to a flash mode using a detection signal that detects the state of charge of a flash capacitor. 1. A flash photography device characterized by comprising charging and level setting means for setting the charging level based on information.