JPS5896688A - Device for converting time axis of sound signal - Google Patents

Abstract

PURPOSE:To obtain high quality sound signal free from discontinuous parts and fluctuation of pitch, in the correction of frequency change of sound signal reproduced at a speed different from the recording speed, by converting the time axis of the reproduced sound signal based on the fundamental basic period unit using the zero cross point of the reproduced signal as the starting point. CONSTITUTION:The sound signal inputted to the sound signal input terminal 1 is digitized by an A-D converter 2 and written in the memory 4 at a predetermined frequency using a time axis conversion means to convert the time axis of the sound signal corresponding to the ratio of writing frequency to the reading frequency. The data are outputted from the memory 4 at a reading frequency different from the writing frequency. The inputted sound signals are successively and continuously inputted to the memory 4, and outputted selectively from the memory 4 based on the fundamental period unit taking the zero cross point corresponding to the peak of the zero cross characteristics of the inputted sound signal in each fundamental period as a starting point. The signals are outputted selectively using a fundamental period unit taking the zero cross point as a starting point so as to prevent the formation of blank time, discontinuous point, and the duplicate read out of the inputted signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time axis conversion device for audio signals, and more particularly, to a time base conversion device for audio signals, and particularly for converting signals reproduced at a speed different from that at the time of recording by a speed variable audio signal recording and reproducing device (hereinafter abbreviated as a tape recorder). When correcting and restoring frequency changes, the reproduced audio signal is subjected to time axis conversion processing on its own fundamental period starting from its zero cross point, thereby achieving good sound quality without discontinuities and pitch changes. Output audio signal? The purpose of the present invention is to provide a time axis converting device that can perform 44 times.

Generally, when playing back and listening to signals recorded on magnetic tape using a tape recorder, if necessary, the signal may be played back for a shorter time than the recording time (or conversely, at a slower rate).
You may want to play it. In this case, simply changing the tape speed simultaneously changes the pitch of the original audio signal, making it impossible to understand the content at all. For this reason, so-called time-base conversion is required to convert the frequency components of the reproduced signal so that they approximate the frequency components of normal audio when recorded.

As such a time axis conversion device, two analog shift registers connected in parallel are used to sample and store an input audio signal into one analog shift register, and read it out from the other shift register at a clock frequency different from that used at the time of storage. When the reading is completed, the device repeats the operation of reading data from one of the shift registers and inputting data into the other shift register, and converts the time axis based on the ratio of the clock frequency at the time of storage and the time of output, for example. JP-A No. 48-90608, JP-A No. 49-Sho.
It is publicly known from, for example, Japanese Patent No.-17705.

1. A device that uses a random access memory to sequentially sample and store an audio signal, reads it out using a readout clock different from that used during storage, and converts the time axis based on the ratio of the clock frequencies during storage and readout is disclosed in, for example, Japanese Patent Publication No. Showa 4
This method is known from, for example, Japanese Patent No. 8-80018.

However, in such conventional time axis conversion devices, the sampling processing interval is fixed at regular intervals regardless of the signal waveform, and noise may occur due to signal phase disturbance (pitch fluctuation) or discontinuity in the connection part. This has the disadvantage that the sound quality of the audio signal after time axis conversion is poor because of this.

In time-base compression in which a part of the input audio signal is removed and the remaining retained part is waveform-expanded, intelligibility largely depends on the duration of the removed part. As the duration of the removed portion increases, intelligibility deteriorates due to information loss and discontinuity of the retained portion.

The present invention eliminates the above-mentioned drawbacks, and includes sampling an input audio signal → which has not been reproduced at a desired reproduction speed at a predetermined clock frequency, writing it into a storage device, and reading it out using a read clock slower than the writing speed. This method obtains an audio signal that has been time-axis converted. The removed portion and the retained portion necessary for time axis compression are configured in basic period units starting from the zero-crossing point corresponding to the maximum value of zero-crossing characteristics within each basic period of the input audio signal. As a result, it is possible to obtain a speech output with good intelligibility and no noise and little pitch change.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the operating principle of the audio signal time axis conversion device according to the present invention. In Figure 1, 4 is a high-speed reproduction signal that is reproduced at approximately twice the recording speed, and 2) is a high-speed reproduction signal that is retained and removed every basic period starting from the zero cross of the high-speed reproduction signal (5). This is an expanded signal waveform obtained by expanding and connecting the retained portion.

In this way, since the time axis conversion process is performed in basic cycle units starting from the zero cross, the converted audio signal has good sound quality because there is no disturbance in the fundamental cycle and no discontinuity occurs at the connection part. . Furthermore, since the duration of the removed portion during time axis compression is short, deterioration in intelligibility is significantly reduced, and deterioration in sound quality is reduced, especially in female voices.

FIG. 2 is a block diagram showing an embodiment of an audio signal time base conversion device according to the present invention.

This embodiment is used for so-called time axis compression, which expands the waveform of an audio signal.The audio signal is sampled and written to a storage device at a predetermined speed, and then read out and written at a reading speed that is slower than the writing speed. This is to obtain an audio signal with a time axis conversion ratio corresponding to the ratio of speed and reading speed. In the above storage device, writing and reading are performed cyclically, and the writing speed is higher than the reading speed, so the writing position □ catches up with and overtakes successive positions, but in this embodiment, writing is performed continuously. When the writing position precedes the reading position by 1 or more F for one basic period of the audio signal, and the reading position reaches the starting point of the basic period, the reading position is changed to the writing position 71 of the starting point of the latest basic period. The writing position and the reading position are configured so that they do not overtake each other or cross over each other.

In FIG. 2, 1 is an audio signal input terminal, and analog-to-digital conversion means (hereinafter abbreviated as A-D converter) 2
and connected to the fundamental period extraction means 3. The output signal of the A-D converter 2 is stored in a storage device (hereinafter abbreviated as RAM).
4 is supplied.

For example, a random access memory with a storage capacity of 512 words can be used as the RAM 4, and in the following description, the storage capacity is assumed to be 612 words.

The output terminal of RAM 4 is connected to the output control means 5,
The output terminal of the control means 6 is connected to the digital-to-analog conversion means (
The output terminal of the DA converter 6 (hereinafter abbreviated as a DA converter) 6 is connected to an audio signal output terminal 7.

The output control means 6 is composed of launch circuits 8 and 9. 1cn-J: Zero/zero detection means, flip-flop circuit (hereinafter abbreviated as FF circuit) 11. It is composed of an inverter 12 and an AND gate 13. FF1! The sign bit output of the AD converter 2 is connected to the D input of the +1 path 11. 14 is a write address counter, and 15 is a read address counter, each of which is configured so that the next count value after 611 is φ, corresponding to the storage capacity of the RAM 4.

16 is a data selector, and write address counter 1
4 and the output terminal of the read address counter 16 are connected to the input, and the output terminal is connected to the address input terminal of the RAM 4.

17 and 18 are FF circuits, and 19 is an AND gate. These, the fundamental period extraction means 3, and the zero cross detection means 1o constitute the starting point detection means 2o. 21 is a first address register, which is a write address counter 1;
4 is supplied, and the address data is temporarily stored by the start point detection signal STP of the start point detection means 20. 22 is a 17th address register, to which the output of the first address register 21 is supplied! +, the above output is temporarily stored at the falling edge of the comparison output WA2<RA of the comparison means 23. The second address register 22 uses a transparent latch that generates the input signal as it is at the output terminal when the comparison output WA2<RA is "H". 23 is the output RA of the read address counter 15
is a comparison means, in which the output (WA2) of the second address register is supplied to the B input, and these are compared.

The A)B output, that is, the (RA)WA2) output of the comparison means 23 is supplied to the load terminal of the second address register 22, and the address data WA1 of the first address register 21 is temporarily stored at -2. Further, the A=B output, that is, the (WA2=RA) output of the comparison means 23 is supplied to the CK large input of the FF circuit 24. 26 is an AND gate, the output of which is supplied to the load terminal of the successive address counter 16 and the address data WA1 of the first address register 21.
is loaded into the read address counter 16. 26 is a clock generation circuit. 29 to 36 each receive a predetermined clock signal CL2°CL2. from the clock generation circuit 26.
CLa, CL4. RDCLKl, RDCLKl.

RDCLK2 and RDCLK3 are supplied.

The zero cross detection means 10 outputs a zero cross detection signal S when a zero cross in a predetermined direction exists in the input audio signal.
Generate Z. This zero cross detection signal SZ is sent to the FF circuit 1.
7 CLR input. The °°H'' signal is supplied to the D input of the FF circuit 17, and the output SF of the fundamental period extraction means 3 is supplied to the CK large input.FF circuit 18
The Q output of the FF circuit 17 is supplied to the D input, and the clock signal CL2 is supplied to the CK large input. The two inputs of the AND gate 19 are connected to the ◇ of the FF circuit 17, respectively.
The output and the Q output of the FF circuit 18 are supplied.

The FF circuit 17 is set by the fundamental period signal from the fundamental period extracting means 3, and the Q output becomes "HI+". It is sent at the rising edge and its Q output becomes "H". Further, after the FF circuit 17 is set, it is reset by another zero cross detection signal from the first zero cross detection means 1o, and its Q output becomes °゛L.
The FF circuit 18 latches °'L" at the first rising edge of the clock CL2 after the D input becomes °L", and its Q output becomes L". The Q output of the FF circuits 17 and 18 and the AND output of the Q output serve as the output of the starting point detection means 2o. As a result, starting point detection means 2
0 means that after the basic period extraction signal SF of the audio signal arrives,
At the time of generation of the first arriving zero cross detection signal SZ, a single cross STP having a width of 1 to 1 and a half period of the clock CL2 is generated with the start point detection signal.

27, 28 are Nantes gates, and the two gates of Nantes gate 27 are supplied with clock signals CL3 and CL4, respectively. The output of the Nant gate 27 is supplied to one input of the Nant gate 28, and the clock signal CL2 is supplied to the other input.

In addition, as the fundamental period extraction means 3, for example, 9,'I
- The "fundamental period extraction device for audio signals" disclosed in Japanese Patent Application No. 56-89076 can be used.

FIG. 3 is a block diagram of one embodiment of the clock generation circuit 26 of FIG. 2.

In FIG. 3, 100 is a clock oscillation circuit whose oscillation frequency is 8.4 MHz. 101 to 106 are frequency dividers each having a predetermined frequency division ratio, and the output signal of the clock oscillation circuit 100 is commonly supplied to each input. 110 is a changeover switch having a switching contact (A) to) and a common contact (one sword).Switching contact (A)
The output terminals of the frequency dividers 101 to 104 are connected to the output terminals of the frequency dividers 101 to 104, respectively. 111 to 114 are each a 1/2 frequency divider, and the input of the 1/2 frequency divider 111 is a changeover switch 1.
The common contact of the changeover switch 110 is connected to the clock output terminal 116, and its Q output is supplied to the input of the frequency divider 112. Connected to clock output terminal 117 via inverter 116. 1/2 frequency divider 111
The Q output and Q output of are respectively clock output terminal 11.
The Q output and the Q output of the frequency divider 112 are connected to the clock output terminal 1 and 119, respectively.
20 and 121 are connected to tl. 1/2 frequency divider 1
13 is supplied with the output of the 1/210 frequency divider 105, and its Q output is supplied with the 1/2 frequency divider 114. 17
The output of the 210 frequency divider 105 is also provided to the clock output terminal 122. The Q output of the 1/2 frequency divider 113 is connected to the clock output terminal 123. 1/2 frequency divider 114
The Q and Q outputs of are connected to clock output terminals 124 and 126.

Clock output terminal 116, 117, 118, 119°1
20.121.122, 123, 124 and 126, respectively, and clock signals CL4. CL4. CLa,C
La.

and RDCLKl are sent.

With the above configuration, the output terminal 124 always outputs 10KHz.
A clock signal RDCLK1 is sent out.

In addition, from the clock output terminal 120, the changeover switch 1
20KHz corresponding to the switching position (A) to (A) to (A) to (A) to (A) to (A) to (A) to (B) of 1o.

17.5KHz, 15KHz and 12,5KHz
A clock signal CL2 is sent out.

Note that by resetting the frequency dividers 101 to 105 and 111 to 114 to their initial states when the power is turned on and when switching the contacts of the changeover switch 110, the clock signal CL2 and the read clock signal RDCLK1 can always be synchronized.

The clock generation circuit 26 supplies the clock signal to predetermined clock supply terminals 29 to 36 in FIG. .0,1.
75, 1.5. and a time-base conversion signal of an audio signal having a time-base conversion ratio of 1.26.

Next, the operation of the audio signal time axis converting device having the above configuration is explained in the fourth section.
This will be explained with reference to the timing diagram shown in the figure.

The audio signal supplied to the audio signal input terminal 1 is A-to-D converted by an A-to-digital converter 2, and then supplied to the RAM 4. Since the write address counter 14 is supplied with the clock signal CL2, the write address WA increases sequentially, and the AD conversion signal AS of the input audio signal is continuously written to the corresponding address (WA) of the RAM 4. .

On the other hand, as shown in FIG. 4(b), the start point detection means 20 detects the start point corresponding to the fundamental period and zero cross point of the input audio signal, and the address data of the RAM 4 in which the latest start point is written is written. from the included address counter 14 to the first address register 21. The audio data written in the RAM 4 is sequentially read out according to the address designation of the read address counter 16. The comparison means 23 compares the address data (RA2) of the second address register 22 and the address data (RA) of the read address counter 16,
When RA2<RA, the output is set to "'H". In response to this "H" signal, the second address register 22 outputs the input data WA1 as is, and supplies it to the comparison means 23. Then, when RA2<RAAm force L''',
That is, when WAl becomes larger than RA, the second address register 22 temporarily stores the data 'WA1. Therefore, the second address register 22 stores the address of the storage device where the latest start point of the audio signal or an earlier start point has been written.

At time t1, the write address WA is as shown in FIG. 4(a).
The first address register 21 and the second address register 22 are the addresses A2 and A where the starting point ■ and the zero point are written, respectively.
1, and the read address RA is the written address Ab of 0 point. After time has elapsed, at time t2, the write address WA is the address A where the 0 point of the audio signal is written. , and the read address RA is the second
When the storage data A1 of the address register 22 is reached, the RA = WA 2 output of the comparison means 23 gives
The first address register 21 is added to the successive address counter 16.
The stored data WA1 is set. In other words, the read address RA will jump from A1 to A2, and R
Among the audio signals written to AM4, from time t to t0'
The data of one fundamental period up to this point will not be read out.

At the moment the read address RA is replaced by A2, the output WA2 of the second address register 22, that is, A1 becomes smaller than RA, and WA2 (RAm force becomes II HII
Therefore, the output of the second address register 22 is the same as the output A2 of the first address register 21. A with
2 is also not larger than RA, so RA2<RAAm force”
The state of “H” continues.

Further time passes and at time t3, the start point detection signal 5TP3
occurs, and the address A3 where the starting point ■ is written is stored in the first address register 21. At this time, since the read address RA is smaller than A3, RA2<RAAm force °゛L
'', and the address A3 where the starting point ■ is written is stored in the second address register 22.

Further, as time passes, the read address RA and write address WA also increase, reading and writing continue sequentially, and at time t4, the start point detection signal 5TP4 is generated, and the start point
Address A4 corresponding to is stored in the first address register 21 from the write address counter 14. At this time, it is assumed that the read address RA has not reached the address A3 corresponding to the starting point (2).

Then, when the successive address RA reaches A3, the RA, WA2 output of the comparing means 83 becomes "H#" again, and the address RA of the successive address counter 15 is replaced by the stored data A4 of the first address register 21.

That is, the read address RA will jump from A to A4.

In this way, when the write address WA precedes the read address RA by one basic cycle or more, the read address RA
When reaching the address corresponding to the starting point, the reading address is configured to jump to the address corresponding to the latest starting point, so that selective reading can be performed in basic cycle units.

The timing diagram in FIG. 4 is for the case where the time axis conversion ratio is 2, and skipping and reading are performed alternately every basic cycle. Table 1 shows the relationship between the time axis conversion ratio and the write frequency, and the relationship between the read frequency and the number of skip cycles.

For example, if the time axis conversion ratio is 1.76, two fundamental periods are read out consecutively once every four times, and the others are read every one basic period, skipping is performed, and the time axis conversion ratio is 1.76. is 1.6
In this case, 2 basic period reading and 1 basic period skipping are repeated.

As shown in Table 1, according to the present invention, the input audio signal is sequentially and continuously written, and is selectively read out from the storage device in basic cycle units starting from the zero cross point, corresponding to the writing speed and the reading speed. It is possible to perform time axis conversion of the audio signal.

Furthermore, regarding the above reading, if the write address precedes the read address by one basic cycle or more and the read address reaches the address corresponding to the start point of the basic cycle, the read address is changed to the address corresponding to the latest start point of the basic cycle. Since it is configured to jump, it operates automatically without setting the number of readout cycles and the number of jump cycles according to the time axis conversion ratio, and also automatically responds to fluctuations in the basic cycle. It is.

Furthermore, although Table 1 shows four stages of time axis conversion ratios,
By adding a frequency divider to the clock generation circuit 26, various conversion ratios can be obtained.

FIG. 6 is a timing diagram showing an example of the operation of the starting point detection means 20.

In FIG. 6, clocks (CL4) and (CLa) are supplied to the clock supply terminals 32 and 31. (C) is a clock (CL2) supplied to the clock supply terminal 29. Clock 0CL3
) and the clock (CL2) are frequency-divided outputs of the clock (CL4) and are synchronized. The A-D converter 2 receives a clock (C
L2), and the AD conversion output As of the audio signal is generated at the timing shown in FIG. As shown in the figure (e), when the sign bit of the A-D conversion output As changes from "H" to "L", that is, when the audio signal changes from negative to positive, the FF circuit 11 changes to the figure (f). As shown in the figure, the output of the AND gate 13 changes in synchronization with the rising edge of clock (CL2).The output of the AND gate 13 becomes a single pulse almost synchronized with the falling edge of clock (CL2), as shown in (q) in the figure, and this is the zero cross detection. The zero cross detection means 10 is configured to generate the detection signal SZ at the zero cross point when the audio signal' changes from negative to positive, that is, at the zero cross where the differential coefficient has positive polarity. It may also be configured to detect a zero-crossing point that goes negative from , that is, a zero-crossing point that has a negative differential coefficient.

In this way, the zero cross detection means 1o detects only zero cross points having differential coefficients of the same polarity. The audio signal subjected to time axis conversion processing in basic period units with the zero crossing point as the starting point or end point has a continuous differential coefficient at the connection point, and generates extremely little noise.

FIG. 6 (false) shows the Q output of the FF circuit 17.

The FF circuit 17 has already been set by the basic periodic signal SF, and is reset in synchronization with the rise of the zero cross detection signal Sz, and its Q output becomes "L It". This "'L" output is the clock signal. The rising edge of the signal CL2 is latched by the FF circuit 18, and the Q output of the FF circuit 18 becomes as shown in FIG. It I of the clock signal CL2 generated by SZ, only for a period of 11 °
'H' signal is generated. This signal, that is, the start point detection signal STP is generated at the zero cross point where the audio signal shifts from negative to positive, and is supplied to the first address register 21. As a result, the first address register 21 is the RA in which the data on the positive side of the zero cross point where the audio signal transitions from negative to positive is written.
The address (WA) of M4 is temporarily stored as the starting point of the basic cycle.

FIG. 6 is a timing diagram showing the timing at which the address data WA1 of the first address register 21 is loaded into the read address register 16.

In FIG. 6, (a), Φ) and (0) indicate clock signals RDCLKa, RDCLK2 and RDCLKl supplied to clock supply terminals 36, 35 and 33. (d) shows the address data (RA) of the successive address counter 16 before the address data WA1 of the first address register 21 is loaded.

(e) shows the address data RA/ of the read address counter 16 after the address data WA1 has been loaded. (f) shows the Q output of the FF circuit 24, and (q) shows the output waveform of the AND gate 26.

In FIG. 6, the read address counter 16 is supplied with the clock signal RDCLK1 shown in (C), and its address data RA increases sequentially as shown in (d). Assume that the address RA becomes equal to the address data WA2 stored in the second address register 22 at time t1. Then, the A=B output of the comparing means 23 becomes °'H'' and the FF circuit 24 as shown in FIG.
The Q output of becomes "H". A clock signal RDCLK1 is supplied to the CLR input of the FF circuit 24, and the RDCL
°'L''' from time t2 in synchronization with the falling edge of Kl.
becomes. The output of the AND gate 26 generates a single pulse PL at the timing shown in FIG. 2(q). This signal PLC1 is supplied to the successive address counter 16, and the address data WA1 stored in the first address register 21 is loaded into the read address counter 16. As a result, the addresses increase sequentially starting from WAl, as shown in FIG. 4(e).

That is, the read address RA increases sequentially and when it reaches the address WA2 of the RAM 4 where the starting point of the basic cycle has been written, it jumps to the written address WA1 which is the new starting point. As a result, the read address RA is...RA
-2, RA, , WA1, WA1+1... and so on. The read address RA is an address corresponding to data on the negative side of the zero cross point that transitions from negative to positive, and WAl
is the natress corresponding to the data on the positive side, so the RAM
The output of 4 is smooth and there is no unnatural noise.

FIG. 7 is a timing diagram showing an example of the operation of the RAM 4 and the output control means 6. RAM 4 writes and reads data using clock signals of different frequencies, and write data and read data of various durations are generated at the output end of RAMa. We have obtained read data with a duration of .

In FIG. 7, reference numeral ``body'' is the read clock signal RDCLK1 supplied to the clock supply terminal 33. In FIG.

2) is the clock signal CL2 supplied to the clock supply terminal 29. In FIG. 4, the frequencies of clock signals RDCLK1 and Cu2 are shown as 10 KHz and 15 KHz.

The clock signals CL4 and Cu3 shown in FIG. 6 are supplied to the two input terminals of the Nante gate 27, and the clock signals CL4 and Cu3 shown in FIG.
Since the output of the Nant gate 28 and the clock (Cu2) are supplied, the rising edge is synchronized with the falling edge of the clock (Cu2) and the H
A clock signal whose "period is longer than the "L" period is generated.

This clock signal is supplied to the RAM 40R/W terminal and the select terminal S of the data selector 16. The data selector 16 selects a read address (RA) when the select terminal S is "H", and a write address (WA) when the select terminal S is "L".
) is supplied to RAM4.

RAM4 is read when the clock signal is H71.
Write operation is performed when RA is “L”.
This is the A-D conversion output As of the A-D converter 2 supplied to the M40 input terminal, and data (Wl, W2 . . . ) are set up in synchronization with the clock (CL2).

(e) is the write address (WA), and the address (WAl, WA2) is also synchronized with the clock (CL2).
...) is set up. (f) is a read address (RA), and the address (RA1, RA2, . . . ) is set up in synchronization with the clock (RDCLK1). (q) is the data appearing at the output terminal of RAM4, and when the clock signal supplied to the R/W terminal is H, the above read address (RA, RA2.
...) corresponding data (R4, R2...)
) is occurring and the clock signal is L11,
The above A-D conversion output data (Wl, W2...)
is occurring. As shown in (9), since a mixture of write data and read data is generated at the output terminal of the RAM 4, the output control means 6 is configured to extract only the necessary data.

First, the data at the output end of the RAM 4 is supplied to the latch circuit 8 which latches it at the rising edge of the clock (CL2) to obtain the differential shown in FIG. Although unnecessary write data has now been removed, the duration of read data is not constant.

This data is supplied to a latch circuit 9 that latches it at the rising edge of the read clock (RDCLKl) to obtain the data shown in FIG. 2(i). This data having a constant duration is supplied to the DA converter 6 to obtain a time-base converted audio signal.

Although FIG. 7 shows an example of the operation in the case where the read clock frequency is 10 KHz and the write clock frequency is 16 KHz, it goes without saying that the same operation can be performed with the other write clock frequencies mentioned above.

In this way, the RAM 4 has the write address counter 14
The AD conversion output is written to the write address corresponding to the contents of the read address counter 16, and data at the read address corresponding to the contents of the read address counter 16 is read out, and writing and reading are executed at different speeds.

As described above, the audio signal time axis conversion device according to the present invention writes an input audio signal to a storage device at a predetermined writing speed, reads it at a reading speed different from the writing speed, and corresponds to the ratio of writing speed to reading speed. When converting the time axis of an audio signal using a conversion ratio, the input audio signal is written sequentially and continuously, and is selectively read out from the storage device in units of basic cycles starting from the zero cross point, and is adjusted according to the writing speed and reading speed. It is possible to perform time axis conversion of audio signals.

Furthermore, regarding the above reading, if the write address precedes the read address by one basic cycle or more and the read address reaches the address corresponding to the start point of the basic cycle, the read address is changed to the address corresponding to the latest start point of the basic cycle. Since it is configured to jump, it operates automatically without setting the number of readout cycles and the number of jump cycles according to the time axis conversion ratio, and also automatically responds to fluctuations in the basic cycle. It is.

In the audio signal shown in Figure 4), there are one positive or negative zero-crossing point of the differential coefficient in one fundamental period.
It is not uncommon for an audio signal to have a plurality of such zero-crossing points in one basic period. The audio signal shown in Figure 8(a) has zero crossing points with positive and negative differential coefficients, each with two zero crossing points in the first half.
There are one each in the second half. Assume that the fundamental period extraction means 3 generates the fundamental period signal SF shown in (b) in response to the audio signal (-). In such a case, if the zero cross point that arrives following the generation of the fundamental periodic signal SF is taken as the starting point, for example, in the interval from period T1 to T2, one fundamental period is from the zero cross point ■ to θ, and this - wave and , period T
If one fundamental period in the section from 6 to T6, that is, one wave from the zero cross point ① to O, is selectively read out, the pitch of the fundamental period will be disturbed and it will be difficult to hear.

The start point detecting means of the present invention can set @ as the starting point in the period T, and G as the starting point in the period T2 for the audio signal shown in FIG.

That is, a starting point detection means is used that takes as a starting point a zero crossing point having the characteristic maximum value of the zero crossing points in each fundamental cycle. The configuration will be explained below.

FIG. 9 is a block diagram showing another embodiment of the starting point detection means 2o shown in FIG. 2.

The starting point detection means of this embodiment determines the slope of the zero-crossing point of the input audio signal, and generates a detection signal PLB every time a zero-crossing point with a larger slope occurs within each basic period. It is.

In FIG. 9, 63 and 64 are delay circuits I and 2, each of which is constructed of, for example, an N-stage shift register. These delay the outputs of the A-D converter 2 and the delay circuit 1 by a time corresponding to N clock signals CL2, respectively. The output DAS of the delay circuit 153 is also supplied to the zero cross detection means 1° and the RAM 4, and the delay circuits I63 and 1154 are provided to measure the audio level before and after the zero cross point. For example, if the above N is 4, the frequency of the clock signal CL2 is 20
KHz, 17.6KHz, 16 KHz and 12.5KHz respectively! ■, Spill 07. Point 0.2m5ec, 0, 229m5ec, 0
, 267m5ec and 0.32m B+il C The sound level before and after can be measured. 68 is an FFM path, the S input is supplied with the '°H°'' signal (+V), and the CK large input is the output SZ of the zero cross detection means 10.
is supplied, and a clock signal CL2 is supplied to the CLR input. 61 and 62 are each three-person AND gates, one input of which is commonly connected i.
, the Q output of the FF circuit 68 is supplied. and gate 6
1, the other two clock signals CL3 and CL4
The other two inputs of AND gate 62 are supplied with clock signals CL3 and CL4.

66 is a comparison circuit, the output of the delay circuit 54 is supplied to the 6 input, and the output of the delay circuit 63 is supplied to the S input, and when the S input>6 input, the output becomes "H". 67 is a data selector, and the delay 1 [J1 path 64 and the output of the A-D converter 2 are supplied to the A and S inputs, and when the S input is II L II, the S input is °′H″
When , the signal supplied to the S input is output. A latch circuit 68 latches the output of the data selector 67 with the output of the AND gate 62. A latch circuit 69 latches the output of the latch circuit 68 with the output of the AND gate 7o. A basic cycle signal SF is supplied to the clear terminal of the latch circuit 69. Reference numeral 71 denotes a comparator circuit, and the outputs of latch circuits 69 and 68 are supplied to six inputs and S input, respectively, and when S input>A input, its output becomes "H". The output of the comparison circuit 1 is supplied to one input of the AND gate 7o. and gate 61
The output of is fed to the other input of AND gate '70.

72 is an address register, and the output W of the write address counter 14 is controlled by the output signal PLB of the AND gate 7°.
Latch A. The output of the address register 72 is supplied to the first address register 21, and latched therein by the basic period signal SF.

Next, the operation of the starting point detection means 62 having the above configuration will be explained with reference to FIGS. 10 and 11.

For the input audio signal shown in Figure 10), the fundamental period signal SF and zero cross detection signal SZ are generated at the timings shown in Figures (b) and (C). This signal SZ (FIG. 11t) causes the Q output of the FF circuit 68 to change to FIG.
) becomes "H" as shown in 1. Immediately after that, CL2 is I
IH#l, FF5s is cleared and a single pulse is generated. Single pulses having the width of the clock signal CL4 are generated at the outputs of the AND gates 62 and 61 at the timings shown in FIGS. 11(q) and 11(h), respectively.

Since the zero cross detection signal Sz is detected by the zero cross detection means 10 based on the output signal of the delay circuit (53), when the zero cross detection signal SZ shown in FIG. 11(e) is generated, the comparison circuit 66 and the six inputs of the data sector 67 are A- as shown in FIG. 11(d).
The D-converted output is W-4, and the signal supplied to the S input is W4.

In other words, audio data at locations a predetermined time away before and after the zero cross point are supplied to the comparison circuit 66. Since the measured bit is not input to the comparator circuit 66, its level, that is, its absolute value, is compared by the comparator circuit 66, and the larger one appears at the output of the data selector 67. The data is latched in the latch circuit 68 at the timing shown in FIG. 11(q), that is, every time the zero cross detection signal SZ is generated.

The audio level data latched in the launch circuit 68 is level-compared with the audio level data latched in the latch circuit 69 by a comparison circuit 71.

Then, the comparison is made only when the audio level corresponding to the newly arrived zero-crossing point is higher than the audio level corresponding to the zero-crossing point before the previous zero-crossing that is latched in the latch circuit 69. The output becomes H”,
The AND gate 70
The output PLB of is set to "H", and the audio level data of the latch circuit 68 is latched into the latch circuit 69. Note that since the latch circuit 69 is configured to be cleared by the basic periodic signal SF, the audio level data corresponding to zI that first arrives following the generation of the basic periodic signal SF is always latched. It is latched into circuit 69. This latch signal PLB is also supplied to the address register 72, and the address data WA of the write address counter 14 at that time is stored in the address register 7211C-.

The first address register 21 is configured to latch the output data of the address register 72 using the basic periodic signal SF.

That is, with the above configuration, when a zero cross point occurs, the start point detection means 62 compares the levels before and after the predetermined time, and selects the larger one to correspond to the zero cross point that occurred earlier within the same period. When the above level corresponding to the new zero-crossing point is larger than the above level, the output signal P
Generates LB and stores the above level. This signal PLB is the output data R of the write address counter 14.
A.

That is, the address register 72 in which the zero cross point is written is temporarily stored. Therefore, immediately before the basic period signal SF arrives, the zero cross point having the maximum value of the audio level before and after the zero cross point among the zero cross points that existed during the basic period is written in the address register 72. This means that 6 addresses of RAM4 have been memorized.

The operation of the configuration shown in FIG. 9 will be explained again with reference to the timing diagram shown in FIG. 10.

Time t. The fundamental periodic signal SF1 is generated at , and the first zero cross signal SZ1 arrives at time t1. At this time, the latch 69 is cleared and 0 data is stored. The starting point detection means 52 latches the larger audio level data before and after S21, that is, the slope data in S21, in the latch circuit 69, and stores the output data RA of the write address counter 14 in the address register 72. Next, at time t2, a zero cross signal Sz2 is generated, and since the slope data corresponding to this is larger than that corresponding to Szl, the slope data in this zero cross signal Sz2 is latched in the latch circuit 69, and the slope data is stored in the write address counter. Fourteen output data RA are stored in address register 72. Furthermore, a zero cross signal SZ3 is generated at time t3. is smaller than the slope corresponding to the corresponding slope data S22, so the latch signal PLB is not generated. Then, at time 14 when the basic periodic signal SF2 is generated, the address register 72 registers the zero point SZ2 corresponding to the maximum slope data among the zero crosses SZ1 to SZ3 during one period from times t1 to t4. RA at the time of occurrence
This means that the address WA of M4 is stored. This address data WA1 is temporarily stored in the first address register 21 as the starting point of the basic cycle of the input audio signal.

This address data WA1 is supplied to the second address register 22 and the coincidence detection means 23, as shown in FIG.

In this way, the zero crossing point with the maximum slope within each fundamental period is detected as the starting point of the fundamental period. In FIG. 10, zero cross detection signals szt Sz6. Zero cross points corresponding to Sz8 and 5z11 are detected as the starting point of each fundamental period.

In the embodiment shown in FIG. 9, the start point detection means 62 retains the larger level of the predetermined time period before and after the zero-crossing point as the slope data of that zero-crossing point, and compares it with the slope data of other zero-crossing points. Although the detection signal PLB is generated each time a zero cross point having larger slope data is generated by comparison, it is also possible to use the sum of the above levels or either one as the characteristic value of the zero cross point. Furthermore, a differential value at a zero-crossing point or an integral value near a zero-loss point can also be used.

As described in detail above, according to the present invention, an input audio signal is written to a storage device at a predetermined writing frequency, data is read from the storage device at a reading frequency different from the writing frequency, and data is read from the storage device at a reading frequency different from the writing frequency. It is equipped with a means for converting the time axis of the audio signal in accordance with the ratio, and the input audio signal is sequentially and continuously written to the storage device, and is selectively read out in basic period units starting from the zero cross point, thereby outputting the signal. It is possible to provide a time axis conversion device for an audio signal in which no blank time or discontinuity occurs in the signal.

Furthermore, regarding the above reading, when the write address reaches the address corresponding to the start point of one basic cycle, the read address is jumped to the address corresponding to the latest start point of the basic cycle, so the time axis conversion ratio is It operates automatically without setting the number of successive cycles and the number of skipped cycles in response to this, and also automatically responds to fluctuations in the fundamental cycle.

Furthermore, the time axis conversion device according to the present invention obtains the characteristics of the zero-crossing points of the audio signal, such as slope data, and calculates the zero-crossing point corresponding to the maximum value of the zero-crossing characteristics among the zero-crossing points existing in each fundamental period. Since the time axis is converted in basic period units with , which is the starting point of each basic period, there is no disturbance in the basic period of the audio signal after time axis conversion, and the sound quality is good.

Furthermore, according to the present invention, since the signals are selectively read out in basic cycle units starting from zero-crossing points having differential coefficients of the same polarity, it is possible to obtain a time-base converted signal with extremely little noise p generated at connection points. It's something.

[Brief explanation of the drawing]

Fig. 1 is a waveform diagram showing the operating principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the audio signal time axis conversion device according to the invention, and Fig. 31 is an example of a clock generation circuit used in this device. A block diagram showing an example; FIGS. 4, 6, 6 and 7 are timing diagrams showing an example of the operation of this device; FIG. 8 is an example of an audio signal waveform and a fundamental period extraction signal for it. 9 is a block diagram showing an embodiment of the start point detection means of the time axis conversion device according to the present invention,
FIGS. 10 and 11 are timing charts showing the operation. 2...A-D converter, 3...Fundamental period extraction means, 4...Storage device, 6...Output control means, 6... ...D-A converter, 10...
. . . Zero cross detection means, 14 . . . Write address counter, 16 . . . Read address counter,
16...Data selector, 20.52...
・Starting point detection means, 21° 22...First and second address registers, 23...Comparison means, 2e
・・・・・・Clock generation circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 5 - It814 (Tsuku Figure 6

Claims (1)

[Claims] (1) Writing an input audio signal to a storage device at a predetermined writing frequency, reading data from the storage device at a reading frequency different from the writing frequency, and corresponding to the ratio of the writing frequency to the reading frequency. a time axis conversion means for converting the time axis of the audio signal,
A writing means for sequentially and continuously writing the input audio signal into the storage device; and a storage device selectively storing the input audio signal in basic period units starting from a zero-crossing point corresponding to the maximum value of the zero-crossing characteristic within each basic period of the input audio signal. In order to prevent blank time, discontinuous points, and repeated reading of the write signal from occurring in the output signal, the zero cross reading means corresponds to the maximum value of the zero cross characteristic within each fundamental cycle. A time axis conversion device for an audio signal, characterized in that it selectively reads out data in basic period units starting from a point. (2) The successive output means includes a start point detection means for detecting a zero cross point corresponding to the maximum value of the zero cross characteristic within each basic cycle of the input audio signal, and an address of the storage device in which the start point of the input audio signal is written. It is equipped with at least two temporary storage devices for temporary storage, and a coincidence detection means for detecting a coincidence between the address data stored in these temporary storage devices and the subsequent address, and a write position and a readout position. When the relative position of is equal to or more than one basic period of the audio signal and the read address reaches the address corresponding to the start point of the basic period, the read position of is set to the address stored in the other temporary storage device. 2. The audio signal time axis conversion device according to claim 1, characterized in that the audio signal is configured to jump. (3) The starting point detection means includes a fundamental period extraction means for extracting the fundamental period of the input audio signal, a zero cross detection means for detecting the zero crossing of the input audio signal, and a starting point detection means for measuring the zero crossing point with respect to a predetermined characteristic, and detecting the zero crossing point of the input audio signal. A patent claim characterized in that the zero-crossing characteristic detection means is provided to compare the characteristic of the zero-crossing point with the above-mentioned characteristic, and the zero-crossing point corresponding to the maximum value of the above-mentioned predetermined characteristic within the fundamental period is set as the total points of the fundamental period. 2. The audio signal time axis conversion device according to item 2. (4) The audio signal time axis conversion device according to claim 3, wherein the zero cross detection means detects zero cross points having differential coefficients of the same polarity. (6) The zero cross characteristic detection means includes a delay circuit, a temporary memory I
The sum of the audio signal levels before and after a predetermined time of the zero crossing point, or whichever is larger,
Or one of them is held as its zero-crossing characteristic, and compared with the zero-crossing characteristic of the zero-crossing point that arrived earlier, when the zero-crossing characteristic of the later zero-crossing point is large, that characteristic value is held, 4. The audio signal time axis conversion device according to claim 3, characterized in that the device is configured to generate a detection signal.