JPS589626B2 - digital signal receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal receiver for receiving a time division multiplexed signal of a pulse code modulated multi-frequency signal and a pulse code modulated single frequency signal.

Conventionally, this type of device has separately installed a receiver for a multifrequency signal (MF signal) and a receiver for a single frequency signal.

As a digital multifrequency signal receiver, there is a so-called digital MF receiver using discrete Fourier transform as shown in the block diagram of FIG.

As shown in FIG. 1, the pulse code modulated multi-frequency signal input from the input terminal 10 is multiplied by the output of the wint function generator 13 in the multiplier 12, and the temporary storage circuit 14
is input.

This receiver uses time-division multiplexing, and the received signal is sequentially supplied from a temporary storage circuit 14 to a discrete Fourier transform circuit 15 of a selected frequency for each purpose.

The signals inputted here are multiplied by a sine wave generator 18, a cosine wave generator 19, and multipliers 16 and 17, which have the same frequency as the frequency to be detected.

The outputs of these multipliers are each integrated for a certain period of time by integrators 20 and 21, and these integrated outputs are added vectorially.

That is, the outputs of the integrators 20 and 21 are connected to the circuits 22 and 2, respectively.
3 is converted into an absolute value, and the outputs are added in an adder 24.

Alternatively, each input may be squared in the circuits 22 and 23, and a vector sum of squares may be obtained by the adder 24.

This addition output is provided by a digital comparison/judgment circuit 25 (hereinafter simply referred to as a comparison circuit).

) is compared with the threshold from the threshold generation circuit 26, and an input signal exceeding this is determined to be a signal of the target frequency,
The result is output via the storage circuit 27 to the output terminal -728.

The signal supplied from the temporary storage circuit 14 is detected by the above-described operation, and the determination result is outputted to the output terminal 28 in time series for each selected frequency.

FIG. 2 shows the time tissement of the signal of the digital MF receiver of FIG. 1.

The receiver receives pulse-encoded signals A from a plurality of lines such as the Ao line and the A1 circuit.

, A1, etc. are time-division multiplexed and input.

b is the input of the multiplier 12, C is the input of the temporary storage circuit 14,
d is the input of multipliers 16 and 11, e is the input of integrators 20 and 21, f is the absolute value or squarer circuit 22 and 2
3, g is the input of the adder 24, and h is the input signal of the comparator 25.

Furthermore, i is the output of the comparator 25, and the MF signal includes two of the six frequencies in the input signal, and as shown in the figure, it is output in a form where there is an output in two of the six bits. be done.

fi (i=1 to 6) correspond to MP signals, respectively, f1=700Hz, f2=900Hz
, f3=1 100Hz, f4=1 300Hz,
It represents f5=1500Hz and f6=1700Hz.

Sij, Oij (t=1 to 6, j=1 to 6)
ij is 1ΣAo (f i) on the side that multiplies the sine wave
l and Otj represent the side by which the cosine wave is multiplied.

On the other hand, a single frequency signal receiver is used for the multi-frequency signal (
It is provided separately from the receiver for MF signals, and therefore has the drawback of being uneconomical.

The present invention has been made in view of the above-mentioned conventional drawbacks,
A new and useful digital signal receiver capable of simultaneously receiving multi-frequency signals and single-frequency signals is provided.

FIG. 3 is a block diagram of one embodiment of the present invention, in which the first
Components with the same numbers as those in the figure are the same circuits as those described in FIG. 1.

11 is a control circuit, 14' is a temporary storage circuit with variable storage time, and 26' is a variable level threshold generation circuit.

FIG. 4 shows a time pulse for explaining the operation of this embodiment, and the input is a pulse-encoded multi-frequency signal (M
F signal) and a pulse-encoded single frequency signal are time-division multiplexed.

Below, the single frequency signal component is the common line inter-office continuity test signal (C
It is called the S signal.

) will be explained as an example. In the time chart of FIG. 4, b, c, . . . , i correspond to the same symbols as explained in FIG. 2.

However, C in FIG. 4 is a temporary storage circuit 1 with variable storage time.
4'.

As shown in FIG. 4b, the multiplier 12 in FIG.
o, A1...MF signal A from the line.

, A1... and CS signal B from Bo, Co,... lines.

, co, . . . are time-division multiplexed signals.

Note that the sum of absolute values of the Bo and Co signals is represented by xi and yi.

As shown in FIG. d, the storage time of the temporary storage circuit 14' is the single frequency CS signal B.

, Co..., is set to a value equivalent to a single slot, and multi-frequency signals (MF signals) AO,
When A I... is input, it is set to a value equivalent to 6 slots.

Such changes in the accumulation time are performed based on a control signal from the control circuit 11.

The control signal of the control circuit 11 is also applied to a sine wave generator 18 and a cosine wave generator 19.

As a result, the sine wave generator and cosine wave generator generate signals synchronized with the time slots of each signal, as shown in FIG. 4j.

The input level to the comparison circuit 25 differs for each channel due to the frequency characteristics of the multipliers 16, 17, the integrators 20, 21, the absolute value circuits 22, 23, etc.

This difference in level is particularly noticeable in the case of the MF signal and the CS signal.

Therefore, as shown in FIG. 3, the output level of the threshold generation circuit 26' is controlled by a control signal from the control circuit 11.

Such control of the output level is performed in synchronization with the control of the temporary storage circuit 14' with variable storage time, the sine wave generator 18, and the cosine wave generator 19 described above.

In the block diagram of FIG. 3, the control circuit 11 is shown as an independent block, but its hardware configuration includes a temporary storage circuit 14', a sine wave generator 18, a cosine wave generator 19, and a threshold value generator. Of course, it may be formed integrally with any one of the circuits 26', or may be formed separately in the above hardware.

As explained above, the MF receiver and the CS receiver using discrete Fourier transform were conventionally installed separately, but according to the present invention, the MP signal and the CS signal are time-division multiplexed, and the receiver By adding a control circuit that controls the storage time of the storage circuit, the generation timing of sine waves and cosine waves, and the threshold level, the receiver can be made more economical.

Furthermore, even if the MF receiver becomes unnecessary in the future due to the communication system, it can be used as a CS receiver by making some hardware changes, so it is extremely economical and flexible.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an example of a digital MF receiver using a conventional discrete Fourier transform circuit, Fig. 2 is a time chart for explaining the operation of the digital MF receiver of Fig. 1, and Fig. 3 is a block diagram of an example of a digital MF receiver using a conventional discrete Fourier transform circuit. FIG. 4, which is a block diagram of one embodiment of the present invention, is a time chart for explaining the operation of FIG. 3. 10... Input terminal, 12... Multiplier,
13... Wind function generator, 14...
・Temporary storage circuit, 15... Discrete Fourier transform circuit, 16, 17... Multiplier, 18...
・Sine wave generator, 19...Cosine wave generator, 20
, 21...Integrator, 22.23...Absolute value or square circuit, 24...Adder, 25.
...Digital comparison/determination circuit, 26...Threshold value generation circuit, 27...Storage circuit, 28...
...Output terminals 7, 14'...Temporary storage circuit with variable accumulation time, 26'...Variable level threshold generation circuit, 11...Control circuit.

Claims (1)

[Claims] 1. A temporary storage circuit with variable storage time that receives a time-division multiplexed signal of a pulse code modulated multi-frequency signal and a pulse code modulated single frequency signal, and an output of the temporary storage circuit with variable storage time. a discrete Fourier transform circuit that performs a discrete Fourier transform on the data; a digital comparison/judgment circuit that compares the output of the discrete Fourier transform circuit with the output of the variable level threshold generation circuit; and storage of the temporary storage circuit with variable storage time. A digital signal receiver comprising a control circuit that controls time, generation timing of the sine wave and cosine wave of the discrete Fourier transform circuit, and output level of the variable level threshold generation circuit.