JPS5896269A - Positron ct device - Google Patents

Abstract

PURPOSE:To enable in a short time the collection of signals corresponding to all of the combinations of detectors concerned with detection of a phenomenon of coincidence counting, by programming the sequence of the combinations of detected values to be selected in a processing device. CONSTITUTION:A group 1 of detectors is formed by grouping detectors arranged in a ring, and a plurality of detector address encoder circuits 2 have the function of taking in the outputs of a test signal generating circuit 10 selectively, while a computer 9, which is a processing device, have software for reconstituting a picture and soft ware for testing operations, both of which are incorported therein. The test signal generating circuit 10 has the function of setting the distribution of the data on the sequence of the combinations of detectors, received from the computer 9, to any of the detector address encoder circuits 2 in plural, and the function of delivering a test signal. The encoder circuits perform prescribed operations for data for test, inputting the results of the operations in the computer 9 via a coincidence counting circuit 5, a group address encoder circuit 6 and a multiplexer circuit 7. The computer 9 checks up on a channel specified by the address, based on the corresponding relation between the above input and an output address mentioned above.

Description

[Detailed description of the invention] The present invention relates to a positron CT apparatus.

Operation testing of positron CT equipment, especially coincidence counting equipment,
This has not been done properly in the past. This will be explained using the coincidence counting device shown in FIG.

In the figure, a plurality of detector groups l are detector groups formed by grouping for convenience to simplify the circuit.

The plurality of detector address encoder circuits 2 are installed corresponding to the above-mentioned detector groups, and have a function of converting the outputs of the detectors in the group into binary codes. The coincidence circuit 5 is configured as an AND circuit, and detects coincidence events between groups. A group address encoder circuit 6 encodes the group address signal of the detector into binary code. A detector address multiplexer circuit 7 sorts the detector address signals.

The processing device 9 collects the outputs 8A and 8B of the encoder circuit 6 and the multiplexer circuit 7, that is, the detector address and group address signals that are the position information of the two detectors involved in detecting the coincidence event, and generates the image g1. Reproduce.

Generally, the detectors used in positron CT devices are arranged in a ring shape, and each ring has an i5 Zo.

Since it is 1 or more, the above signal 8A is handled by the coincidence counting device.
, 8B has thousands of variations. Operation tests of coincidence counting devices are carried out to discover malfunctions in the circuit elements used, faulty connections in cables, etc., and faulty adjustments in the timing of each signal. The simplest operation test is to know the position information of the detectors collected by the processing device 9 using the positron-emitting nuclide Y, that is, all the combinations of detectors involved in the detection of the coincidence event. However, in the above method, factors such as malfunction of the detector system and variations in sensitivity are added, so it is impossible to test only the coincidence counting device.

In an improved test method for this purpose, a test signal equivalent to the output signal of the detector is sequentially inputted to the encoder circuit 2 instead of the two opposing detectors. However, as mentioned above, the number of input power combinations is 1000.
It was extremely difficult to implement this, as it would extend over the street K.

It is an object of the present invention to overcome the drawbacks of the prior art described above, and to make it possible to collect information for confirming circuit operation, that is, signals corresponding to all combinations of detectors involved in detecting a coincidence event, within a short period of time. It is an object of the present invention to provide a positron CT apparatus with a

The gist of the invention is as follows. The combination order of detected values to be selected in the processing device is programmed (2).
Furthermore, based on the combined output of this processing device, the test signal was simulated inputted into the detector address encoder circuit for the corresponding combined detector1, and the output to the processing device for this simulated test human power was calculated. The main point of the present invention is that the processing device monitors and checks the operation. Furthermore,
In the present invention, a test signal generation circuit is provided as having a function of generating a test signal based on the combined output from the processing device. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is an embodiment of the coincidence counting device of the present invention. The detector group 1 is a group of detectors arranged in a ring shape, and is the same as the conventional example shown in FIG. The multiple detector address encoder circuit 2 is basically the same as the conventional detector address encoder shown in FIG. different. Coincidence circuit 5. Group address encoder circuit6. The structure of the multiplexer circuit 7 is the same as each corresponding circuit of the conventional example shown in FIG. The features of this embodiment are that the internal functions (software) of the processing device 9 are uniquely added, and that a test signal generation circuit 10 is also provided.
be.

The processing device 9 is composed of a computer. Therefore, in the following, it will be referred to as a computer instead of a company processing device. The computer 9 includes software for image reconstruction and software for operation testing.

The operational test software is programmed with the order of combinations of detectors to be selected, so that all combinations of detectors related to the detection pressure of coincidence events can be realized for testing. This operational test software is accessed automatically or manually during operational test mode.

The test signal generation circuit 10 has a function of receiving detector combination order data from the computer 9 and setting which of the plurality of detector address encoder circuits 2 the data is to be distributed to, and a test signal sending function. The former function may be any eight-doware function that distributes, and the latter function is a logical *11 function.
, 161 is sufficient.

Explain the operation. The operation test mode, for example, is set before testing the object, and the operation test software of the computer 9 is accessed (according to instructions from an operator). This access activates the operation test software. The operation test software outputs the detector combination order one after another and inputs it to the test signal generation circuit 10. In the computer, the detector number is indicated by an address indicating the detector number, and the order of detector combinations is determined by indicating two addresses indicating the combination of detectors. Two addresses indicating this combination detector are input to the test signal generation circuit 10.

The test signal generating circuit 10 which receives the two addresses of the water quantity combination detector is similarly triggered for each pair of detector combinations outputted from a plurality of detector addresses.

The encoder circuit performs a predetermined operation on the test data that has entered the encoder circuit corresponding to each detector pair, and further includes a coincidence circuit 5, a group address encoder, a coder circuit 6,
It is input to the computer 9 via the multiplexer circuit 7. Based on the correspondence between this input and the previous output address, the computer 9 checks the yarn path specified by the address. This yarn path check is performed for every pair of detectors, and the objects to be diagnosed as a result of the yarn path check are all electronic circuits between the detector group 1 and the computer 9. In addition, the data as a diagnosis result by the computer 9 includes diagnosis of which detector is abnormal, which encoder circuit 2 series in FIG.
Two detector groups IA and IB are shown. For simplicity, the figure shows a case where the number of detectors in a group is four.

In the figure, (0) to (3) are the addresses of each detector, IA (0)
~IB(0), IA(0) ~IB(1), IA(0
) to IB(2) and IA(0) to IB(3) indicate combinations of detectors that detect coincidence events. In addition, similar combinations are established for IA address (1), address (2), and address (3). Regarding such opposing groups, the computer 9 selects opposing groups IA and IB, and then sequentially outputs specific corresponding detector combination data (address combinations) and inputs them into the operation test circuit 10. This combination data is sent by IA(0) and IB(01→IA(0) and IB(1
)-1A(0) and I B (21→I A (0) and I
This is done in the order of B(3). For each piece of data, the output via the encoder circuit 2 -> multiplexer device 7 is taken into the computer 9 and an abnormality check is performed.

Next, regarding IA(1), IB(01 to IB(
A pair with each detector in 3) is selected and data is sent out. Similar processing is then performed for all corresponding detected echo pairs.

To perform all possible combinations, another opposing group is selected one after another, and a similar procedure is repeated to form the addresses of the detector pairs. When the number of detectors in a group is four, for group A, the frequency of the clock is divided by four, and then the quadrupled frequency-divided signal is counted by a binary counter.

The output Qo=Qs of the cough binary counter indicates the detector number (address) of the A group. For group B, the clock is counted by a binary counter.

The output Qe = Qt of the binary kakunta indicates the detector number (address) of the B group. The count input for both groups A and B is a clock that forms a group selection signal. The computer 9 generates and divides the group selection signal, and further generates the Qo and Qt multiplied signals of A and B synchronized with each binary output Woog selection signal (1), and generates combinations I A (0) to I B as shown by the broken lines. (0) Corresponds to K.

Similarly, group selection signals (2), (3), (4
) are respectively IA (Ol-IB(1), IA(0)
-1B(2), 1mu(0) -1B(3)...
・Corresponds to The same applies to other combinations below.

There are various modifications to the above embodiments.

(1) Test signal generation: 8 paths 10 are used in common, but test signal generation circuits may be provided individually (same meaning as distributed) for each encoder circuit 2. In this configuration, since the encoder circuit 2 and the test signal generation circuit are directly connected, there is an advantage that the connection of the input of the test signal can be simplified.

(2) In an extreme case where the amount of processing shared between the test signal generation circuit 10 and the computer 9 is extreme, the test signal generation circuit that mainly performs various processing takes over the computer 9, and the computer 9 has a test signal generation circuit. It would be better to just have the role of triggering. This method is not very practical because the test signal generation circuit 10 has the same role as a computer. The most extreme example of the second method is a case in which the test signal generation circuit functions only as a signal transmission means, and the computer 9 performs all the main processing. This expansion naturally has the disadvantage of increasing the burden on the computer 9.

Therefore, it is necessary to allocate processing based on these points.

Next, the fifth embodiment employing the distributed configuration of (1) above will be described.
As shown in the figure. In the figure, two encoder circuits correspond to one of the encoder circuits 2 in FIG. 2. In this embodiment, a test signal generation circuit 10A is added to these two encoder circuits. The two encoder circuits are connected to the receiver circuit 11. Encoder 12. Latch circuit 14° tie generation circuit 13.
It consists of driver circuits 15A and 15B. The receiver circuit 11 has the function of receiving the detector output. The encoder 12 has a function of selectively taking in the test output of the test signal generating circuit 10m and the output of the receiver circuit 11 and encoding them into binary code. Timing generation circuit 13
has the function of determining the width of the timing signal generated from the output of the encoder 12.

The output timing circuit 14 is controlled by the output timing of the timing generation circuit 13.
, 1(: Rad, +, the driver circuit 15A is the latch circuit 14
The detector address signal latched by the multiplexer circuit 7
The driver circuit 15B has a function of sending out the output timing of the timing generation circuit 13 to the coincidence counting circuit 5.

Test signal generation circuit 10A, receiver circuit 11A1, comparison circuit 16, 16A, comparison address setting circuit 17, 1
7A, frequency divider circuit (rate down circuit) 18, OR gate 19. Binary counter addition, binary coded-decimal counter 21
Toyo υ becomes. The seeker circuit 11A is connected to the bus 9A of the computer 9.
The detector group address signal to be selected is received via the detector group address signal. The comparison address setting circuits 17 and 17A set detector group addresses determined in advance for each group. The comparator circuits 16 and 16A correspond to group A, and sometimes correspond to group n. Whether it corresponds to the A group or the n group is determined by the instructions of the computer 9 and the receiver circuit 11.
It depends on the decoding function of A. This will be explained in detail below. By arranging the test signal generation circuit 10A in a distributed configuration, each encoder circuit can accommodate two test signal generation circuits 10A.
must send an output according to A group, n group, or K to its corresponding encoder 12. This output is
When selecting the comparison circuit 16, select the A group, and select the comparison circuit 1.
When selecting 6A, it is n group. Therefore, whether each test signal generation circuit 10A is made to work in group A or group n depends on the instruction to select between comparison circuits 16 and 16A. The receiver circuit 11A makes this determination. That is, the receiver circuit 11A decodes from the signal on the bus 9A whether it is in a mode corresponding to group A or group n, and according to this result, it decodes either comparator circuit 16 or 16A. Make a selection. Here, deciphering means a case in which a decision is made based on timing, and one of the comparison circuits 16 and 16A is selected depending on whether the computer performs the A group or the N group. Since each of the two encoder circuits always exists in the A group and in the B group, the comparison circuits 16 and 16A are always selected in the test mode. When determining the A group, the comparison circuit 16 determines whether the group corresponds or not. The output of this frequency dividing circuit 18 is passed through an OR gate 19 and added to a binary counter to form an address. Next, the conversion circuit 21 performs binary code-decimal conversion.
and outputs it to the corresponding encoder circuit 21. In the corresponding encoder circuit 2A, two encoders receive the above output, and test data C%1#) is sent out via the encoder 12, latch circuit 14, and driver circuit 15A,
Moreover, the timing is determined by the timing generation circuit 13. It is sent out via the driver circuit 15B. This data and timing are transmitted to the computer 9 via circuits 5, 6, and 7Q as shown in FIG.
is entered and checked for diagnosis.

On the other hand, when it is determined that it is in the B group, the comparison circuit 16A performs a comparison, and when a match is obtained, the thread path from the OR gate 19 is followed and a similar diagnostic check is performed.

According to this embodiment, the connection of the test signal input is simplified. It goes without saying that once the number of detectors and the number of groups are determined, the number of bits of each element to be used is determined accordingly, so that it can be expanded or reduced by appropriately selecting the number of bits of each element. Therefore, by simply connecting the test signal generating circuit once, any signals corresponding to the combinations of detectors involved in detecting the coincidence event can be collected as desired, simplifying the operation test.

[Brief explanation of the drawing]

111 is a diagram of a conventional example, Figure 2 is a diagram of an embodiment of the present invention, and Figure 3 is a diagram of an embodiment of the present invention.
The figure is an explanatory diagram of the opposing group, Figure IN4 is a time chart, and Figure 5 is a diagram of another specific embodiment of the present invention. ! ...Detector group, 2A...Encoder circuit, 10
, IOA... test signal generation circuit, 9... processing device (computer). Patent applicant: Agency of Industrial Science and Technology Director Shibanz Figure 1, Ward 2, Ward 3

Claims (1)

[Claims] 1. A plurality of detector address encoder circuits provided corresponding to a plurality of groups of detectors formed by grouping; A coincidence means that detects a coincidence event and outputs the position information of the two detectors involved in the detection of the coincidence event, that is, a detector address and a group address, and a coincidence means that captures the position information that is the quantity of the image. and a test signal generating means for performing reconstruction processing and inputting the encoder circuit corresponding to the test in place of the output of the detector group, and the encoder circuit by the output of the test signal generating means. , the position information of the two pieces involved in the detection of the coincidence event in the test mode obtained through the coincidence counting means is input into the processing device, and the electrical path from the test signal generation means to the processing device is A positron CT device in which the processing device performs a diagnostic check. 2. The positron CT apparatus according to claim 1 or 2, wherein the processing device is a computer.