JPS589475A - Controller of digital key signal - Google Patents

Abstract

PURPOSE:To compress or enlarge an edge by a prescribed synchronizing period, by selecting either one of a digital key signal and the signal obtained by giving an integer-fold delay of the sampling period to the digital key signal based on the output of detection of the front and rear edges of the selected signal and an indication. CONSTITUTION:A digital key signal KEY which is produced so as to correspond to a partial region of a digital video signal is supplied to a rough control circuit 38. The circuit 38 is controlled by a control logical circuit 40 to which the data and the control signal are supplied from a microprocessor. An RAM42 within the circuit 38 gives a shift to the signal KEY by a prescribed clock synchronize period. The RAM43 and 44 prescribe the degree of the enlargement and compression by setting the degree of delay at a prescribed level. At the same time, a level comparator 54 detects the front and rear edges. Then the outputs of the RAM43 and 44 are selected based on the output of the above-mentioned detection and an indication given from the circuit 40. As a result, both edges are compressed and enlarged by an integer-fold value of the sampling period.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a key signal adjustment device that can be applied to digital video signal processing devices such as digital chromakey devices/IIIt and digital montage devices.

In these video signal processing devices, it is necessary to form a key signal corresponding to a partial area of one image.

A well-known chromakey device has a configuration as shown in FIG. In the figure, m +21 is a color television camera that photographs the foreground and background, respectively; +
31F4) is a gate circuit to which the foreground color video signal and background color video signal are supplied, (5) is a key signal generation circuit that generates a key signal for this gate circuit (31t4), and (6) is the output of the gate circuit (31+43). mix
This is a mixing circuit that leads the combined signal to the output terminal (7). Figure 2A
As illustrated in , a color TV camera (
1), the key signal generation circuit f5J calculates the three primary color components (JQ, H) in this foreground color video signal, and converts the hue difference into an amplitude difference to form a key signal. In other words, as shown in Fig. 2C, a key signal for turning on the gate only at the subject (9) is formed, and this is supplied to the gate circuit (3). A key signal to turn on the gate is formed only in the parts other than (9), and this is the gate circuit (4).
). Therefore television camera (2)
The signal of the image shown in FIG. 2E, in which the subject (9) of the back shadow (Iυ) shown in FIG. ) is mixed in the mixer (6) with the signal corresponding to object (9) from Image signals can be obtained.

In such a chromakey device, the edge portion of the generated key signal does not necessarily correspond to the boundary between the back screen (8) and the subject (9). Therefore, it is necessary to adjust the timing of the edge portion of key i.

This invention makes it possible to arbitrarily adjust the timing of the front edge and rear edge of the digital key signal when the video signal is digitized and the generated key signal is also digital. be. 1. The purpose of this invention is to realize a digital key signal adjustment device that can adjust the timing of the edge portion not only to an integral multiple of the sampling period of the digital key signal but also within a range smaller than one period of this sampling period. be. If this invention is applied to a digital chromakey device, it is possible to effectively prevent color fringing in which the back color remains on the side of the subject (9) at the boundary between the subject (9) and the back shadow αυ in the composite image. be able to.

Hereinafter, an embodiment of the present invention applied to a digital chromakey device for digital video signals of Y, U, and V signal systems will be described with reference to the drawings.

In FIG. 3 showing the overall configuration of the digital chromakey device, (one part is foreground color video data FG, ViD
and background color video data 13G, VID are supplied together with respective timing reference signals TI(,S). This color video data is a matrix of color television camera outputs (1, Q, B). Luminance signal Y1 color difference signal L formed by calculation
It is made up of components obtained by sampling l and V at a sampling frequency of, for example, a ratio of (14:7:7). The interface Q2+ looks at the timing code (horizontal synchronization signal, vertical synchronization signal, etc.) decoded from each timing reference signal TBS, and outputs two color video data F''G, VID and 13G, V.
The phase of ID is made appropriate and output to the subsequent stage.

03) is a back color data forming circuit. Back color data is formed from the foreground color video data] ("G, V I l), and this back color data is supplied to the key signal forming circuit side and the color canceller (I61).

The key signal forming circuit side performs a comparison operation for each corresponding sample of the back color data and the foreground color video data F(j, VII) to generate a key signal of a predetermined level. The key signal itself generated in this way contains many disturbances and cannot be used until the first one.
After that, as shown in FIG. is obtained.

The color canceller (16) removes the back color from the foreground color video data FG and VID based on this key signal KEY. For example, when the subject (9) is transparent, the transparent background color is removed. Specifically, the back color data is amplitude-modulated using the key signal KEY, and the modulated output is used as the foreground color video data FG, V.
It is done so that it is subtracted from ID. This back color removal is performed only on the U and ■ signals, and the luminance signal Y is simply passed through.

This color canceller (I6) includes a delay circuit (17
) are supplied with the previous color video data FG, VID. The delay circuit aη has a delay amount corresponding to the time required for the above-mentioned waveform processing in the key processor (15).

And the output CAN of the color canceller U6J,
VID and background color video data BG, VID are supplied to the mixer, and mixing of the two is performed based on the key signal KEY. In addition to simply switching and outputting two color video data CAN, vID and BG, VID, this mixing also involves gradually reducing the level of one at the boundary between the two, and
A cross-fade method can be used that gradually increases the level of the other. The output of this mixer (18) is passed through a digital filter (IJ) to an interface (
20). The digital filter output is for adjusting the waveform of the output of the mixer (18).

The interface system (to) is the composite color video data KYI) from the color canceller (CAN, VII) and the digital filter θ■, VID
, the respective timing reference signals, and the key signal KEY are output to the outside.

Furthermore, a microprocessor (21), a CRT monitor (
22I and the console (231) are used to translate the user's key human power from the console (231) and transmit it to the inside of the system, and to perform the calculation processing required in each circuit block. ing.

The digital chromakey device described above is operated by a sampling clock having a frequency corresponding to the sampling rate of color difference data.

There are several methods of processing in the key signal generation circuit (1 circuit), but for example, as shown in Figure 4, (u,
V) Specify a reference point (Uo, Vo) corresponding to the back color on the chromaticity coordinates, and create foreground color video data for new coordinates based on this reference point (Uo, ■0). A key signal is generated by calculating a linear combination (K-lxl+lyl) of projected components x, y of instantaneous values (U, V) of , V ID . Here, x = (U - Uo) cos θ ten (V - Vo
) sinθy = (V-Vo) cosθ-(T
J −Uo ) sin θ.

FIG. 5 shows the configuration of the key processor (151), in which the key signal K from the key signal generation circuit is supplied between the clip circuits and (25).The clip circuit f24)
A key signal HK E Y for hard keying is formed, and the clip circuit (25) forms a key signal 5KEY for soft keying, and one key signal HK E
Y is a non-additive mixer (2η and a selector (
C), and the other key signal 5KEY is supplied to the phase shift circuit (
Similarly, a non-additive mixer (2η
and a selector (2al).Non-additive mixer (2 power is supplied to two key signals HK, 1 and 2).

The 5KEY values are compared and the larger one is output.

The key (No. 8) output from the selector (28) is supplied to the edge timing n14 adjustment circuit (29), and the timing of the edge, that is, the part with the gradient, is set to 14M. As shown in Fig. 6A, the configuration is such that it is possible to perform adjustment in units of lock sampling period t, and adjustment within this period.The adjustment mode is as shown in Fig. 6B. As shown in FIG. 6C, there is a shift mode in which the key signal is shifted in parallel in units of a clock period t, and an edge is moved inward (compression) or expanded outward (expansion) in units of a clock period t, as shown in FIG. 6C. There is a coarse adjustment as shown in Figure 6, and a fine adjustment in which the edge is compressed within the clock cycle.This edge timing adjustment circuit G91 will be described in detail later.

The key signal output from the edge timing adjustment circuit 9) is taken out as the key signal K ID Y via the filter (3). In addition, the band of the key signal is limited so that aliasing noise does not occur when the video signal is modulated with the key signal KEY in the mixer ( ) 81.

For control and arithmetic processing in the key processor 05) as described above, data, addresses and control signals are supplied to each circuit via an I/O controller 6υ.

About hard keying and soft keying, Part 7
Explain briefly by referring to the diagram. For example, when photographing the back screen (foreground α0 where a transparent tip is placed as the subject (9) in front of 81), the back color is visible in the center of the tip, so the image shown in Figure 7A A key signal K is generated from the key signal forming circuit (14), which has a high level corresponding to the outline of the subject (9) and a slightly low level at the center thereof. In FIG. 7, signals are shown as analog waveforms for convenience of explanation, but F31
In the digital chroma key device described in J.
This is data in which samples are sequentially located at a sampling period t.

Then, in the clipping circuit (with two inputs), a clipping operation is performed using the base clipping level BL and the peak clipping level PLh as threshold levels, and a key signal HKgY for hard keying as shown in FIG. 7B is formed. Further, in the clip circuit (25), the base clip level 11 I and the peak clip level PLs
()PLh) A clipping operation is performed to set the threshold level to a soft keying key signal SKgY as shown in FIG. 7C. In this way, soft keying can form a key signal that corresponds well to the back color that can be seen through the transparent subject (9) or the reflected light of the back screen that is reflected on the subject (9).

FIG. 8 shows the basic configuration of color cancellation and mixing performed using the key signal KEY. First, when the level range from the lowest value to the highest value of the key signal KEY is 1, and the relative level of its instantaneous value is k, the key signal KEY is supplied to the arithmetic circuit (3 winters), so that (
1-k). Taking the key signal 8KEY shown in FIG. 7C as an example, the key signal 8KEY shown in the same figure
is converted to This key signal KEY is applied to the multiplier 1331
and modulates the back color signal DB from the back color data forming circuit α3). This multiplier (331
The output of is supplied to the subtractor 041 and subtracted from the foreground color video data FG, VID. Therefore, from the subtractor (341), the color video data FG, V
ID that corresponds to the subject (9) and that corresponds to the subject (9).
) video data CAN with the back color removed,
VID occurs. The above-mentioned operation is nothing but the one performed in the color canceller call in FIG.

Also, in the multiplier G51, the video data CAN, VI
D is modulated by the key signal KEY, and the background video data BG, VID are modulated by the key signal KEY in the multiplier (sub)), and both multipliers C351 (36
The outputs of 1 are added in an adder (37). In the case of a transparent subject (9) as described above, the background image can be seen through the field video data KYD and VID. Furthermore, due to the gradient of the edge of the key signal K EY, a crossfade is performed at the boundary between the subject (9) and the background fl I), in which the image is gradually switched from one side to the other, and the boundary between the images is It can be made to look natural.

The edge timing adjustment circuit C included in the key processor di will be described in detail with reference to FIG.

This edge timing adjustment circuit (2) shifts the 1-sample 8-bit digital key signal KEY supplied from the selector (to) and supplies it to a coarse adjustment circuit [K, followed by a fine adjustment circuit 0 shown surrounded by a broken line. !1, and a common control μ-chirac circuit (4
(l is provided. This control logic circuit (4(J
Data, data and control signals from the Micronorsessor are supplied via the 4-control circuit (31J), and are used to switch the shift amount, coarse adjustment on/off, fine adjustment on/off, expansion or compression. , adjustment amount, etc. are controlled.

First, to explain the shift and coarse adjustment circuit (G), it is provided with three RAMs (421 (4)). Therefore, each RAM is assumed to have a capacity for 4 samples.
M (43 is for shift mode, RAM (4
3 is for coarse adjustment of the front edge, RAM (4
4) is for rough adjustment of the trailing edge.

RAM (43 (4:31) (44) has a write operation commonly controlled by a write address WA formed by a control logic circuit.

In addition, the read address 0 formed by the control logic circuit +41 is given to the RAM (4).
Writing and reading are possible within one memory cycle, and by creating a difference between the write address WA and the read address RAo for address control of RAM (g), the input key signal KEY (1 to 4) An output shifted by a clock period can be obtained.

In addition, the read addresses RAl and RA2 formed in the control logic W form (40) are supplied to each of RAM M (43 and (44)), and the read addresses ILAt and RA2 are controlled to reduce the amount of delay occurring in the RAM. By being predetermined, the expansion defines the amount of compression.

The output of R, A M (4'2 is supplied to RAM (4) via the latch (451), and is also supplied to the latch (4G
) (47) is supplied to the RAM (44) via (48). The latches shown in FIG. 9 all cause a delay of one sampling clock. Therefore, for the output M I ]) of the latch (48), RAM
(The data written in 43K has an advanced phase. The output of this RAM (4:9) is supplied to the launch 1561 of the fine adjustment circuit 03 via the latch (4ω50). Output is fine I4 via lunch 6υ5a
It is supplied to the latch t5 (9) during the adjustment circuit. In this case, the control signal TKI generated from the control logic circuit (401)
, TK2.1-ILD latches C3Ql (52(t)
The output of either the latch 50) or the launch 6z is selected based on the trend of the waveform of the key signal, and data updating of the latch (56) is stopped.

The front and rear edges showing the trend of the waveform are the lunch (4
It is detected by comparing the output PR, E of 9) with the output PRI (which is delayed by one clock period by the latch 53) by the level comparator 541. In other words, when the levels of both are equal and in the flat region, Detection signal CT that becomes H, rising slope (PRI signal), detection signal UP that becomes H when PRI, that is, the front edge, and detection signal DW that becomes H when there is a falling slope (PRE (PRE), that is, the rear edge) is generated. and is supplied to the control logic circuit (41).When performing this level comparison, among the outputs PRE of the latch (49), the top six
By using bits, it is practical to widen the range that is determined to be a flat area. These detection signals C
T, UP, and DW are latches (4S output PRE [synchronized).

In addition, a level comparator (5) is provided, and the levels of the four outputs PRE and the output FLW of the latch 6υ are compared to form a detection signal GT. This detection signal GT is
This is frustrating because the result of enlarging or compressing the edge portion during rough adjustment does not result in an unnatural waveform. This level comparator 6 phrase includes I7. A mode switching signal is supplied via the controller (4υ), and in the expansion mode, (I” L
A detection signal GT is formed that becomes H when W≧P It E), and in the compression mode, becomes H when (1I'LW) PI also E).

In the above-mentioned shift and coarse adjustment circuit C (81), when the coarse adjustment is off, the control signals are (TKI = ], TK2 = H) according to instructions from the microprocessor.
The key signal read from RAM (44) is always supplied to latch 561 via latch 5υ52. Then write address W at RAM (43K)
By controlling the read address RAo for A, the key signal KEY can be shifted (delayed) by an integral multiple of the period of the sampling clock CK.
When the coarse adjustment is on, an instruction for expansion or compression and a lid at that time are issued from the microprocessor, and are supplied to the control logic circuit (40), and are also sent to the level comparison circuit 55.
1 operation mode is switched.

In other words, in the control logic circuit f4i), when expanded: '1
1 = 'UP threat QTTK2 = DWM - GT ) iLD = TKI -4 - TKz During compression: TKl - IJW - GT TK2 = U P M - GT HLD = TKt + 'f'Kz Control signal by the logic TKI, TK2. H.L.D.
is generated. Here, DWM and UPM are each DW
and UP are delayed by the phase difference between PRE and FLW. The control amount for expansion and compression is the read address from the control logic circuit f40, RAl,
The latch defined by RA2 (4! lI5υ output PRE, F'LW is determined by the phase difference it has with respect to the latch (4 barrel output MID). During expansion, the front edge of PREO and the rear edge of PI, W are control signals. Selected by TKt and TK2, during compression, the front edge of FLW and PR
The rear edge of E is selected by control signals TK1 and TK2. Therefore, by controlling the phase difference that PRE and F'LW have with respect to MID, it is possible to independently control the degree of expansion or compression for the front edge and the rear edge.

- As an example, for the sampling clock shown in FIG. 10A, the output P of the latch (49), the output PR of the latch r53), the output MID of the latch (48),
The enlarging operation when each of the outputs FLW of ll is as shown in FIG. 10B (the illustrated waveform represents discrete sample data in analog form) will be described. As is clear from the waveform of FIG. 10B, in the operation of FIG. 10, PRE and F
Each of the RAMs (43 and 44) is controlled so that L and W have a leading phase difference and a lagging phase difference of one clock period, respectively, and are expanded by one clock period, and P RE and FLW The phase difference between the two clocks is assumed to be two clock periods.

A level comparison circuit 541 compares the levels of P1'LE and PRE, resulting in a detection signal CT shown in FIG.

Each of UP and DW occurs. Further, during enlargement, the detection signal GT shown in FIG. 10E, which becomes H when (F LW>P RE ) is generated from the level comparison circuit 155). These detection signals are supplied to the control logic circuit (40), and the control signal TK2. TKI, 14LD is formed.

During the H period in which the control signals TK2 and TKI include the rising edge, sample data included in each waveform of FLW and PRH is selected by the latch 52 (C30), and
Sample data is pre-held in an interval I-1 where LD includes a rising edge.

Fig. 10 shows the jfftlJlfl signal TI (
2. The sample data selected and held by TKt and HL D is shown by white circles in FIGS. 10B and 10C, and as shown in FIG. 10C,
A key signal EAK is obtained in which both the leading edge and trailing edge are expanded by one clock period relative to MID.

Further, FIG. 11 is a time chart showing the operation when both the leading edge and the trailing edge form a compressed key signal EAK for one clock period. The sampling clock shown in FIG. 11A, the waveform shown in FIG. 11B, and the detection signal shown in the same figure are the same as those shown in FIG. N10 in the aforementioned enlargement operation. However, level comparison circuit I5
The operation is changed so as to generate the detection signal GT shown in FIG. Control signals TK2, TK as shown in Figure F
t.

HLD is formed. Therefore, the sample data marked with white circles in FIGS. 11B and 11C is selected and held, and as shown in FIG.
It is possible to form K.

Next, the fine adjustment circuit (39) will be explained.The key signal obtained at the output of the latch acid is
5131. RAM (59), and these outputs are taken out as outputs via latch l.Buffer memory 5
D, 几AM 15gj691 is a control logic circuit (
Control signals NC, ALE, and ATE formed by 40 are supplied as output control signals, and outputs appear from each during the period when the control signals are H. RAM 519 is a table for front edge conversion, and is loaded with conversion data from the microprocessor via the % controller (4υ). Conversion data from the processor is being loaded.

In this embodiment, compression is performed as a fine adjustment, and therefore the conversion data is a value obtained by attenuating each sample data of the key signal provided from the latch by a predetermined amount.

First, when the fine adjustment is off, an output appears from the control logic circuit (ALE=L, ATE=L, NC=H in 40, always buffer memory 57), and is taken out as an output via a latch.

Further, when the fine adjustment is on, the logic for forming the control signal differs depending on whether the coarse adjustment operation between the shift and coarse adjustment circuits in the previous stage is on or off. When coarse adjustment is off, ALE=UPD ATE=DW@CTD-1-DWD @CT When coarse adjustment is on and enlargement is performed, ALE = TKID A TE = TK2 N C = A L E + A TE coarse adjustment is off During compression operation, each control signal is formed by the logical formula: A L E = TK2 D A T E = TKt N C = A L E +A T ] (UPD in the above formula.

Each of CTD, ])WD is obtained by delaying each detection signal of UP, CT, and DW by two clock cycles, and TKID
and '1' and 2D are the control signal TK during coarse adjustment.
I and TK2 are delayed by one clock period.

The fine adjustment operation when the coarse adjustment is off will be explained with reference to the time chart in Figure 12. Figure A shows the sampling clock CK, and Figure B shows the key signal -IPRE appearing at the output of the latch (40). Detection signal C shown in Figure 12 is generated at a timing synchronized with this key signal P-E.
T, UP, and DW are generated from the level comparison circuit (54). This detection signal is delayed by two clock cycles CTD
,UPD.

The DWD is shown in Figure 12E. PRE is latched (50) in buffer memo v57) and RAM58) (59).
A key signal shown in FIG. 12C delayed at 561 is provided.

The key signals shown in FIG. 12B; FIG. 12C and FIG. 12G, respectively, are as follows:
Although each sample is continuous, it is represented as an analog signal for ease of understanding. Also, in the waveform shown by the broken line in FIG. 12C, the waveform corresponding to the previous edge is R.
The conversion data output from AM59) corresponds to the rear edge.

Then, when the coarse adjustment is off, the 12th
Each of control signals ALE and ATJNC shown in FIG. F is formed. By this control signal, the sample data indicated by white circles in FIG.
The key signal is output from either mark 5 or the RAM (59), and as shown in FIG. 12G, a key signal is formed in which the front edge and the rear edge are each compressed within one sampling period.

Note that the conversion data loaded into R, AM 51p and RAM 5'l respectively increases the original data (maximum value is 255 by 8 bits), and expands within one clock cycle. You can also do this.

FIG. 13 shows the configuration of another embodiment of the fine adjustment circuit (3(g)). In this other embodiment, a coefficient corresponding to the slope of the edge of the input key signal is generated from the ROM (67) K, This coefficient is multiplied by each sample of the key signal in a multiplier circuit (g).A key signal is supplied to this multiplier circuit via a latch R). Further, the slope of the edge of the key signal is detected by the latch and the subtraction circuit 151, and the detected signal is supplied as an address to the box 0M17) via the latch IE9. The coefficients generated in this ROM ([i7) are supplied to the multiplier circuit through the latch.

The sign of the slope is indicated by the most significant bit of the detection signal.

The example of the fine adjustment circuit having the configuration shown in FIG.
As shown in Figure A, the amount of compression τ1 where the slope is large and the amount of compression τ2 where it is small are different, (τ2>τl)
This results in variations in the amount of compression. On the other hand, the first
In the configuration shown in FIG. 3, the slope is detected and a multiplication coefficient that becomes larger as the slope becomes larger is generated by the ROM (iη). Therefore, as shown in FIG.
The amount of compression can be constant (τl−τ2).

As can be understood from the description of the embodiments described above, according to the present invention, the timing of an edge portion corresponding to the outline of a part of an image is determined by the period of a sampling clock, like a digital key signal in a chromakey device. Adjustments can be made to expand or compress by an integer multiple of . Of course,
In this invention, the amount of expansion or compression can be adjusted independently for the leading edge and trailing edge of the key signal.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing an outline of the configuration of a conventional chromakey device and a route map used to explain its operation, and FIG. 3 is an overall configuration of an embodiment of a digital chromakey device to which the present invention is applied. FIG. 4 is a route diagram used to explain key signal generation, FIG. 5 is a block diagram showing the configuration of the key processor, FIGS. 6 and 7 are waveform diagrams used to explain the key processor, and FIG. Figure 8 is a block diagram showing the general configuration of the color canceller and mixer.
FIG. 9 is a block diagram of an embodiment of an edge timing adjustment circuit to which the present invention is applied, and FIG. 11 and 12 are time charts used to explain the operation of the edge timing adjustment circuit, and FIGS. 13 and 14 are block diagrams and explanations of other embodiments of the fine adjustment circuit included in the edge timing adjustment circuit. FIG. 04 is a key signal forming circuit, 01 is a key processor, (1
81 is a mixer, (2 is an edge timing adjustment circuit,
Shift and coarse adjustment circuit, (C) fine adjustment circuit, (4)
01 is a control logic circuit, 541 (551 is a level comparison circuit.)

Claims (1)

[Claims] a delay unit that is supplied with a digital key signal formed to correspond to a partial area of the digital video signal and forms first and second digital key signals having a phase difference that is an integral multiple of the sampling period; means for detecting a leading edge and a trailing edge of the digital key signal; and a control signal for selecting and outputting one of the first and second digital key signals based on the detection output and an expansion or compression instruction. and means for expanding or compressing the front edge and the rear edge of the digital key signal by an amount that is an integral multiple of the sampling period.