JPS589383Y2 - pulse amplification circuit - Google Patents

pulse amplification circuit

Info

Publication number
JPS589383Y2
JPS589383Y2 JP1977117054U JP11705477U JPS589383Y2 JP S589383 Y2 JPS589383 Y2 JP S589383Y2 JP 1977117054 U JP1977117054 U JP 1977117054U JP 11705477 U JP11705477 U JP 11705477U JP S589383 Y2 JPS589383 Y2 JP S589383Y2
Authority
JP
Japan
Prior art keywords
pulse
amplification circuit
circuit
transformer
pulse amplification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1977117054U
Other languages
Japanese (ja)
Other versions
JPS5442452U (en
Inventor
塩野達夫
岡田和久
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1977117054U priority Critical patent/JPS589383Y2/en
Publication of JPS5442452U publication Critical patent/JPS5442452U/ja
Application granted granted Critical
Publication of JPS589383Y2 publication Critical patent/JPS589383Y2/en
Expired legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Description

【考案の詳細な説明】 本考案はパルス増巾回路に関し、特にレーダ用送信装置
に有用なサグ補正を施したパルス増幅回路に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse amplification circuit, and more particularly to a pulse amplification circuit with sag correction useful for radar transmitters.

従来この種のパルス増幅回路は第1図のような回路構成
を採用しており、複数の連続パルスein(第2図a参
照)を増幅する場合にトランスTを介した出力電圧e。
Conventionally, this type of pulse amplification circuit has adopted a circuit configuration as shown in FIG. 1, and when a plurality of continuous pulses ein (see FIG. 2a) are amplified, the output voltage e is generated through a transformer T.

gがトランスT自身の磁気的特性に起因するサグが発生
し出力電圧e。
When g occurs, a sag occurs due to the magnetic characteristics of the transformer T itself, and the output voltage e.

gは時間とともに低下してしまい(第2図す参照)、又
、第2図Cに示す如く真空管v2のグリッドに流れる電
流icgも減少するという欠点があった。
g decreases with time (see FIG. 2), and the current icg flowing through the grid of the vacuum tube v2 also decreases, as shown in FIG. 2C.

本考案の目的は上記サグによる出力レベルの低下の補正
を可能にしたパルス増幅回路を提供することにある。
An object of the present invention is to provide a pulse amplification circuit that makes it possible to correct the drop in output level due to the sag.

かかる目的を達成するため本考案によるパルス増幅回路
は、トランス結合忙よるパルス増幅回路において、コン
デンサと抵抗が並列接続された並列回路と、ダイオード
とが直列に接続された直列回路を前記トランスの二次側
に並列に接続したことを特徴とする。
In order to achieve this object, the pulse amplification circuit according to the present invention combines a parallel circuit in which a capacitor and a resistor are connected in parallel, and a series circuit in which a diode is connected in series in a transformer-coupled pulse amplification circuit. It is characterized by being connected in parallel to the next side.

次に本考案の一実施例を図面を参照して説明する。Next, an embodiment of the present invention will be described with reference to the drawings.

本考案の一回路例を示す第3図を参照するとトランスT
の二次側と真空管v2のグリッド間に抵抗R1の一方の
端子を接続し別の端子にダイオードDのアノードを接続
する。
Referring to FIG. 3, which shows an example of the circuit of the present invention, the transformer T
One terminal of the resistor R1 is connected between the secondary side of the V2 and the grid of the vacuum tube V2, and the anode of the diode D is connected to the other terminal.

ダイオードDのカソードにはコンデンサC1と抵抗R2
の並列回路を接続し、この並列回路の別の端子をトラン
スTの二次側の別端子に接続する。
A capacitor C1 and a resistor R2 are connected to the cathode of the diode D.
A parallel circuit is connected, and another terminal of this parallel circuit is connected to another terminal on the secondary side of the transformer T.

次に第3図の各部の動作について各部の信号のタイムチ
ャートを示す第4図を参照して説明する。
Next, the operation of each section in FIG. 3 will be explained with reference to FIG. 4, which shows a time chart of signals of each section.

第3図における真空管v1のグリッドに複数のパルス列
第4図aに示すeinを人力し、真空管■1のプレート
で電圧増幅してトランスTの一次側に導く。
A plurality of pulse trains ein shown in FIG. 4a are manually applied to the grid of vacuum tube v1 in FIG.

トランスTの二次側の出力レベルは前記従来例ではトラ
ンスのサグ特性により第2図すに示すように後のパルス
になるに従って出力レベルが低下するが、本発明による
サグ補正回路では抵抗R1にトランスTの二次電流ic
が流れコンデンサC1を充電するためコンデンサC1の
一端の電位8cが上昇しく第4図す参照)、第一番目の
パルスで流れる二次電流i。
In the conventional example, the output level on the secondary side of the transformer T decreases as the pulses become later, as shown in Figure 2, due to the sag characteristics of the transformer, but in the sag correction circuit according to the present invention, Secondary current ic of transformer T
flows and charges the capacitor C1, so that the potential 8c at one end of the capacitor C1 rises (see Figure 4), and the secondary current i flows at the first pulse.

よりも第二番目のパルスで流れる二次電流icの方が減
少し、第4図Cに示すicのように後のパルスになるに
従って電流が減少する。
The secondary current ic flowing in the second pulse decreases more than that in the second pulse, and as shown in ic shown in FIG. 4C, the current decreases as the pulse progresses.

即ちトランスTの二次側の負荷は後のパルスになるに従
って軽くなるため第4図dの様に次第に出力パルスec
gは振幅が大きくなりパルスのピーク電圧及びパルス幅
をほぼ一定にすることができる。
In other words, since the load on the secondary side of the transformer T becomes lighter as the pulse progresses, the output pulse ec gradually decreases as shown in Fig. 4d.
The amplitude of g increases, and the peak voltage and pulse width of the pulse can be kept almost constant.

従ってグリッド電流icgも第4図eに示すicgのよ
うに一定とすることができる。
Therefore, the grid current icg can also be made constant as icg shown in FIG. 4e.

なお図中ダイオードDはコンデンサC1に充電した電荷
が抵抗R1に逆流するのを防ぐためのものであり、抵抗
R2はコンデンサC0に充電した電荷を次のパルス列が
来るまでに放電させるための抵抗である。
Note that the diode D in the figure is used to prevent the charge charged in the capacitor C1 from flowing back to the resistor R1, and the resistor R2 is a resistor used to discharge the charge charged in the capacitor C0 before the next pulse train arrives. be.

本考案は以上説明した如く第3図に示した回路を構成し
、抵抗R1・R2、コンデンサC1の定数を適当に選択
することによりトランス結合によるパルス増幅回路にお
けるサグを除去することが可能であり、本考案による変
調器を使用した送信機では、サグが除去されたて定レベ
ルのパルス列の信号を送信することが可能となる。
As explained above, the present invention configures the circuit shown in FIG. 3, and by appropriately selecting the constants of resistors R1 and R2 and capacitor C1, it is possible to eliminate sag in the pulse amplification circuit due to transformer coupling. A transmitter using the modulator according to the present invention can transmit a constant-level pulse train signal with sag removed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のパルス増幅回路、第2図は第1図におけ
る各部の動作波形図、第3図は本考案によるパルス増幅
回路図、第4図は第3図における各部の動作波形図であ
る。
Fig. 1 is a conventional pulse amplification circuit, Fig. 2 is an operating waveform diagram of each part in Fig. 1, Fig. 3 is a pulse amplification circuit diagram according to the present invention, and Fig. 4 is an operating waveform diagram of each part in Fig. 3. be.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] トランス結合によるパルス増幅回路において、コンデン
サと抵抗が並列接続された並列回路と、ダイオードおよ
び抵抗とが直列に接続された直列回路を前記トランスの
二次側に並列に接続したことを特徴とするパルス増幅回
路。
A pulse amplification circuit using transformer coupling, characterized in that a parallel circuit in which a capacitor and a resistor are connected in parallel, and a series circuit in which a diode and a resistor are connected in series are connected in parallel to the secondary side of the transformer. Amplification circuit.
JP1977117054U 1977-08-30 1977-08-30 pulse amplification circuit Expired JPS589383Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1977117054U JPS589383Y2 (en) 1977-08-30 1977-08-30 pulse amplification circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1977117054U JPS589383Y2 (en) 1977-08-30 1977-08-30 pulse amplification circuit

Publications (2)

Publication Number Publication Date
JPS5442452U JPS5442452U (en) 1979-03-22
JPS589383Y2 true JPS589383Y2 (en) 1983-02-21

Family

ID=29070143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1977117054U Expired JPS589383Y2 (en) 1977-08-30 1977-08-30 pulse amplification circuit

Country Status (1)

Country Link
JP (1) JPS589383Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513765A (en) * 1974-06-28 1976-01-13 Nippon Electric Co PARUSUHENCHOKI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513765A (en) * 1974-06-28 1976-01-13 Nippon Electric Co PARUSUHENCHOKI

Also Published As

Publication number Publication date
JPS5442452U (en) 1979-03-22

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