JPS5890689A - Manufacture of matrix type liquid crystal display - Google Patents

Manufacture of matrix type liquid crystal display

Info

Publication number
JPS5890689A
JPS5890689A JP56191126A JP19112681A JPS5890689A JP S5890689 A JPS5890689 A JP S5890689A JP 56191126 A JP56191126 A JP 56191126A JP 19112681 A JP19112681 A JP 19112681A JP S5890689 A JPS5890689 A JP S5890689A
Authority
JP
Japan
Prior art keywords
liquid crystal
crystal display
matrix type
electrode
tft array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56191126A
Other languages
Japanese (ja)
Other versions
JPH0587811B2 (en
Inventor
隆夫 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56191126A priority Critical patent/JPS5890689A/en
Publication of JPS5890689A publication Critical patent/JPS5890689A/en
Publication of JPH0587811B2 publication Critical patent/JPH0587811B2/ja
Granted legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は複数個のゲート線、及びゲート線と直交する
複数個のソース線を備え、その各交点にTPT等の能動
素子及び蓄積コンデンサー等よりなるマトリクス型液晶
表示装置の製造方法に関するものである。
Detailed Description of the Invention The present invention provides a matrix type liquid crystal display device comprising a plurality of gate lines and a plurality of source lines orthogonal to the gate lines, and an active element such as a TPT, a storage capacitor, etc. at each intersection point. The present invention relates to a manufacturing method.

第1図はTFTアレイの構成を、第2図はマトリクス型
カラー液晶表示装置の構成を説明するための断面構造図
である。
FIG. 1 is a cross-sectional structural diagram for explaining the configuration of a TFT array, and FIG. 2 is a cross-sectional structural diagram for explaining the configuration of a matrix type color liquid crystal display device.

図において、(1)はゲート線、(2)はソース線、(
3)はドレイン電極、(4)はTPT、(5)は表示電
極、(6)は蓄積コンデンサー、(7)は液晶、(8)
はTFTアレイ、(9)はTFTアレイ基板、叫は透明
導電膜、0υはカラーフィルター、(6)は対向基板、
α4はマトリクス型カラー液晶表示装置、04は外部光
を示している。
In the figure, (1) is a gate line, (2) is a source line, (
3) is the drain electrode, (4) is the TPT, (5) is the display electrode, (6) is the storage capacitor, (7) is the liquid crystal, (8)
is a TFT array, (9) is a TFT array substrate, 0 is a transparent conductive film, 0υ is a color filter, (6) is a counter substrate,
α4 indicates a matrix type color liquid crystal display device, and 04 indicates external light.

従来、この種の装置として第8図、第4図に示すものが
あった。第8図はTFTアレイ画素の部分平面図、第4
図は第8図A −A’部の断面構造図を示したものであ
る。
Conventionally, there have been devices of this type as shown in FIGS. 8 and 4. FIG. 8 is a partial plan view of the TFT array pixel,
The figure shows a cross-sectional structural diagram of the section A-A' in FIG. 8.

図において、(1)はゲート線、(2]はソース線、(
3)はドレイン電極、(5)は表示電極、(9)はTF
Tアレイ基板、α均は半導体、a6は5iOz、αηは
ゲート絶縁膜%(至)はドープドポリシリコン、αりは
ソース領域。
In the figure, (1) is a gate line, (2) is a source line, (
3) is the drain electrode, (5) is the display electrode, and (9) is the TF.
T array substrate, α average is semiconductor, a6 is 5iOz, αη is gate insulating film % (to) doped polysilicon, α is source region.

翰はドレイン領域、C!υはPSG膜、に)は1−間絶
縁膜、(至)は蓄積コンデンサー電極、■は誘電体を示
している。
The pen is the drain area, C! υ is a PSG film, 2) is an insulating film between 1 and 2, (to) is a storage capacitor electrode, and 2 is a dielectric.

まず第1図、第2図とともにマトリクス型カラー液晶表
示装置の構成を説明する。マトリクス型カラー液晶表示
装置α]は、複数個のゲート線(1)。
First, the structure of a matrix type color liquid crystal display device will be explained with reference to FIGS. 1 and 2. The matrix type color liquid crystal display device α] has a plurality of gate lines (1).

及びこれらのゲート線と直交するソース線(2)とを備
え、その交点に例えばT P T (4) 4の能動素
子が形成されそのドレイン電極(3)、表示電極(5)
、信号蓄積コンデンサー(6)を有する構造のTFTア
レイ(8)を形成したTFTアレイ基板(9)と、これ
と対向する透明導電膜(10,赤、緑、青等のカラーフ
ィルターαυを有する対向基板(6)、及びこの両基板
(9)、(2)の間に液晶(7)が挾持された1造とな
っており、これに外部光(141が照射される構造にな
っている。
and a source line (2) orthogonal to these gate lines, and an active element, for example T P T (4) 4, is formed at the intersection thereof, and its drain electrode (3) and display electrode (5) are provided.
, a TFT array substrate (9) on which a TFT array (8) having a structure having a signal storage capacitor (6) is formed, and an opposing transparent conductive film (10) having a color filter αυ of red, green, blue, etc. It has a structure in which a liquid crystal (7) is sandwiched between a substrate (6) and both substrates (9) and (2), and is irradiated with external light (141).

ひき続き、従来のTFTアレイ(8)を第8図、第4図
により説明する。TFTアレイ(8)は、ガラス等の絶
縁基板よりなるTFTアレイ基板(9)の表面に、例え
ばポリシリコン等の半導体0Gを減圧CVD法等で成1
漢し、SiN等のマスクをもちいてTPT形成部OG、
以外の部分のポリシリコンを選択酸化した5i02αG
を形成した後、ゲート絶縁膜07)を例えば熱酸化法等
で形成、ひき続きボロン等の不純物をドーピングしたド
ープドポリシリコン(ト)を成膜した後にゲートαη、
(至)のパターンニングを実施する。
Next, the conventional TFT array (8) will be explained with reference to FIGS. 8 and 4. The TFT array (8) is formed by forming 0G of a semiconductor such as polysilicon on the surface of a TFT array substrate (9) made of an insulating substrate such as glass by low pressure CVD or the like.
TPT forming part OG using a mask of SiN etc.
5i02αG with selective oxidation of polysilicon in other parts
After forming the gate insulating film 07) by, for example, a thermal oxidation method, and subsequently forming a film of doped polysilicon (T) doped with an impurity such as boron, the gates αη,
(to) Perform patterning.

この後ソース領域−、及びドレイン項域(ホ)に例えば
砒素等の不純物をイオン注入する。ひき続きリン、ガラ
スωSG)膜(2)をCVD法等で成膜しパターンニン
グして、ソース線(2)、及びドレイン電極(3)とな
るAIを例えば蒸着法等で形成する。
Thereafter, ions of impurity such as arsenic are implanted into the source region and the drain region (e). Subsequently, a phosphorus, glass ωSG) film (2) is formed and patterned by a CVD method or the like, and AI, which will become a source line (2) and a drain electrode (3), is formed by, for example, a vapor deposition method.

又、この後蓄積コンデンサーX毬礪(至)となるITO
(インジウム、スズ酸化物)を蒸着法で形成し、ゲート
線(1)とソース線(2〕との層間絶縁膜(2)及び蓄
積コンデンサーの誘電体iとなる例えば5i01+スパ
ツター法等で形成した後に、蓄積コンデンサーの上部電
極と表示電極(5)を兼ねるITOよりなる透明゛電極
を例えば蒸着法等で形成し、先に形成したドレイン電極
(3)に接続し、ゲート線+1)となるA1を例えば蒸
着法で形成してTFTアレイ(8)を完成する。
Also, ITO, which will later become the storage capacitor
(indium, tin oxide) was formed by a vapor deposition method, and the interlayer insulating film (2) between the gate line (1) and the source line (2) and the dielectric material i of the storage capacitor were formed by, for example, a 5i01+ sputtering method. Later, a transparent electrode made of ITO, which serves as the upper electrode of the storage capacitor and the display electrode (5), is formed by, for example, vapor deposition, and connected to the drain electrode (3) formed earlier, forming the gate line A1 (gate line +1). is formed by, for example, a vapor deposition method to complete the TFT array (8).

従来のTFTアレイ(8)は以上のように構成されてい
るのでリン酸素エツチング液でAIをエツチングしてソ
ース線(2)、ドレイン電極(3)を形成した後に、塩
化第2−鉄を含有する塩酸系エツチング液でITOをエ
ツチングして蓄積コンデンサー電極(ハ)及び表示電極
(5)を形成しなければならず、先に形成する゛)−ス
ミ極及びドレイン電極のA1表面が。
Since the conventional TFT array (8) is constructed as described above, after etching the AI with a phosphorus-oxygen etching solution to form the source line (2) and drain electrode (3), the TFT array (8) containing ferric chloride is etched. The storage capacitor electrode (c) and display electrode (5) must be formed by etching the ITO with a hydrochloric acid-based etching solution.

塩化第2鉄を含有する塩酸素エツチング液により、腐蝕
、酸化され、例えばドレイン′(極と表示電極間の電気
的コンタクトの不良、又は断線が多発する等の欠陥があ
り、この方法によったTFTアレイ、及びこのTFTア
レイを用いたマトリクス型液晶表示装置は製造歩留が悪
ろく、又寿命が短いといった欠陥があった。
The salt-oxygen etching solution containing ferric chloride corrodes and oxidizes the electrodes, resulting in defects such as poor electrical contact between the drain electrode and the display electrode, or frequent disconnections. TFT arrays and matrix type liquid crystal display devices using these TFT arrays have drawbacks such as poor manufacturing yields and short lifespans.

この発明は前述のような従来のものの欠点を除去するた
めになされたもので、TFTアレイの製造において、I
TO形成部のエツチングをす4て完了した後に、AI等
の電極形成部のエツチングを実権する方法により、再現
性、製造歩留が高く、長寿命のTFTアレイ、及びマト
リクス型液晶表示装置を提供することを目的としている
This invention was made in order to eliminate the drawbacks of the conventional ones as mentioned above.
We provide TFT arrays and matrix-type liquid crystal display devices with high reproducibility, high manufacturing yield, and long life by using a method in which the etching of the electrode formation part, such as AI, is actually performed after the etching of the TO formation part is completed. It is intended to.

以下この発明の一実施例を第5図、第6図により説明す
る。
An embodiment of the present invention will be described below with reference to FIGS. 5 and 6.

第5図は本発明の一実施例をTFTアレイ画素の部分平
面図、第6図は第5図A −A’部の断面4造図を示し
たものである。
FIG. 5 is a partial plan view of a TFT array pixel according to an embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line A-A' in FIG.

図において(りはゲート線、(2)はソース線、(3)
はドレイン電極、(5)は表示電極、(9)はTFTア
レイ基板、α均は半導体、αGはSing、07)はゲ
ート絶縁膜、α榎はドープドポリシリコン、0呻はソー
ス領域、(1)1ドレイン領域、(2)はPSG膜、磐
は1間絶縁膜、(至)蓄積コンデンサー電極、(財)は
誘電体を示している。
In the figure (ri is the gate line, (2) is the source line, (3)
is the drain electrode, (5) is the display electrode, (9) is the TFT array substrate, α is the semiconductor, αG is Sing, 07) is the gate insulating film, α is the doped polysilicon, 0 is the source region, ( 1) 1 drain region, 2) PSG film, 1 insulating film, (to) storage capacitor electrode, 2) dielectric.

ひき続きその構成を説明する。The structure will be explained next.

TFTアレイはガラス等の絶縁基板よりなる。The TFT array is made of an insulating substrate such as glass.

TFT7レイ基板(9)の表面に例えばポリシリコン等
の半導体(ハ)を減圧CVD法等で設け、 SiN等の
マスクをもちいて、TPT形成部a8以外の部分のポリ
シリコン等を選択酸化した5iOz Lllを形成した
後、ゲート絶縁膜αηを例えば熱酸化法等で形成し。
A semiconductor (c) such as polysilicon is provided on the surface of the TFT7 lay substrate (9) by a low pressure CVD method, etc., and using a mask such as SiN, selectively oxidizes the polysilicon etc. in areas other than the TPT forming area a8. After forming Lll, a gate insulating film αη is formed by, for example, a thermal oxidation method.

ひき続きボロン等の不純物をドーピングしたドープドポ
リシリコン(至)を成膜した後に、ゲート0η、(至)
のパターンニングを実施する。
After successively forming a film of doped polysilicon doped with impurities such as boron, the gate 0η, (to) is formed.
Perform patterning.

この後ソース領域QQ、及びドレイン領域に)に例えば
砒素等の不純物をイオン注入する。ひき続きリンガラス
(PSG)膜Q珍をCVD法等で形成する。
Thereafter, impurity ions such as arsenic are ion-implanted into the source region QQ and drain region. Subsequently, a phosphor glass (PSG) film Q is formed by a CVD method or the like.

この後、蓄積コンデンサー、電極(2)となるITOを
例えば蒸着法等で成膜し、塩化第二鉄を含有する塩酸系
エツチング液でパターンエツチングし、引き続き蓄積コ
ンデンサーの誘電体(財)となる例えば5i02をスパ
ッター法等で形成した後、可変表示?ぼ極(6)と蓄積
コンデンサーの上部電極を兼ねるITOよりなる透明電
極を例えば蒸着法等で成膜した後、塩化第二鉄を含有す
る塩酸系エツチング液I  でパターンエツチングする
。この後、ソーX 線(2)及びドレイン電極(3)と
なるAIを例えば蒸着法等で成膜した後、リン酸系エツ
チング液でパターンエツチングし、ドレイン電極(3)
を先に形成した表示電極(5)に接続する。この後、ソ
ース線(2)とゲート線(1)との眉間絶縁/Illと
なる例えば5i02をスパッター法等で形成した後、再
度、ゲート線(1)となるAIを蒸着法等で成膜し、リ
ン酸系エツチング液でパターンエツチングして、TFT
アレイ(8)が完成゛する。
After this, ITO, which will become the electrode (2) of the storage capacitor, is formed into a film by, for example, a vapor deposition method, and then pattern-etched with a hydrochloric acid-based etching solution containing ferric chloride, which will subsequently become the dielectric material (material) of the storage capacitor. For example, after forming 5i02 by sputtering method etc., is there a variable display? After forming a transparent electrode made of ITO, which also serves as the void electrode (6) and the upper electrode of the storage capacitor, by, for example, a vapor deposition method, pattern etching is performed using a hydrochloric acid-based etching solution I containing ferric chloride. After this, after forming a film of AI that will become the saw X-ray (2) and the drain electrode (3) by, for example, a vapor deposition method, pattern etching is performed using a phosphoric acid etching solution to form the drain electrode (3).
is connected to the previously formed display electrode (5). After this, for example, 5i02, which will become the glabellar insulation/Ill between the source line (2) and the gate line (1), is formed by sputtering, etc., and then AI, which will become the gate line (1), is again formed by vapor deposition, etc. Then pattern-etch the TFT using a phosphoric acid etching solution.
Array (8) is completed.

本発明によるTFTアレイは以上のように、蓄積コンデ
ンサー電極(至)、及び表示電極(5)にもちいたIT
Oを塩化第二鉄を含有する塩酸系エツチング液でパター
ンエツチングした後に、ソース線Q)、ドレイン電極(
3)、及びゲート線(11にもちいたAIをリン酸系エ
ツチング液でパターンエツチングするように構成したの
で、ソース線で2)、ドレイン電極E極(3)を構成す
るAIが従来例のよう炉、ITOの塩化第二鉄を含有す
る塩酸系エツチング液に接触することがなく、又Alの
エツチング液にもちいるリン酸系エツチング液に対して
ITOは十分に安定であるため、ドレイン電極(3)と
表示[極(5)間の電気的コンタクトは良好かつ安定で
、断線等が生じない。
As described above, the TFT array according to the present invention uses IT for the storage capacitor electrode (5) and the display electrode (5).
After pattern etching O with a hydrochloric acid etching solution containing ferric chloride, the source line Q) and drain electrode (
3), and the gate line (11) was pattern-etched using a phosphoric acid-based etching solution, so the AI used for the source line 2) and the drain electrode E electrode (3) was changed as in the conventional example. The drain electrode ( 3) and the display [The electrical contact between the pole (5) is good and stable, and there is no disconnection.

このため、本発明法によったTFTアレイ、及びこのT
FTアレイをもちいたマトリクス型液晶表示装置は製造
歩留が良好で又寿命が長いといらだ特徴を有している。
Therefore, the TFT array according to the method of the present invention and the TFT
Matrix type liquid crystal display devices using FT arrays have a frustrating feature of good manufacturing yield and long life.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、TFTアレイの構成の説明図、第2図はマト
リクス型カラー液晶表示装置の断面構造図、第8図は従
来のTFTアレイ画素の部分平面図、第4図は第8図へ
−に部の断面構造図、第5図は本発明のTFTアレイ画
素の部分平面図、第6図は第5図A −A’部の断面構
造図である。 :A中、(1)はゲート線、(2)はソース線、(3)
はドレイン1極、(5)は表示電極、@は蓄積コンデン
サー゛4極である。 なお1図中同一行合は同−又は相当部分を示している。 代理人  葛 舒 信 − 第1図 8 第2図 第3図 第4図 手続補正書(自発) 昭和 5η 1川 1〜 1、事件の表示    特願昭 511−11111重
6号事件との関係   特許出願人 代表者片山仁へ部 4、代理人 住 所     東京都千代田区丸の内二丁目2番3号
6、補正の対象 明細書の発明の詳細な説明の欄および図面6、補正の内
容 (11明細書の第6頁、第4行の「リン酸素」を「リン
酸系」と訂正する。 (2)同第6頁第1θ行の「塩酸素」を「塩酸系」と訂
正する。 (3)同第6頁第6行の「実施例を」を「実施例の」と
訂正する。 (4)図面の第2図を別紙複写図に未配したとおり訂正
する。 ?、 添付書類の目録 (1シ図面(第2図)        1通以上 第2図
Figure 1 is an explanatory diagram of the configuration of a TFT array, Figure 2 is a cross-sectional structural diagram of a matrix type color liquid crystal display device, Figure 8 is a partial plan view of a conventional TFT array pixel, and Figure 4 is directed to Figure 8. 5 is a partial plan view of the TFT array pixel of the present invention, and FIG. 6 is a sectional structural diagram of the section A-A' in FIG. :In A, (1) is the gate line, (2) is the source line, (3)
1 is the drain pole, (5) is the display electrode, and @ is the storage capacitor (4 poles). Note that the same lines in Figure 1 indicate the same or equivalent parts. Agent Ge Shu Xin - Figure 1, Figure 8, Figure 2, Figure 3, Figure 4, Procedure amendment (voluntary) Showa 5η 1 River 1-1, Indication of case Relationship to patent application Showa 511-11111 case No. 6 Patent Representative Hitoshi Katayama, Department 4, Agent Address: 2-2-3-6, Marunouchi 2-chome, Chiyoda-ku, Tokyo, Detailed Description of the Invention and Drawing 6 in the Specification Subject to Amendment, Contents of the Amendment (11 Specifications) "Phosphorous oxygen" on page 6, line 4 of the book is corrected to "phosphoric acid type". (2) "Salt oxygen" on page 6, line 1θ of the same book is corrected as "hydrochloric acid type". (3 ) Correct "Example" in line 6 of page 6 to "Example of Example". (4) Correct Figure 2 of the drawings to indicate that it has not been placed in the attached copy. ?, List of attached documents (1 drawing (Fig. 2) 1 copy or more Fig. 2)

Claims (1)

【特許請求の範囲】[Claims] 複数個のゲート線及びゲート線に直交する複数個のソー
ス線を備えその交点に薄膜トランジスター(以下TPT
と称す)等の能動素子及び蓄積コンデンサー等よりなる
TFTアレイを形成した基板と、透明導電膜及びカラー
フィルターを形成した対向基板とを有し、前記側基板間
に液晶を挾持した構造のマトリクス型液晶表示装置の製
造方法ニオイて、表示電極、及び蓄積コンデンサー電極
等を構成するインジウム及びス女の酸化物のエツチング
を完了した後にTPTのゲート線、ソース線、及ヒトレ
イン電極等を構成するアルミニムのエツチングを実施す
ることを特徴としたマトリクス型液晶表示装置の製造方
法。
It has a plurality of gate lines and a plurality of source lines orthogonal to the gate lines, and a thin film transistor (hereinafter referred to as TPT) is installed at the intersection point.
A matrix type having a structure in which a substrate is formed with a TFT array consisting of active elements such as (referred to as ) and storage capacitors, and a counter substrate is formed with a transparent conductive film and a color filter, and a liquid crystal is sandwiched between the side substrates. In the manufacturing method of a liquid crystal display device, after completing the etching of the indium and tin oxides that make up the display electrodes, storage capacitor electrodes, etc., the aluminum that makes up the gate lines, source lines, and train electrodes of the TPT is etched. A method of manufacturing a matrix type liquid crystal display device characterized by performing etching.
JP56191126A 1981-11-25 1981-11-25 Manufacture of matrix type liquid crystal display Granted JPS5890689A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56191126A JPS5890689A (en) 1981-11-25 1981-11-25 Manufacture of matrix type liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56191126A JPS5890689A (en) 1981-11-25 1981-11-25 Manufacture of matrix type liquid crystal display

Publications (2)

Publication Number Publication Date
JPS5890689A true JPS5890689A (en) 1983-05-30
JPH0587811B2 JPH0587811B2 (en) 1993-12-20

Family

ID=16269296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56191126A Granted JPS5890689A (en) 1981-11-25 1981-11-25 Manufacture of matrix type liquid crystal display

Country Status (1)

Country Link
JP (1) JPS5890689A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5386593A (en) * 1977-01-10 1978-07-31 Matsushita Electric Ind Co Ltd Production of color picture image display device
JPS552266A (en) * 1978-06-20 1980-01-09 Matsushita Electric Ind Co Ltd Image display unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5386593A (en) * 1977-01-10 1978-07-31 Matsushita Electric Ind Co Ltd Production of color picture image display device
JPS552266A (en) * 1978-06-20 1980-01-09 Matsushita Electric Ind Co Ltd Image display unit

Also Published As

Publication number Publication date
JPH0587811B2 (en) 1993-12-20

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