JPS5885562A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to discover improper bit without error in a short time by breaking periodicity and arranging bits at every several memory cells. CONSTITUTION:After 10 memory cells 1 are arranged, i.e., after 10Xamum isolated, 10 cells are again arranged in column at an interval of Amum (which is different from amum), are then arranged again at Amum, and are repeated until reaching necessary number. Memory cells are similarly arranged also in rows. In this manner, in case, for example, of 57-th rows, it is not counted sequentially from the first one by one, but it is counted from the fifth interval of Amum to seventh memory cell. Thus, even if it is counted under microscope, it does not take a plenty of time, and it does not mistake.

Description

[Detailed description of the invention] The present invention relates to a semiconductor device.

2. Description of the Related Art In recent years, with advances in semiconductor device manufacturing technology, the number of bits of random access memory (hereinafter abbreviated as BAM) has increased. On the other hand, technology for analyzing defective bits has also advanced, and if a certain bit of B/AM does not function properly, it is possible to identify the defective bit. A tester that outputs the location in the form of a so-called bitmap has also been developed. However, when it comes to 16,384-bit memory, the memory cells are arranged in one 128 row x 128 column arrangement or two 128 rows x 64 columns arrangement, and defective bit positions are detected on the semiconductor substrate using a microscope. Counting is very time consuming and error prone.

An object of the present invention is to provide a semiconductor device having means for completely eliminating such difficulties.

The present invention resides in a semiconductor device in which the periodicity of a large number of memory cells arranged at a constant pitch is broken every predetermined integral multiple of the pitch.

According to the present invention, it is possible to easily identify defective billers.

The present invention will now be described in detail with reference to all the drawings.

FIG. 1 is a plan view of a semiconductor substrate according to an embodiment of the present invention. The length of the memory cell 1 is a μm vertically and b μm horizontally, and after 10 memory cells 1 are arranged vertically, that is, 1
After 0 × a μm away (this is different from 3 μm)
After 10 pieces are arranged vertically again at intervals, Aμ
The arrangement is repeated with m intervals until the required number is reached. Similarly, for the horizontal arrangement, after 10 memory cells 1 are arranged horizontally, the same process is repeated again at intervals of B μm.

Instead of arranging all the required number of rows, for example 128, at a fixed pitch of 3 μm as in the conventional method, they are spaced at intervals of A μm every 10 pitches, that is, every 10 × a μm. In this way, for example, in the case of the 57th row, instead of counting one memory cell at a time from the beginning, you can count from the 5th bud at intervals of Aμm, and then count the 7th memory cell, and so on. Even if you count them under a full microscope, it doesn't take much time and there's no chance of making a mistake.

Although the above explanation has been made only for the rows (vertical) of the memory cell array, the same applies to the columns (horizontal).

Further, the structure that destroys the periodicity may be other than spacing.

For example, in the case of 3 μm=A μm, the regions spaced apart by A μm may be left open without forming any circuit elements such as memory cells. In this case, by visual inspection, it is possible to immediately distinguish between a memory cell portion and a portion without a memory cell portion.

As for the pitch, an example of 10 pitches was given, but 8 pitches were given.
Other natural numbers such as pitch may also be used.

As described above, according to the present invention, all defective pits can be found without fail in a short time.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an embodiment of the invention. In the top view, 1... memory cell.

Claims (2)

[Claims] (1) A semiconductor device in which a large number of memory cells are arranged on a semiconductor substrate, characterized in that the large number of memory cells are arranged with irregularity every certain number of memory cells. (2) Does the configuration in which the periodicity is broken and the memory cells are arranged have different pitches? A semiconductor device according to claim (1).