JPS5884557A - Conversion circuit for 4b-3t code - Google Patents

Abstract

PURPOSE:To obtain a 4B-3T code converting circuit which does not cause malfunction to decide by majority, without making an error of 1-bit generated on a transmission line greater than 2-bit, by scattering codes causing errors to be parted >=4-bit. CONSTITUTION:When a code train is inputted from an input terminal 16, a sequential 4-bit code is stored in 1-bit storage circuits 17-20, and in transferring the content of storage to one-bit storage circuits 21-24 at each 4-bit, data of 4-bit intervals of the code train is sequentially stored to the circuits 21-24. When 4-bit delay circuits 25-30 connected to the storage circuis 21-23 respectively execute bit delay of 12, 8, 4, a data is inputted to input points J-M of a converting circuit 31, 4B-3T code conversion is performed with the combination of codes and converted into pulses of + and - polarity, and transmitted to a transmission line. At the reception side, reproduction is peformed with the inversion and a 4-bit delay circuit. In passing through the transmission line, the pulse section in 3-bit can be corresponded to the combination of codes in 5-bit intervals.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a code conversion circuit that is used, for example, in pulse regeneration relay transmission and creates a multi-pulse code string to be sent to a transmission path.

In addition to data, the pulse code string transmitted on the transmission line also contains data! It often includes rounded control codes to reliably control the various devices connected to each other, and is usually transmitted uniformly over the transmission path without distinguishing between service data and control code sequences. be. In general, in pulse regenerative relay transmission, the transmitted code has a pulse waveform that is suitable for the repeaters that make up the transmission path, and is converted into a code string configuration of an optimal format before being sent out. Code conversion in such cases is performed at the terminal relay equipment connected to both ends of the transmission line, and it is the receiver's responsibility to separate the data and control code strings from the code strings received across the transmission line. This is often carried out in a terminal relay device or a receiving device connected Km thereto.

When a pulse regeneration relay transmission line is configured by connecting a plurality of repeaters, pulse regeneration w4 may sometimes occur. However, even if an error occurs on the transmission path, care is usually taken to minimize the number of erroneous lines in the control code. For example, when allocating 3 bits as a device control code, on the transmitting side, when the code is 1, all 3 bits are set as the code level, and when the code is 00, all 3 bits are sent as the code level 0. On the other hand, in the receiving device,
Extract the device control code from the received code string, make a majority decision using the 3-bit pulses, and if it is 2 bits or more, it is judged as a level, and if 2 bits or more is O level, it is judged as θ level. In some cases, a preventive measure is taken to prevent an immediate malfunction due to a one-bit error input.

3 consecutive 4-bit code divisions of a binary code string as a unit
The combination of ten-polar and unipolar pulses is mixed and uniformly corresponded to nine pulse train segments, and sent to the transmission path. On the receiving side, the pulse train segments that have more units than the received pulse train are extracted, and are combined into nine pulse train segments. In combination with unipolar, 4-bit 2
4B made up of 41m to convert back to 100 million code classification
A corresponding example of ~3T code conversion is shown in FIG. Further, FIG. 2 shows the configuration of a conventional 4B-37 code conversion circuit, and FIG. 3 shows the configuration of a conventional 4B-3T inverse conversion circuit.

In FIG. 2, a continuous binary code string ti inputted from the input terminal 1 is sequentially stored in four 1-bit storage circuits 2, 3, 4. 2
The contents of each memory are simultaneously transferred to the memory circuit 6゜7.8.9, and the stored values of these memory circuits 9゜8.7.6 are transferred to the conversion circuit 1.
It is supplied as a combination code every 4 bits to the 0 input point ABCD. The conversion circuit 10 converts the pulses into a combination of + polarity and unipolar pulses according to the correspondence shown in FIG. 1 according to the sign of the input point ABCD, and sends the pulses from the output terminal 11 to the transmission line.

The 94B-3T inverse conversion is performed at the receiving terminal 1 as shown in Figure 3.
The inverse transform circuit 13 extracts pulse train segments from the received pulse train of 2 and performs inverse transform corresponding to FIG. A combination code corresponding to the FGHK%ABCD point is obtained and sequentially combined in the combination circuit 14 to reproduce the same code string as the terminal l at the output terminal 15.

With this kind of circuit configuration! When 4B-3T code conversion is performed on the transmitting side and the inverse conversion to restore the original state is performed on the receiving side, 111. JIK
A series of pulse train segments in units of 3 bits is transmitted.

As an example of a pulse generated on a transmission path that transmits such a pulse train, if 1 bit *b, which becomes a 3-bit pulse of 10+ 3-bit pulse car++, occurs in the middle of the transmission path, -10+ 3-bit pulse + is converted into the 0101 code string segment, which is an inverse conversion of ttgb. 2
There is a 4I image of special longevity where bits are concentrated in neighborhoods within 4 bits. Therefore, when transmitting using 4B-3T code conversion, it is necessary to particularly consider the spread of errors.

When transmitting the code string subjected to the above preventive measures through a 4B-3T code transmission path, the 1-bit w4 generated on the transmission path
When an error occurs within a unit of a pulse train section corresponding to a control section, the majority decision may be incorrect due to the spread of an error that expands to 2 bits, and this has the disadvantage that problems are likely to occur in the control of the device.

The purpose of this invention is l! It is an object of the present invention to provide a simple 4B-3T code conversion circuit that can solve the above-mentioned drawbacks by dispersing the codes that spread over 4 bits so that they are separated by 4 bits or more.
be.

FIG. 4 shows the configuration of the 4B-3T code conversion circuit of the present invention, and FIG. 5 shows the configuration of the inverse code conversion circuit of the receiving section of the present invention. FIG. 6 shows an example of a Kugata code string.

In Fig. 4, input terminal 16 and code string 43 (Fig. 6)
When input, 1-bit storage circuit 17, 18, 19,
20, consecutive 4-bit codes are sequentially stored.

Memory circuits 20, 19, 18 for every 4 bits of input terminal 16
．． The memory contents of 17 are stored in 1-bit memory circuits 21, 22, 23.
, 24 respectively, the memory circuits 21, 22, 23 .
24 sequentially store data at 4-bit intervals of the input code '43.

When the code string 43 is divided into 4-bit code units, dHl,
dokura, dns, do4 (nWBO, 1, 2,...”
), the storage data of storage circuits 17, 18, 19, and 20 are dta, dport, dim, and da, respectively.
At mO, the memory circuits 21, 22, 23, 24 store 4 bits earlier, dis, do, dma, and d44, respectively. - For example, memory circuits 21, 22, 23
When delayed by 12 bits, 8 bits, and 4 bits by 4-bit delay circuits 25 to 30 connected to
The input point JKLMK of the conversion circuit 31 receives data di4. d
as, dam, dst are input, da4. da
According to the code combination K of the m, dma, and d ports, the pulses are converted into ten-polarity and eleven-polarity pulses according to the correspondence shown in FIG. 1, and are sent to the transmission path from the output terminal 32.

On the receiving side, when the pulse train received at the receiving terminal 33 is inversely converted by the inverse converting circuit 34 according to the correspondence shown in FIG. is played. 4 bit j! 4 bits by extension circuits 35-40,
When delayed by 8 bits and 12 bits, data ds4. dts, d1
snow, d11 is input, and is sequentially combined in the combining circuit 41 to obtain d.
The input code string 43 can be obtained at the output terminal 42 by returning every three bits of the received pulse (K<J) such that st, d, dt, and dt4 are output to the output terminal 42 in this order.

The 3-bit pulse division when passing through the transmission line is coded d.
44. Correspondence is provided by code combinations at 5-bit intervals, such as dss, dma, and dlt. Therefore, the 1-bit itgb that occurred on the transmission path becomes the 2-bit code a! Even if expanded to 4b, the position of the mb code will be dispersed to 9 positions separated by more than 5 bits, and 2 or more erroneous codes will be inserted into the control code string section where majority decision is made using 3-bit codes. This has made it possible to prevent errors in majority decision making. As explained above, according to the present invention, a 1-bit error that occurs on the transmission path can be reduced to 2 bits.
Even if bit errors occur, it is possible to provide a simple 4B-3T code conversion circuit that can avoid errors in majority decision of control codes because the positions of the W14 codes can be distributed.

The above example uses 12 bits, 8 bits, and 4 bits of delay by a 4-bit delay circuit, but the delay cover K
It is clear that the same effect can be obtained regardless of the situation.

[Brief explanation of drawings]

Figure 1 shows an example of code conversion for Mine 4B-37. FIG. 2 shows the configuration of a conventional 4B-3T code conversion circuit. FIG. 3 shows the configuration of a conventional 4B-3T inverse conversion circuit. FIG. 4 shows the configuration of a 4B-3T code conversion circuit according to the present invention. FIG. 5 shows the configuration of the 4B-3T inverse conversion circuit of the present invention. FIG. 6 is a diagram showing an example of an input code string. 1: Input terminal 12.2-9: 1-bit storage circuit, 10:
Conversion circuit, 11: Output terminal, 12: Receiving terminal, 13: Inverse conversion circuit, 14: Coupling circuit, 15: Output terminal, 16: Input terminal, 17-24: 1-bit storage circuit, 25-30:
4-bit delay circuit, 31: conversion circuit, 32: output terminal, 33: reception terminal, 34: inverse conversion circuit, 35-40:4
Bit delay circuit, 41: Coupling circuit, 42: Output terminal, 4
3: Input code string. Patent Applicant NEC Corporation Agent Single Needle Table Figure 1 Figure 73 O Figure 4

Claims (1)

[Claims] (1) Nine digital codes (an
) (H to Q, l, 2, 3, 5eas) 4 code strings obtained by extracting every 4T (a4xL (14 sections ◆t)
e(a4t+g), (ant's) (KmO,1,2
, mamma→, and the code string (bathe(a4x+t), (a4g
+s), (a4g+*) and a delay circuit that delays the delay time 4TO integer times;
), (a4x+*), (a4i+s) before Se slow m1l
The g code string (a' 4IC) obtained through jllt, (
a'<x+t), (a84x+consideration). Let (a'uc+s) be a binary input code, a'ig, a@a
It has nine code conversion circuits that predetermine the correspondence between the code combinations x+t-・4Kll, &'4Kll, the output pulse polarity, and the presence or absence of the output pulse O, and the retardation amount of the retardation circuit is converted into a code string (mail , (la*+t), (aax+s), (a
a*+g) K-qui? The 94B-37 code conversion circuits each have different characteristics.