JPS5884528A - Digital signal wave shaping circuit - Google Patents

Abstract

PURPOSE:To attain wave shaping with fidelity with respect to rapid amplitude fluctuation and DC fluctuation, by setting a voltage inversion reference level inputted to one terminal of a differential comparator to the center between the peaks of an input signal. CONSTITUTION:An input signal vi has an amplitude level suitable to the input amplitude level of a comparator 3 through an amplifier circuit 21 and clamped at a clamping circuit 12. Further, the input signal vi is applied to an amplifier circuit set to a half the gain of the amplifier circuit 21 and the output is applied to a clamping circuit 13. The clamped output at the clamp circuit 13 is rectified at a peak rectifier circuit 23, smoothed at a maximum level of the input signal vi and inputted to an inverting input terminal of the comparator 3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal waveform shaping circuit, and more specifically, a digital signal waveform shaping circuit that shapes the waveform of a digital signal having rapid amplitude fluctuations, DC level fluctuations, and pulses with different duties in a manner faithful to the original signal. It is related to circuits.

In recent years, with the development of computers, magnetic tapes, magnetic disks, etc. have characteristics such as being able to economically record large amounts of digital information, being able to easily rewrite written information, and being able to be stored stably over a long period of time. has developed as the main peripheral storage device for computers. (The recording of digital signals onto a magnetic recording medium such as a magnetic tape-1 magnetic disk is called digital magnetic recording.) Subsequently, an inexpensive microcomputer was developed, and the above-mentioned storage device according to the price of this computer was developed. digital magnetism
Among recording methods, magnetic tape devices that use audio cassette tapes, which are inexpensive and easy to operate, have been adopted and widely used.

However, this inexpensive magnetic tape device has the following drawbacks.

When playing back a magnetic tape, the amplitude level of the playback signal may become loose due to non-uniformity (disturbance) in the running of the tape, which is a problem with the mechanism of this device, or uneven coating of the magnetic material, which is a problem with the recording medium tape. The vibration level varies in a variety of ways, from small fluctuations to rapid fluctuations, and the vibration level is often one-third or less of the steady value. In particular, in magnetic tape devices that use cassette tapes, the non-uniformity of tape running is greater than in magnetic tape devices that use oven-reel tapes (the occurrence of amplitude level fluctuations is also noticeable).

Conventionally, the following circuits have been devised and implemented for waveform shaping of digital signals.
'1) A method of using the DC level as a reference level for voltage inversion. (Referred to as DC level reference method) FIG. 1A is a block diagram showing a circuit configuration of the DC level reference method.

2A is a waveform diagram showing signal waveforms of the circuit of FIG. 1A.

In this DC level reference method, a digital input signal is input to a comparator 3 by an amplifier 1 as shown in FIG.
The input signal is amplified to an appropriate level, DC cut is performed by a capacitor 2, and a new reference potential VRE is applied to this DC cut digital signal by a reference potential supply device 4.
F is added to one input terminal of comparator 3,
The reference potential Vnr:r from the reference potential supplier 4 is applied to the other input terminal of the comparator 3.

This method is the simplest and has good followability even for large amplitude fluctuations of the input signal, but as shown in the waveform diagram A in FIG.
In 2, since the reference potential V- does not match the peak-to-peak center of the digital input signal V0, the pulse widths of the original signal S and the output signal MA0 are different, and waveform shaping that is faithful to the original signal is not performed. It has major drawbacks.

2) Method using AGC and clamp circuit (referred to as AGC clamp method) FIG. 1B is a block diagram showing the circuit configuration of the AGC clamp method.

FIG. 2B is a waveform diagram showing signal waveforms of the circuit of FIG. 1B.

This AGC clamp method amplifies the digital input signal to a constant amplitude VA suitable for the input of the comparator 3 using the AGC amplifier 11, as shown in FIG. 1B, and clamps the minimum level of this amplified input signal. The circuit 12 and the clamp potential supply device 5 clamp the input signal to the clamp potential yct, and the clamped input signal is sent to the comparator 3.
In addition to one input terminal of the comparator 3, a reference potential Vct-1-VA/2 is applied to the other input terminal of the comparator 3.

This method always sets the reference potential at the center of the peak to peak of the digital input signal and inverts the voltage, ensuring that the AGC amplifier circuit operates in an ideal manner (response time is O). In this case, waveform shaping that is most faithful to the original signal is performed. However, in reality, most AGC amplifier circuits perform peak detection on the peak-to-peak value of the input signal and apply negative feedback to the multiplier for this detected signal, so the AGC response has a constant p time. There will always be delays. To reduce this time delay, the response speed is 11
If you try to speed it up, the AGC circuit will oscillate and become useless for practical use, forcing you to slow down the AGC response speed.

However, this method cannot follow sudden amplitude fluctuations of the input signal, and a part of the input signal cannot be detected as shown by bl in B in Fig. 2, and the AGC fails as shown in b2. This has a major drawback in that the pulse width of the original signal S and the output signal MA0 changes due to the response delay, and waveform shaping that is faithful to the original signal cannot be performed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal waveform shaping circuit that can shape the waveform of a digital signal having rapid amplitude fluctuations and DC level fluctuations faithfully to the original signal.

The digital signal waveform shaping circuit of the present invention includes a series circuit including an amplifier circuit for amplifying a digital input signal and a clamp circuit for clamping the input signal, which are connected so as to amplify and clamp the same digital input signal, respectively. Connect to one input terminal of a differential comparator that is the output of one series circuit, connect a peak rectifier circuit to the output of the other series circuit, and connect the output of this peak rectifier circuit to the other input terminal of the comparator. The gain of the amplifier circuit in the latter series circuit is set to 1/2 of the gain of the amplifier circuit in the former series circuit, and the clamp potential of the clamp circuit in the latter series circuit is set to be lower than the clamp potential of the clamp circuit in the former series circuit when there is no signal. The feature is that the potential is set to a value that is higher than the noise level of the noise level.

Further, in the digital signal waveform shaping circuit of the present invention, a hysteresis circuit is provided at the input terminal of the comparator to which the former series circuit is connected in the above-described circuit, an initial value setting means is provided at the output terminal of this comparator, and both are clamped. The clamp potentials of the circuits may be set to be equal.

According to the present invention, the voltage inversion reference level of one input terminal is always set to the center between the peaks of the other digital input signal in the signal waveform of the input terminals of the differential comparator without using an AGC amplifier circuit. Therefore, even if a digital input signal having rapid amplitude fluctuations, DCt movement, and pulses with different duties is input, waveform shaping that is faithful to the original signal can be performed. In addition, since the DC level of the input terminal of this comparator is shifted by a potential greater than the noise level when there is no signal, malfunctions due to noise will not occur when there is no signal, and since a clamp circuit is used, the commercial frequency (50 or 6
Waveform shaping is performed satisfactorily even when induced hum (such as 0 Hz power supply) is present at the top.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3A is a block diagram showing a first embodiment of the present invention.

FIG. 2C is a waveform diagram of the first embodiment shown in FIG. 3A.

As shown in FIG. 3A, the circuit configuration of this embodiment is such that in the circuit from the input terminal 31 to the non-inverting and inverting input terminals of the differential voltage comparator 3, In the circuit connected to the inverting input terminal, the digital input signal vi is input to the input terminal 31.
An amplifier circuit 21 having a gain for amplifying the signal to a suitable amplitude level is connected to the non-inverting input of the comparator 3.

Then, the input signal vi passes through this amplifier circuit 21 to reach an amplitude level suitable for the input amplitude level of the comparator 3. Then, an amplifier circuit is used to clamp the minimum level of this signal to an appropriate ramp potential. The output of 21 is connected to the input of a clamp circuit 12, and this clamp circuit 12 is further connected to a clamp potential supplier 5. Since the output potential of this clamp potential supply device 5 is VCL and the diode of this clamp circuit 12 is arranged in the forward direction toward the signal source, when the input signal amplified by the amplifier circuit 21 passes through this clamp circuit, The non-inverting input terminal is connected to apply the input signal clamped to this signal amplifier potential Vct to the non-inverting input terminal of the cone comparator 3. In other words, digital human power signal vi&l
At the non-inverting input terminal of the comparator 3, the signal is amplified to an amplitude level suitable for the non-inverting input, and the minimum level of this amplified signal is clamped to the clamp potential VCL. On the other hand, in the circuit connected to the inverting input terminal of the comparator 3, an amplifier circuit 22 for amplifying the digital human input signal vi is connected to the input terminal 31, similarly to the above circuit. The gain of this amplifier circuit 22 is
Since the gain is set to 1/2 of the gain of 1, the input signal vi
When the signal passes through this amplifier circuit 22, the amplitude level of the output signal of the amplifier circuit 22 becomes 1/2 that of the output signal of the amplifier circuit 21. In order to clamp the minimum level of this signal to the clamp potential of the clamp potential supplier 6 similarly to the above circuit, the output of the amplifier circuit 22 is connected to the input of the clamp circuit 130, and furthermore, the output of the amplifier circuit 22 is connected to the input of the clamp circuit 130.
is connected to the clamp potential supply device 6. The clamp potential of this clamp potential supply device 6 is at the upper eye level.
Vct, and a potential ΔV greater than the noise level when there is no signal.
Since the potential is set to the sum of CL, the amplifier circuit 2
The minimum level of the input signal amplified to 1/2 of the output signal of the amplifier circuit 21 in step 2 passes through the clamp circuit 13 and is clamped to the clamp potential Vch+ΔVct. Next, the output of the clamp circuit 13 and the input of the peak rectifier circuit 23 are connected to perform peak rectification of the input signal which is amplified by the amplifier circuit 22 and clamped by the clamp circuit 13 and the clamp potential supply device 5. Since this peak rectifier circuit 23 rectifies the input signal and smooths it at the maximum level of the input signal, the output signal of the clamp circuit 13 reaches the maximum signal level when it passes through this peak rectifier circuit 23. This becomes a DC signal. This DC signal is not completely C due to the presence of the time constant of peak rectification, but has pulsations.

Therefore, in order to suppress the pulsating current as low as possible at a period less than the maximum value of the digital input signal period, and to follow the vibration fluctuation period of a relatively large digital input signal without any problem, the time constant τ of the peak rectifier circuit 23 is set.
is set to a value that satisfies (MAX of the digital input signal period) (τ minus (MIN of the digital input signal amplitude fluctuation period).The digital output signal of a normal magnetic tape device is period's M.A.X.
) << (MIN of digital signal amplitude fluctuation), so there is no problem in practice. Next, the output of the peak rectifier circuit 23 is connected to the inverting input terminal of the comparator 3 in order to apply the DC signal output from the peak rectifier circuit 23 to the inverting input terminal of the comparator 3. In other words, the signal at the inverting input terminal of the comparator 3 is the clamp potential VCL+ΔVCL provided by the clamp circuit 13 and the clamp potential supply device 6, and the input signal amplified by the amplifier 22 to 1/2 of the amplitude of the output signal of the amplification signal 21. This results in a DC signal having a pulsating current with the value added to the amplitude value. The input signal of the non-inverting input terminal of the comparator 3 mentioned above is set as V◆, and the input signal of the inverting input terminal of this comparator 3 is set as V-, as shown in FIG. 2C. In other words, the input signal V- of the inverting input terminal has amplitude fluctuations, DC fluctuations,
Even if input signals having pulses with different duties are input, the input signal V+ is always located at the center from peak to peak of the input signal V+ of the non-inverting input terminal. Therefore, the output terminal of comparator 3 is always connected to C in Fig. 2.
As shown in FIG. 2, it is possible to obtain an output signal vO whose waveform has been shaped faithfully to the original signal S. In addition, each input terminal of the converter 3 is shifted by a potential greater than the noise level when there is no signal at the DC level, so that malfunctions due to noise do not occur when there is no signal. Note that this noise level is very small compared to the signal, so even if the clamp potential of the clamp potential supply device 6 is raised by a potential ΔVCL greater than the noise level, the comparator 3
It has almost no effect on the value of the DC signal ■- at the inverting input terminal, and the ■- signal at the inverting input terminal changes from the peak to the peak of the input signal ■+ at the non-inverting input terminal of the target converter 3. Located in the center of

FIG. 3B is a block diagram showing a second embodiment of the invention.

This example is amplified compared to the first example described above.
, the clamp circuit 12, the clamp potential supply device 5, and the amplification 22, the clamp circuit 13, and the clamp potential supply device 6, respectively. Same as the first embodiment shown. Note that in this embodiment, the input signal is first clamped and then amplified, so the amplification wA9121 and wA9122
must be a DC amplifier.
(FIG. 3C is a block diagram showing a third embodiment of the present invention.) This embodiment has a means for preventing malfunctions due to noise when there is no signal, compared to the first embodiment shown in FIG. The effects obtained are the same except for

Therefore, only the differences in the means for preventing malfunctions due to noise will be explained in detail.

The clamp potential supply device 6 of the clamp circuit 13 is set to a potential Vct that is equal to the clamp potential of the clamp potential supply device 5. A hysteresis circuit 25 is provided at the non-inverting input terminal (G) of the comparator 3, so that the comparator 3 has hysteresis characteristics. The output terminal of the comparator 3 is connected to one side of a switch 26, which is an initial value setting means for the non-inverting input terminal.
The other end of this switch 26 is connected to ground.

First, in the first embodiment shown in FIG. 1, in order to prevent malfunctions due to noise when there is no signal, the clamp potential of the clamp potential supplier 6 is set to be lower than the clamp potential of the clamp potential supplier 5, which is lower than the noise level when there is no signal. The DC voltage of each input terminal of comparator 3 is increased only outside the large potential.
I explained that this is done by shifting the levels.

In this embodiment as well, this is done by shifting the DC level of each input terminal of the comparator 3.
Clamp circuit 12 provided before the comparator 3.
By providing a hysteresis circuit 25 in the comparator 3 and giving the comparator 3 a hysteresis characteristic, the DC level of each input terminal of the comparator 3 can be shifted, regardless of the clamp potential supply device 5.13 and the clamp potential supply device 5.6. There is.

Hereinafter, the operation of the comparator 3 including the hysteresis circuit 25 and the switch 26 which is an initial value setting means for setting the initial value of the non-inverting input terminal of the comparator 3 will be explained in detail.

First, when not operating the circuit of this embodiment, switch 26
is turned ON, and the output terminal of comparator 3 is forced to ground potential. The output terminal of the comparator 3 is connected to the non-inverting input terminal through the hysteresis circuit 25, and the output signal of the comparator 3 is positively fed back to the non-inverting input terminal via the hysteresis circuit 25. Therefore, if the output terminal is at ground potential, the non-inverting input terminal will move in the direction of ground potential. Comparing the non-inverting input terminal and the inverting input terminal at the DC level, if the switch 26 is turned on, the non-inverting input terminal will move toward the ground potential. The input terminal is lower than the inverting input terminal. Then, when there is no signal, the switch 26 is turned OFF to operate the circuit of this embodiment.

At this time, switch 2.6 is set to 0. Even if disconnected from the ground potential by F There is no change in the fact that positive feedback is applied through the system. In other words, at the DC level, the non-inverting DC level becomes low level, and this low level is fed back to the non-inverting input terminal, so the non-inverting input terminal is always lower than the inverting input terminal (therefore, the comparator 3
This means that the initial value of the non-inverting input terminal of is set. Next, an input signal is supplied to the circuit of this embodiment.

At this time, in order for the output terminal of the comparator 3 to reach a high DC level, the condition is that the non-inverting input terminal becomes higher than the inverting input terminal at the DC level. Therefore, unless the signal has an amplitude greater than the DC level difference between the non-inverting input terminal and the inverting input terminal described above, the DC level at the output terminal will not be high. In other words, this DC level difference serves as a means of preventing malfunction due to noise. Furthermore, this hysteresis characteristic has the effect of preventing erroneous ζ operation due to high frequency noise even when high frequency noise is added to the input signal.

3Dli is a block diagram showing a fourth embodiment of the invention, FIG. 3E is a block diagram showing a fifth embodiment of the invention, and FIG. 3F is a block diagram showing a sixth embodiment of the invention.

The connections to the non-inverting input side and the connections to the inverting input side of the embodiments shown in FIGS. 3A, 3B, and 3C are swapped to form FIGS. 3D and 3E.

Next, circuit examples of the first, second, and third embodiments described in detail will be explained, but those skilled in the art will be able to understand the circuit examples shown in FIGS. Since it can be easily carried out, only the calculation formula for reference will be described.

Note that the numbers of the blocks shown in FIGS. 3A, 3B, and 3C correspond to the numbers of the blocks surrounded by dotted lines in FIGS. 4'A, 4B, and 4C. Note that the block 24 is a level cyst circuit.

FIG. 4A is a circuit diagram of the example circuit of the first embodiment shown in FIG. 3A.

The calculation formula used as a reference for this circuit diagram is shown below.

Note that RB = 2RA, and VBE indicates the pace and emitter voltage of the transistor. Further, transistors of the same type and characteristics are used. (The same applies to the following circuit examples.) FIG. 4B is a circuit diagram of the circuit example of the second embodiment shown in FIG. 3B.

The calculation formula used as a reference for this circuit diagram is shown below.

Amplifier 1 gain "" RA = A FIG. 4C is a circuit diagram of the circuit example of the third embodiment shown in FIG. 3C.

The calculation formula used as a reference for this circuit diagram is shown below.

Hysteresis voltage "" ERH+RJ Note that RH>>RK.

As explained in detail above, the digital signal waveform shaping circuit of the present invention does not use an AGC amplifier and performs waveform shaping by always inverting the voltage using the center from peak to peak of the digital signal as a reference, so that sudden amplitude fluctuations can be avoided. Even if a digital input signal having pulses with different DC fluctuations and duties is input, it is possible to obtain a digital signal that is faithful to the original signal.
Since the level is added to the differential comparator, malfunctions due to noise do not occur when there is no signal, and since a clamp circuit is used, the waveform is well shaped even if the input signal is crested by induced hum. Great value.

[Brief explanation of the drawing]

Fig. 1A is a block diagram showing the DC level reference method, Fig. 1B is a block diagram showing the AGC clamp method,
'Second
The figure shows the DC level reference method in Figure 1A and the AGC in Figure 1B.
A waveform diagram showing the clamp method and waveforms of the first embodiment of the present invention, Fig. 3A is a block diagram showing the first practical example of the present invention, and Fig. 3B shows the second embodiment of the present invention. Block diagram: FIG. 3C is a block diagram showing a third embodiment of the present invention; FIG. 3D is a block diagram showing a fourth embodiment of the present invention; FIG. 3E is a block diagram showing a fifth embodiment of the present invention. 3F is a block diagram showing a sixth embodiment of the present invention; FIG. 4A is a circuit diagram showing a circuit example of the first embodiment shown in FIG. 3A; FIG. 4B is a circuit diagram showing a circuit example of the first embodiment shown in FIG. 3B. FIG. 4C is a circuit diagram showing a circuit example of the second embodiment shown in FIG. 3C. FIG. 4C is a circuit diagram showing a circuit example of the third embodiment shown in FIG. 3C. ,

Claims (1)

[Claims] - (1) A first amplification circuit that amplifies a digital input signal with a predetermined power and input to one input terminal of a differential voltage comparator having inverting and non-inverting input terminals. A series circuit with a first clamp circuit that fixes the signal at a constant potential is connected, a peak rectifier circuit is connected to the other input terminal of the comparator, and the digital input signal is connected to the input terminal of the peak rectifier circuit. 1/2 of the gain of the amplifier circuit of 1
A series circuit is connected between a second amplification circuit which amplifies the gain using a gain, and a second clamp circuit which fixes the input signal to a potential higher than the above-mentioned potential by a potential greater than the noise level when there is no signal. Features a digital signal waveform shaping circuit. (2) A first amplifier that amplifies the digital input signal with a predetermined gain and a first amplifier that fixes the input signal to a constant potential are connected to one input terminal of a differential voltage comparator that has inverting and non-inverting input terminals. A series circuit with a clamp circuit is connected, a peak rectifier circuit is connected to the input terminal of the humpator 9, and the digital input signal is input to the input of the peak rectifier circuit at a gain of 1/1 of the gain of the first amplifier circuit. In the digital signal waveform shaping circuit formed by connecting a series circuit of a second amplifier circuit that amplifies with a second gain and a second clamp circuit that fixes the input signal to a potential equal to the potential, the differential voltage comparator A digital signal waveform shaping circuit characterized in that a hysteresis circuit is provided at the comparator, and initial value setting means is provided at the output terminal of the comparator.