JPS5883894U - jack circuit - Google Patents
jack circuitInfo
- Publication number
- JPS5883894U JPS5883894U JP17861881U JP17861881U JPS5883894U JP S5883894 U JPS5883894 U JP S5883894U JP 17861881 U JP17861881 U JP 17861881U JP 17861881 U JP17861881 U JP 17861881U JP S5883894 U JPS5883894 U JP S5883894U
- Authority
- JP
- Japan
- Prior art keywords
- microphone
- switch
- jack
- channel
- microphone jack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Details Of Connecting Devices For Male And Female Coupling (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の２端子付マイクプラグの一例を示す側面
図、第２図は同じく３端子付マイクプラグを２端子付マ
イクジヤツクに接続した場合の従来例を示したジャック
回路図、第３図は同じく２端子付マイクプラグを３端子
付マイクジヤツクに接続した場合の従来例を示したジャ
ック回路、第４図乃至第１２図は本考案のジャック回路
の一実施例を示すものでこのうち第４図はマイクプラグ
を接続していない場合、第５図は第２マイクジヤツク内
に２端子付マイクプラグを接続した場合、第６図は逆に
第１マイクジヤツクに２端子付マイクプラグを接続した
場合、第７図は第１マイクジヤツクに３端子マイクプラ
グを接続した場合、第８図は逆に第２マイクジヤツクに
３端子付マイクプラグを接続した場合、第９図は第１マ
イクジヤツクに３端子付マイクプラグを接続した場合、
第１０図は第１、第２マイクジヤツクに３端子付マイク
プラグを接続した場合、第１１図は第１マイクジヤツク
に３端子マイクプラグを、また第２マイクジヤツクに２
端子マイクプラグをそれぞた接続した場合、第１２図は
第１マイクジヤツクに２端子マイクプラグを第２マイク
ジヤツクに３端子 −マイクプラグを接続した場合を示
し、第１３図は本考案の他の実施例を示す。
１・・・・・・第１マイクジヤツク、２・・・・・・第
２マイクジヤツク、３・・・・・・第１の出力端、５・
・・・・・第２の出力端、４． ７． １１−−−−−
−コンタクトスイッチ、６・・・・・・第１スイツチ、
９・曲・第２スイツチ、１２・・・・・・第３スイツチ
、８Ａ、１０．１４・・・・・・アース。Figure 1 is a side view showing an example of a conventional microphone plug with two terminals, Figure 2 is a jack circuit diagram showing a conventional example when a microphone plug with three terminals is connected to a microphone jack with two terminals, and Figure 3 is a side view showing an example of a conventional microphone plug with two terminals. 4 shows a conventional jack circuit in which a two-terminal microphone plug is connected to a three-terminal microphone jack, and FIGS. 4 to 12 show an embodiment of the jack circuit of the present invention. The figure shows the case when no microphone plug is connected, Fig. 5 shows the case when the 2-terminal microphone plug is connected to the second microphone jack, and Fig. 6 shows the case when the 2-terminal microphone plug is connected to the first microphone jack. Figure 7 shows a case where a 3-terminal microphone plug is connected to the first microphone jack, Figure 8 shows a case where a 3-terminal microphone plug is connected to the second microphone jack, and Figure 9 shows a case where a 3-terminal microphone plug is connected to the first microphone jack. If you connect
Figure 10 shows a case where a three-terminal microphone plug is connected to the first and second microphone jacks, and Figure 11 shows a case where a three-terminal microphone plug is connected to the first microphone jack and a two-terminal microphone plug is connected to the second microphone jack.
When the terminal microphone plugs are respectively connected, FIG. 12 shows the case where the two-terminal microphone plug is connected to the first microphone jack and the three-terminal microphone plug is connected to the second microphone jack, and FIG. 13 shows another implementation of the present invention. Give an example. 1...First microphone jack, 2...Second microphone jack, 3...First output end, 5...
...Second output end, 4. 7. 11------
- Contact switch, 6... first switch,
9. Song, 2nd switch, 12...3rd switch, 8A, 10.14... Earth.
Claims (1)
ル用の第２マイクジヤツクとで形成され、このうち前記
第１マイクジヤツクには前記第１チヤネルの出力端に通
ずるコンタクトスイッチ及び第２チヤネルの出力側に接
続された第１スイツチを設け、他面第２マイクジヤツク
には第２チヤネルの出力端に通ずるコンタクトスイッチ
及び内部にマイクプラグが差し込まれた時のみオフとな
る第３スイツチを設け、−２端子付マイクジヤツクを前
記第２ジヤツクに差し込んだ時にその出力は前記第１マ
イクジヤツクの第１スイツチを介して第１、第２両チャ
ネルに分配されることによりモノフォニック録音が可能
となり、また３端子付マイクプラグを前記第２マイクジ
ヤツクに差し込んだ時に前記第１スイツチがオフとなっ
て第１、第２両チャネルの通電は断たれ且つアースに通
ずる第１、第２スイツチがオフとなるとともに前記第２
マイクジヤツク内に第３スイツチを介してその出力が前
記第１、第２チヤネルに分配されることによりステレオ
録音が可能となり、さらに２端子付マイクプラグを前記
第１、第２マイクジヤツク内に差し込んだ時に前記第１
、第２チャネル間を接続する第１スイツチと第２スイツ
チ並びに前記第゛ ３スイツチとがそれぞれオフとな
ってステレオ録音が可能となることを特徴としたジャッ
ク回路。It is formed of a first microphone jack for the first channel and a second microphone jack for the second channel, and the first microphone jack has a contact switch connected to the output end of the first channel and a contact switch connected to the output side of the second channel. On the other side, the second microphone jack is provided with a contact switch that communicates with the output end of the second channel, and a third switch that turns off only when the microphone plug is inserted inside, and a microphone jack with a -2 terminal. When plugged into the second jack, the output is distributed to both the first and second channels via the first switch of the first microphone jack, making monophonic recording possible. When the microphone is inserted into the second microphone jack, the first switch is turned off, cutting off power to both the first and second channels, and the first and second switches connected to ground are turned off, and the second switch is turned off.
Stereo recording is possible by distributing the output to the first and second channels through a third switch inside the microphone jack, and when a two-terminal microphone plug is inserted into the first and second microphone jacks. Said first
, a jack circuit characterized in that a first switch, a second switch, and the third switch connecting the second channels are respectively turned off to enable stereo recording.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17861881U JPS5883894U (en) | 1981-12-02 | 1981-12-02 | jack circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17861881U JPS5883894U (en) | 1981-12-02 | 1981-12-02 | jack circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5883894U true JPS5883894U (en) | 1983-06-07 |
| JPH0125036Y2 JPH0125036Y2 (en) | 1989-07-27 |
Family
ID=29973581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17861881U Granted JPS5883894U (en) | 1981-12-02 | 1981-12-02 | jack circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5883894U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014049856A (en) * | 2012-08-30 | 2014-03-17 | Teac Corp | Amplifier unit and portable electronic apparatus having the same |
-
1981
- 1981-12-02 JP JP17861881U patent/JPS5883894U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014049856A (en) * | 2012-08-30 | 2014-03-17 | Teac Corp | Amplifier unit and portable electronic apparatus having the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0125036Y2 (en) | 1989-07-27 |
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