JPS5883494A - Channel device for time division exchange - Google Patents

Abstract

PURPOSE:To easily increase the channel capacity, by selecting the content from a plurality of time switches and outputting the content to one highway, in writing or reading out the information on a PCM highway to a plurality of time switches. CONSTITUTION:A time switch T1 is provided in a channel device MODULE0 and a selection circuits SEL is provided between time switch memories T0, T1 and a multiplex separation circuit DMUX. The selection circuit SEL consists of two AND gates connected with the output of the time switch memories T0, T1 and an OR gate to which the outputs of the AND gates are given, and an output of a control CTLM is given to the other input terminal of the AND gates respectively. Thus, the mutual connection between the highways of the MODULE0 and an MODULE1 can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time division switch. 411K, which relates to small capacity communication path equipment.

Generally, when using a time-division switch for about 1,000 to 2,000 subscribers, the communication path is constructed of, for example, 16 multiplexed POM highways of 50 channels and one stage of time switch memory having 512 time slots.

Additionally, the peripheral control section is optimized and designed to match the maximum capacity of the system.

Therefore, here is a new system maximum capacity of, for example, 30
If a call path for 00 subscribers is required, a device with a large @Kl' circuit configuration including a peripheral control section is required. (1) Are the same time switches used? -8-T configuration (2) Increased multiplicity and 71 of 1024 time slots
It may take the form of steps.

However, in case (1) above, control for path setting becomes complicated as the number of stages increases, and in case (2) above, technical separation occurs as memory speed increases. There are drawbacks such as.

The present invention improves this point by writing the information of the PO's highway to multiple time switches, reading it out, selecting the contents from the multiple time switches, and outputting it to one highway. It is an object of the present invention to provide a communication path device that can easily increase the communication path capacity.

Kinei Meisha, a multiplex circuit to which a first subhighway 9A is connected, a first time switch memory for time-division exchange of the subhighway, and a relationship between this time switch memory and a second subhighway. a connected demultiplexing circuit;
and a control means for controlling the time switch memory, and in a communication path device of a time division exchange that connects the first and second subhighway 9A in a time-division manner, the outputs of the multiplex circuits of other communication path devices are connected. and a means for selecting the outputs of the first and second time switch memories 9 and applying them to the demultiplexing circuit. Let's call it mold.

This will be explained in detail based on Figure INK.

! FIG. 1 is a block diagram of a main part of a communication path device consisting of:

In Figure 1, P Oll[aoo~P OM, . . The contents of this highway are on the counter CM'ro
El is sequentially written into the time switch memory To using the address as the address generation source. On the other hand, information such as path closing and opening of the communication path is set in the control memory QTXaMK from the central processing unit CP-U. The contents of control memory cTLM are counter ON! , and uses this as an address to randomly read the contents of the time switch memory Ta.
The contents of the highway of 2 time slots are demultiplexed by circuit D.
30 channels of PC'M0° via MUX. ~PaMo
Sent to ts.

However, such conventional systems have the disadvantage of requiring significant circuit changes, including the peripheral control section, in order to increase the communication path capacity.

FIG. 2 is a block diagram of the O11 section according to an embodiment of the present invention. -1 Compared to the conventional configuration shown in Figure 1, a time switch T is provided in one channel device MODUL, Kp time switch mode 1% T, and a demultiplexing circuit D.
There is a 4I mold where the selection 1 path 81L is provided to MUX and 01111. This selection path 8EL has the outputs of the time switch memo 971, respectively, from the 92 AND gates and the OR gate from which the output of this AND gate is derived. input terminal K
a Control Me (No. 07; 6 MO outputs are led respectively.

Other points are the same as the conventional device shown in FIG. 1, and the same symbols indicate those of Oka.

Further, in FIG. 2, the communication path device MODULm has the same structure as the communication path device Mo1) ULIIH, and the details thereof are omitted.

With such a configuration O device, company 1 communication path device MOI) tlI
! At 11°, the multi-circuit UXO output is connected to the communication path [
1) Sent to ULll. , similarly the channel device M O
D U L l, - The information is from the communication path device MODUr.
,! , [is sent and stored in the time switch memory T1, which is a feature of the present invention. Time switch memory! . Or, the output of 〒1 is selected by the selection circuit BWL and the communication path device M
ODUII. The sub-highway PGM0° of the 5o channel is passed through the demultiplexing circuit DMUX within. ~" is sent to Ml 115. The gate control of this selection circuit 81L is performed by the gate signals Go and G, which are generated at the time of viewing, based on the information in the control memory OTL. As explained above, according to the present invention, it is possible to connect the highway and the communication path device MODULIt) to each other.As explained above, according to the present invention, just by adding the communication path device, major circuits such as the control section can be changed. It is possible to increase the communication channel capacity without having to perform

Brief explanation of tavi FIG. 1 is a block diagram of a main part of a conventional device, and FIG. 2 is a block diagram of a main part of an embodiment of the present invention.

P.O.Mo. . ~PC! M,,%...Subhigh 9ei, Te. , T1...Time switch memory, O? LM
-・Control memory, MtfX...Multiple circuit, D
MtT! ...Demultiplexing circuit.

Figure 1

Claims (1)

[Claims] (1) A multiplex circuit to which the first subhighway is connected;
A first time switch memory for time-division exchange of the subhighway, a multiplexing/demultiplexing circuit connected between the time switch memory and the second subhighway, and a control means for controlling the time switch memory. Equipped with
In a channel device of a time-division exchange that connects the first and second subhire KII#, a 20th time switch memory to which the output of the multiplex circuit of the other channel device is connected; A channel device for a time division exchange, comprising means for selecting outputs of first and second time switch mails and applying the selected outputs to the multiplexing/demultiplexing circuit.