JPS588238U - logic circuit - Google Patents
logic circuitInfo
- Publication number
- JPS588238U JPS588238U JP10258881U JP10258881U JPS588238U JP S588238 U JPS588238 U JP S588238U JP 10258881 U JP10258881 U JP 10258881U JP 10258881 U JP10258881 U JP 10258881U JP S588238 U JPS588238 U JP S588238U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- logic circuit
- load
- constant current
- switching means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の論理回路を示す。
主な図番の説明1,2・・・入力端子、3・・・第1の
トランジスタ、4・・・第2のトランジスタ、5・・・
第1の負荷、6・・・第2の負荷、7・・・第1の定電
流源、8・・・第2の定電流源、9・・・直流電源端子
、10・・・直流電源端子、11・・・スイッチング手
段、12・・・スイッチングダイオード、13・・・出
力端子。The drawing shows the logic circuit of the present invention. Explanation of main figure numbers 1, 2... Input terminal, 3... First transistor, 4... Second transistor, 5...
First load, 6... Second load, 7... First constant current source, 8... Second constant current source, 9... DC power supply terminal, 10... DC power supply Terminal, 11... Switching means, 12... Switching diode, 13... Output terminal.
Claims (1)
1のトランジスタ及び第1の定電流源を接続すると共に
電源とアース間に第2の負荷、第2のトランジスタ及び
第2の定電流源を接続し、前記第1のトランジスタ及び
第2のトランジスタの両コレクタ間にダイオードを挿入
し、前記第1のトランジスタのベースに基準電圧を、エ
ミッタに第1の入力信号f□を印加し、第2のトランジ
スタ□のベースに第2の入力信号f2を印加して、前記
第2のトランジスタのコレクタ側より出力信号f3を、
前記スイッチング手段に応じて、fa”fz、SZはf
□十Gになすことを特徴とした論理回路。A switching means, a first load, a first transistor, and a first constant current source are connected between the power source and ground, and a second load, a second transistor, and a second constant current source are connected between the power source and ground. A diode is inserted between the collectors of the first transistor and the second transistor, a reference voltage is applied to the base of the first transistor, a first input signal f□ is applied to the emitter, and A second input signal f2 is applied to the base of the second transistor □, and an output signal f3 is output from the collector side of the second transistor.
Depending on the switching means, fa”fz, SZ is f
□A logic circuit characterized by what it does in 10Gs.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10258881U JPS588238U (en) | 1981-07-09 | 1981-07-09 | logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10258881U JPS588238U (en) | 1981-07-09 | 1981-07-09 | logic circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS588238U true JPS588238U (en) | 1983-01-19 |
JPS6348991Y2 JPS6348991Y2 (en) | 1988-12-16 |
Family
ID=29897230
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10258881U Granted JPS588238U (en) | 1981-07-09 | 1981-07-09 | logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS588238U (en) |
-
1981
- 1981-07-09 JP JP10258881U patent/JPS588238U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6348991Y2 (en) | 1988-12-16 |
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