JPS5882353A - Common memory control system - Google Patents

Abstract

PURPOSE:To simplify the constitution of a central controller and to improve ability in access to a main memory, by connecting an adapter having an interface to an interface of the same constitution between the central controller and main memory device, and connecting both device via the said adapter. CONSTITUTION:Plural common memory adapters 13-1-13-n consisting of means of varying the timing between central controllers 11-1-11-n and a common memory device 14, and data address transmitting and receiving means of transmitting and receiving data and addresses are provided and also connected respectively through the same interfaces as interfaces between the controllers 11-1-11-n and main memory devices 12-1-12-n. A memory device 14 is accessed at the same timing with access from the controllers 11-1-11-n to the devices 12-1-12-n through the intervention of the memory adapters 13-1-13-n.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a common memory control scheme (F) in a multiprocessor system with a common memory device.

In traditional multiprocessor systems.

As shown in Figure 1, the central control unit (hereinafter referred to as CC)
1-1 to 1-n are main memory devices (hereinafter referred to as MM) 2-
1 to 2-n and a common memory device (hereinafter referred to as CM) 3 through two connection points, respectively.

Moreover, the CM 3 and the CCs 1-1 to 1-n are connected by a bus 4. According to this type of connection, the CC itself becomes complicated, access to the CM is limited by the transfer capacity of the bus, and there is also the inconvenience that a failure in the CC affects the CM and other CCs. there were.

An object of the present invention is to provide a CM adapter (with the same interface as the interface between CC and MM).
(hereinafter referred to as CMADP).

By connecting the CC and the CMi through all of the CM adapters, it is possible to simplify the configuration of the CC, improve the ability to access the CM, and provide a common memory control method that does not cause failures of the CC to other devices.

According to the present invention, the device is configured of a plurality of central control units, a plurality of main memory devices respectively connected to these central control units, and a common memory device commonly accessed by the plurality of central control units. In multiprocessor systems.

A plurality of common memory adapters are provided, each comprising a means for converting timing between the central control unit and the common memory device, and a data address transmitting/receiving means for exchanging all data and addresses, and these common memory adapters are connected to the plurality of central control units. are connected to the interface between the central control unit and the main memory device corresponding to each one of them via the same interface as the interface, and the common memory adapter is used as an intermediary to connect the corresponding central control unit to the main memory device. A common memory control method is obtained, characterized in that all of the common memory devices are accessed at the same timing as when the common memory device is accessed.

Next, two common memory control systems according to the present invention will be explained with reference to all the drawings.

FIG. 2 is a block diagram showing an embodiment of a multiprocessor system to which the present invention is applied. In this figure, 11-1 to 11-n are CC212-1 to 1
2-n is MM, 13-1 to 13-n are CMADP,
And 14 indicates CMi. CMADP 13-1~13
-n is connected as an extension of the CC and MM interface. When considering the case of accessing CMi from CC, the same control signal as that used when accessing MM from CC is sent out, and only the address for CM is sent out. That is,
From the CC's point of view, it appears that the capacity has simply increased in accessing the MM3. In this case, the control signal for data access from the CC is received by the CMADP,
After timing conversion is performed here, a control signal is output to the CM.

The response signal from the CM is received by the CMADP, the timing is converted, and the signal is sent back to the CC.

Figure 3 shows CMADP13-1 to 13- in Figure 2.
This figure shows a schematic configuration example of n. In addition.

In this figure, 16-1 is shown as a representative CMADP. Reference numeral 13-1a denotes a timing conversion circuit, in which a control signal from a CC is converted into a signal for CM, and a response signal from a CM is converted into a signal for CC. Also,
13-1111 data/address transmitting/receiving circuit 9
Usually includes a latch circuit, and a timing conversion circuit 13-1
By the control signal from a.

Data/address transmission/reception to CC and CM is controlled. Also, since there is usually a distance of several tens of meters between CM and CC,
A cable driver layer bar is provided at the interface between the timing conversion circuit 13-1a and the CM in the data/address transmission/reception circuit 13-1b. I cut it.

CC and CM, l! A control circuit for separating the : is also included in the timing conversion circuit 13-1a and the data/address transmitting/receiving circuit 13-1b.

According to the above embodiment, since the CC and CM are not directly connected, even if one of the multiple CCs fails, other CCs can use the CMi normally by disconnecting it at the corresponding CMADP. . or.

If the CMADP is made into a module, the addition of CCs for processing capacity amplifiers can be handled simply by adding modules, and the expansion work becomes easy.

Needless to say, the same applies to cases where

In the case of duplication, there is an advantage that the CM operating mode and the CC operating mode can be independently controlled by CMADP.

As is clear from the above explanation, according to the present invention, C
For the interface between C and MM.

By connecting a CM adapter with the same interface as this, and connecting the CC and CM via this CM adapter, the configuration of the CC is simplified, and the occurrence of a failure can affect other CCs. Since there is no impact on the system, the reliability of the processing function VC is improved, and the flexibility of the system can be improved in that it is easy to add CCs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a conventional multiprosenozazostem, and FIG. 2 is a block diagram showing the configuration of an embodiment according to the present invention, No. 6Nd. 3 is a block diagram showing a schematic configuration example of the common memory adapter in FIG. 2. FIG. In the figure, 11-1 to 11-n are medium heat control devices (
CC), 12-1 to 12-n are main memory devices (MM
). 13-1~l3-nu common memory adapter (CMADP
). 13-1a is a timing conversion circuit, 131bij data/address transmission/reception circuit, and 14 is a common memory device (C
M).

Claims (1)

[Scope of Claims] 1. A plurality of central control units and a plurality of main memory devices respectively connected to these central control units. In a multiprocessor system comprising a common memory device commonly accessed by the plurality of central control units, means for converting timing between the central control unit and the common memory device, and a data address for exchanging all data and addresses. a plurality of common memory adapters each comprising a transmitting/receiving means are provided, and these common memory adapters are connected to an interface between a central control unit corresponding to each of the plurality of central control units and the main memory device via the same interface as the interface; A common memory characterized in that the common memory device is accessed at the same timing as the access to the main memory device from the corresponding central control unit using each of the common memory adapters as an intermediary. control method.