JPS5882027U - Tuner device - Google Patents

Tuner device

Info

Publication number
JPS5882027U
JPS5882027U JP17519781U JP17519781U JPS5882027U JP S5882027 U JPS5882027 U JP S5882027U JP 17519781 U JP17519781 U JP 17519781U JP 17519781 U JP17519781 U JP 17519781U JP S5882027 U JPS5882027 U JP S5882027U
Authority
JP
Japan
Prior art keywords
tuner device
tuner
shield plate
circuit
high frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17519781U
Other languages
Japanese (ja)
Inventor
浩 福島
揚 船田
Original Assignee
ミツミ電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ミツミ電機株式会社 filed Critical ミツミ電機株式会社
Priority to JP17519781U priority Critical patent/JPS5882027U/en
Publication of JPS5882027U publication Critical patent/JPS5882027U/en
Pending legal-status Critical Current

Links

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はチューナ装置の平面図。第２図は第１図のＡ−
Ａ線断面図。第３図は高周波増幅回路とシールド板の関
係を示す回路図。第４図はシールド板と高周波増幅用Ｆ
ＥＴとの関係を示す要部平面図。第５図イ９口は高周波
増幅回路のアースパターンの実施例を示す要部断面図。 第６図は利得減衰特性を示すグラフである。 １・・・・・・チューナ装置、２・・・・・・チューナ
筐体、３・・・・・・回路基板、４・・・・・・アンテ
ナ段、５〜Ｒ下段、６・・・・・・発振段、−７・・・
・・・混合段、８・・・・・・信号入力部、９・・・・
・・２重シールド板、９ａ・・・・・・絶縁層、９ｂ。 ｂ′・・・・・・導電層、１０．１１・・・・・・シー
ルド板、１２・・・・・・アースパターン。FIG. 1 is a plan view of the tuner device. Figure 2 is A- in Figure 1.
A-line sectional view. FIG. 3 is a circuit diagram showing the relationship between the high frequency amplifier circuit and the shield plate. Figure 4 shows the shield plate and F for high frequency amplification.
FIG. 3 is a plan view of main parts showing the relationship with ET. FIG. 5A9 is a sectional view of a main part showing an embodiment of a ground pattern of a high frequency amplification circuit. FIG. 6 is a graph showing gain attenuation characteristics. DESCRIPTION OF SYMBOLS 1...Tuner device, 2...Tuner housing, 3...Circuit board, 4...Antenna stage, 5-R lower stage, 6... ...Oscillation stage, -7...
...Mixing stage, 8...Signal input section, 9...
...Double shield plate, 9a...Insulating layer, 9b. b'... Conductive layer, 10.11... Shield plate, 12... Earth pattern.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 回路基板に設けた高周波増幅回路のアースパターン上で
、チューナ装置の回路及びチューナ筐体内の接続端子部
を入力側と出力側とに導電層間に絶縁層を有する２重シ
ールド板で分割したことを特徴とするチューナ装置。On the ground pattern of the high frequency amplification circuit provided on the circuit board, the circuit of the tuner device and the connection terminal section inside the tuner housing are divided into the input side and the output side by a double shield plate having an insulating layer between the conductive layers. Features a tuner device.
JP17519781U 1981-11-25 1981-11-25 Tuner device Pending JPS5882027U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17519781U JPS5882027U (en) 1981-11-25 1981-11-25 Tuner device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17519781U JPS5882027U (en) 1981-11-25 1981-11-25 Tuner device

Publications (1)

Publication Number Publication Date
JPS5882027U true JPS5882027U (en) 1983-06-03

Family

ID=29967473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17519781U Pending JPS5882027U (en) 1981-11-25 1981-11-25 Tuner device

Country Status (1)

Country Link
JP (1) JPS5882027U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61212089A (en) * 1985-03-18 1986-09-20 日本シイエムケイ株式会社 Printed wiring board and manufacture thereof
JPH0677685A (en) * 1992-08-27 1994-03-18 Nec Corp Shielding structure for integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039054U (en) * 1973-08-03 1975-04-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039054U (en) * 1973-08-03 1975-04-22

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61212089A (en) * 1985-03-18 1986-09-20 日本シイエムケイ株式会社 Printed wiring board and manufacture thereof
JPH0677685A (en) * 1992-08-27 1994-03-18 Nec Corp Shielding structure for integrated circuit

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