JPS588201B2 - Is there a way to get the job done? - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic train control system that quickly activates a brake system in the event of system failure.

The automatic train control system uses the highest setting signal for the running section sent from the wayside signal system while the train is running, and the actual train speed signal obtained from the speed generator or pulse transmitter attached to the train's wheel axles. Check the speed by comparing with
When the actual speed signal becomes larger than the set signal, the train is automatically braked and decelerated.

Although such a device is simple in function, it is essential for train operation because it is an important safety device.

Therefore, if a failure occurs in the device that performs such speed checks, for example, if a non-braking command is issued as a result of the speed check even though the train speed is higher than the set signal, the train may collide with the preceding train. There is a danger that it may lead to a major accident.

For this reason, there has been a need for a device that can quickly detect a failure in the circuit that performs the speed check, issue a safe brake command, and also be able to quickly operate the circuit to the safe side even if the detection device itself fails.

SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic train control system that can quickly operate to the safe side not only when a speed checking circuit fails but also when the failure detection device itself fails.

The configuration of an embodiment according to the present invention will be explained below with reference to FIG.

A train actual speed detector, for example a pulse transmitter PG, is attached to the wheel axle of the train and emits a pulse signal according to the speed of the train, and its output pulse is applied to the first gate circuit 1.

The setting signal generator ATC instructs the maximum speed in the section in which the train is running, and sends it out as a pulse signal, for example, and applies it to the second gate circuit 2.

The timing pulse generator 3 emits timing pulses at a predetermined period T, which are time-divided into the speed check period and the failure diagnosis period. For example, when an odd-numbered timing pulse is applied to the first and second gate circuits 1 and 2, The first and second gate circuits 1 and 2 determine that it is the speed check period, and pass the command signals from the pulse generator PG and the setting signal generator ATC to the first and second counters 4 respectively. , 5.

Further, even-numbered timing pulses emitted from the timing pulse generator 3 are applied to the first and second gate circuits 1,
2, the first and second gate circuits 1 and 2 determine that it is the failure diagnosis period, pass only the signal from the mode generator 6, and supply it to the first and second counters 4 and 5 separately. , the first and second counters 4 and 5 receive pulses from the timing pulse generator 3, and each time a pulse arrives, they reset the previous count value and at the same time, the first and second counters 4 and 5 receive pulses from the first and second gate circuits 1 and 2. counts the pulses and outputs an analog signal according to the count value.

The comparator γ compares the count values of the first counter 4 and the 20th counter 5 and outputs the pulse generator P during the speed checking period.
When a timing pulse is applied when the output signal from G is smaller than the output signal from the setting signal generator ATC, "1" is output as a result.

Here, rlJ is a voltage, and [0] means no voltage.

Further, the comparator 7 compares the signals from the mode generator 6 sent via the first and second gate circuits 1 and 2 and the first and second counters 4 and 5 during the failure diagnosis period. Set in advance so that the result is "0".

That is, during the failure diagnosis period, the mode generator 6 is set in advance so that the count value of the tenth counter 4 is greater than the count value of the second counter 5.

The output of this comparator 7 is applied to the brake command relay RY1 via a first control circuit whose overall designation is 10A.

This first control circuit is configured as follows.

That is, the output of the comparator 7 is connected to a first transistor (an nPn type is used in this embodiment) via a resistor r1.

) is supplied to the base terminal of T1.

Furthermore, the base terminal of the first transistor T1 is connected to the resistor r2.
It is connected to the negative control power supply bus (hereinafter referred to as negative bus) N via.

The collector terminal of the first transistor T1 is connected to a positive control power supply bus (hereinafter referred to as positive bus 5) P via a resistor r3.

The emitter terminal of the first transistor T1 is connected to the base terminal of the second transistor T2.

The collector terminal of this second transistor T2 is connected to the resistor r
4 and the primary winding of the transformer TR to the positive bus P through a series circuit.

The emitter terminal of the second transistor T2 is connected to the negative bus line N.

A series circuit of a surge voltage absorbing resistor r5 and a capacitor C is connected between the primary winding terminals of the transformer TR.

Full wave rectifier circuit R between the secondary winding terminals of voltage generator TR.

and connect a capacitor C2 and a brake command relay RY1 between its output terminals.

When this brake command relay RYI is deenergized, the brake device is driven by its contacts (not shown) and the brakes are applied to the train.The logic circuit 8 receives the output signals from the comparator 7 and the mode generator 6, and performs a fault diagnosis. If it is a predetermined "0" signal, it will output "1" during the speed check period and "1" during the fault diagnosis period.
0".

The output of this logic circuit 8 is transmitted to the first control circuit 101 described above.
The failure detection relay RY2 is energized via the second control circuit 102 having the same configuration.

When this failure detection relay RY2 is deenergized, the contact point (not shown) drives a failure reporting device (not shown), such as an alarm device such as a bell, or a display device such as a lamp.

Next, the operation of an embodiment of the present invention having the above-mentioned configuration will be explained with reference to FIGS. 2 to 5.

First, normal operation will be explained with reference to FIG.

When the first pulse P1 is emitted from the timing pulse generator 3 at time t1, the first and second gate circuits 1 and 2 determine that it is the speed check period, and the pulse generator PG
and setting signal generator ATC (hereinafter simply referred to as ATC)
The output pulses from the first and second counters 4,
Supply to 5.

The count values of the first and second counters 4 and 50 are converted into analog signals and compared by a comparator 7.

At time t2, the timing pulse generator 3 emits a second pulse P2, which, when applied to the comparator I, outputs the result of the comparison between the contents of the first counter 4 and the contents of the second counter 5. .

Here, if the count value of the first counter 4, that is, the actual speed of the train, is smaller than the count value of the second counter 5, that is, the command value from the ATC, the comparator 7 outputs "1" as the speed check result.
Output and retain this.

Also, the timing pulse P2 issued at time t2
When applied to the mode generator 6, the first and second gate circuits 1 and 2, and the first and second counters 4 and 5, it is determined that the first and second gate circuits 1 and 2 are in the failure diagnosis period. Only the mode signal from the mode generator 6 is passed through, and the first and second counters 4 and 5 are set during the speed checking period. The count value at is erased and the output pulses from the mode generator 6 are counted again.

Here, the mode generator 6 is at the beginning of the failure diagnosis period. 1st in
The pulse passing through the gate circuit 1 is passed through the second gate circuit 2.
Since the timing generator 6 emits the third pulse P3 at time t3 and is applied to the comparator 7, the comparator 7 outputs "0" as a result of fault diagnosis. Output and retain this.

Further, at time t3, when the third pulse P3 is applied to the mode generator 6, the first and second gate circuits 1 and 2, and the first and second counters 4 and 5, the mode signal generator 6
When the mode signal from φ is cut off, the first and second counters 4 and 5 start at the beginning of the failure diagnosis period. The count value at is erased, and counting of command pulses sent from the pulse generator PG and ATC via the first and second gate circuits 1 and 2 is started again.

Thereafter, if the device is normal, the output of the comparator 7 repeats "1", "0", "1", "0", . . . by the above-described operation.

For this reason, the first and second transistors T1 and T2 repeatedly turn on and off, and each time an induced voltage is generated in the secondary winding of the transformer TR, and the brake command relay RYt continues to be energized, so the brake device (not shown) do not drive.

On the other hand, the logic circuit 8 outputs "1" if the comparator 7 is "0" as initially set as a result of the fault diagnosis, and also sets the mode so that the output of the comparator 7 becomes "0" as a result of the fault diagnosis. Even though the mode signal of the generator 6 is set, the comparator 7 is
The configuration is such that when a signal "1" is issued, the output becomes "0".

That is, the logic circuit 8 outputs the i. , B, only when the output ■ is "0" and the mode generator 6 is not emitting a mode signal and a "1" signal is added to the output ■ of the mode generator 6, the output O is set to "1". Emit a signal.

Then, when entering the failure diagnosis period at time 12.14,
When the mode generator 6 issues the mode signal, the logic circuit 8 is given a "0" signal at the output (2), and as a result of the speed check, the output (1) of the comparator 7 is given a "1" signal, so the output O becomes "0".

In this way, if the device is normal, the output of the logic circuit 8 is "1".
”, “0”, “1”, “0”...

Since this output is applied to the failure detection relay RY2 via the second control circuit 102 which has the same configuration as the first control circuit 101, the failure detection relay RY2 continues to be energized, and the failure detection relay RY2 continues to be energized and is connected to a failure display device (not shown) or Do not activate failure reporting devices such as alarm devices.

Next, a case where the actual speed of the train becomes thicker than the command signal from the ATC as a result of the speed check will be described with reference to FIG.

When the train is operating in the above-mentioned normal operation from time t1 to t3, it enters the speed check period Ib from time t3, and when the actual speed of the train becomes 1 greater than the command signal, the output nors from the pulse generator PG becomes the same as that from the ATC. Since the number of output pulses is larger than that of the output pulse, the count value of the first counter 4 is much smaller than the count value of the second counter 5.

Therefore, when the timing pulse P4 is applied to the comparator I at the time t4, the comparator 7 continues to output the "0" signal, which is the result of the fault diagnosis at the time t3 to t4, even after the time t4. T1 and T2 are not turned on, and no induced voltage is generated between the transformer secondary winding terminals even after the timing pulse generation period T has passed.

As a result, the brake command relay RYI is deenergized, so
A brake device (not shown) is driven to decelerate the train.

On the other hand, at time t4, the logic circuit 8 outputs the mode generator 6.
Since a ``0'' signal is given from ``1'' to ``0'', the output changes from ``1'' to ``0'' and the failure detection relay is energized.

Therefore, a failure display device or a failure alarm device (not shown) is not activated.

Furthermore, the first gate circuit 1 does not operate even though the train speed is higher than the speed command signal, or the first counter 4
The pulses from the pulse generator PG may be counted lower than the actual number due to a malfunction of the second counter 5.
When the comparator 7 outputs "1" as a result of speed check due to a cause such as counting the output pulses from the ATC lower than the actual value or an internal failure of the comparator 7, etc.
This will be explained with reference to FIG.

That is, the operation is normal until time t3, and for example, at time t3, the third timing pulse P3 enters the speed checking period Ib, and the number of output pulses from the pulse generator PG exceeds the command pulses from the ATC. Nevertheless, when the above-mentioned failure occurs, pulse P4 is emitted at time t4, and the comparator 7 is activated as if it were operating normally.
changes from "0" to "1".

Therefore, the brake command relay RYt continues to be energized and does not issue a brake command.

However, when the cause of the failure as described above remains, the failure diagnosis period enters b at time t4, and the mode signal from the mode generator 6 gives more pulses to the 20th counter 5 than to the first counter 4. Although the second
The count of the counter 5 becomes smaller than the count value of the first counter 4.

Therefore, when the timing pulse P5 is given to the comparator 7 at time t, the comparison result is the result of the speed check.
It becomes "1", which is the same as "1".

Therefore, even after the timing pulse generation period T has elapsed, no induced voltage is generated in the secondary winding of the transformer TR, and the brake command relay RYI is deenergized.

Therefore, a brake device (not shown) is driven to decelerate the train.

On the other hand, the logic circuit 8 receives "1" from the comparator 7 even after time t7.
Since the signal can be obtained, its output is “0” like period opening b.
” remains.

Therefore, the failure detection relay RY2 is deenergized, and the failure display device or failure alarm device (not shown) is activated to display the failure or issue a failure alarm, thereby making it possible to promptly report the failure.

Also, even though the train speed was lower than the command signal, the 10th
If the counter 4 counts more pulses from the pulse generator PG than it actually does, or if the second gate circuit is inoperable or if the second counter 5 counts the output pulses from the ATC less than it actually does, or if the comparison Due to internal failure of the comparator 7, the output of the comparator 7 may be "0" as a result of the speed check.
” will be explained with reference to FIG. 5.

That is, the operation is normal until time t3, and at time t3
The timing pulse generator 3 emits the timing pulse P3 and enters the speed check period Ib, and if the cause of the failure as described above occurs here, the result of the speed check at time t4 will change even though the train speed is lower than the command signal. The output of comparator 7 becomes "o".

Therefore, the output signal of the comparator 7 remains "0" even after the period T.
As a result, no induced voltage is generated in the secondary winding of transformer TR, and brake command relay RY1 is deenergized.

Therefore, the train driven by a brake device (not shown) is decelerated.

Since the present invention has the above-described configuration and operation, it is possible to provide a highly reliable automatic train control system that can quickly operate to the safe side not only when the speed check circuit fails but also when the failure detection device itself fails. can be provided.

FIG. 6 shows another embodiment of the present invention, the configuration of which will be explained below.

A reference pulse is sent out and supplied to distribution logic circuit 20 via pulse distribution counters Q1 to Qn.

The distribution logic circuit 20 generates an output signal as shown in FIG.

The speed generator TG is attached to the wheel axle of the train and emits a signal according to the speed of the train.The output signal is added to the waveform shaping circuit PS and taken out as a pulse signal, which is sent to one side of the first AND gate circuit A1. Add to input terminal.

A gate command signal G1 from the distribution logic circuit 20 is applied to the other input terminal of the first AND gate circuit A1.

The output signal of the first AND gate circuit A1 is supplied to one input terminal of the first OR gate circuit OR1.

The gate command signal G2 is supplied from the distribution logic circuit 20 to one input terminal of the second AND gate circuit A2, and the failure diagnosis mode signal CV is supplied to the other input terminal.

The output signal of the second AND gate circuit A2 is applied to the other input terminal of the first OR gate circuit OR1.

The output signal of the first OR gate circuit OR is supplied to the counter C.

Clear signals Ca and Cb are applied from the distribution logic circuit 20 to one and the other input terminals of the second OR gate circuit OR2 to clear the contents of the counter C.

Set signals Sa and Sb are applied from the distribution logic circuit 20 to one and the other input terminals of the third OR gate circuit OR3, and the set signals are applied to one of each of the third to n-th AND gate circuits A3 to An. Apply to input terminal.

A speed setting signal is applied from the diode matrix circuit D as the other input signal of the third to nth AND gate circuits A3 to An in response to the closing of the contact Ka or Kb, and the setting signal is supplied to the counter C. .

The output signal of the counter C is supplied to a control circuit 103 having the same configuration as the control circuit 101 shown in FIG. 1, and the output thereof energizes the brake command relay RY3.

When this relay RY3 is de-energized, the brake device is driven by its contacts (not shown) and the brakes are applied to the train.

Next, the operation will be explained with reference to FIG.

At time t1, when a clear pulse Ca is applied from the distribution logic circuit 20 to the counters C1 to cn+t via the second OR circuit OR2, their contents become zero.

Next, at time t2, the third OR circuit O is output from the distribution logic circuit 20.
A set signal S1 is supplied to the third to n-th AND circuits A3 to An via R3.

Then, the maximum setting signal SV for the section in which the train runs is set in the counter C via the diode matrix circuit D in response to the closing of the contact Ka or Kb.

At the same time, the gate command signal G1 is sent from the distribution logic circuit 20 to the first AND gate circuit AN during the speed check period T.
D, the first AND gate circuit A1 satisfies the AND condition and passes the speed signal V from the output of the speed generator TG through the waveform shaping circuit PS.

Therefore, the speed signal V is supplied to the counter C via the first OR circuit OR1 and added to the setting signal Sv.

In the speed check period T, when the number of speed pulses from the speed generator PG is V, when SV+V becomes 2n pulses or more, the counters C1 to Cn change from 1 to O, and Cn+1 changes from 0 to 1.

That is, when the counters C1 to Cn overflow, an overspeed occurs, but under normal conditions when SV+V is 2n or less, the counter Cn+1 does not overflow and does not output.

At time t3, when a clear pulse cb is applied from the distribution logic circuit 20 to the other input terminal of the second OR circuit OR2, the contents of the counters C1 to Cn are cleared to O, and SV is reset again at the next set pulse sb (time 14). is set to

At time t, the distribution logic circuit 20 supplies the fault diagnosis signal G2 to one input terminal of the second AND gate circuit A2, and also supplies the fault diagnosis mode signal Cv to the other input terminal of the second AND gate circuit A2. In addition, this signal CV is
It is supplied to the counter C through the OR circuit OR1 and added to the set value SV.

At this time, it is necessary to make sure that the count value of sv+cv within the failure diagnosis period is 2n pulses.

Therefore, as a result of the fault diagnosis, the counters C1 to Cn overflow and Cn+t changes from 0 to 1.

During normal operation, the above operation is repeated and the output of the counter C changes from "0" to "1" to "0" to "1", so the brake command relay continues to be energized and the brake device (not shown) is not driven.

Next, in the event of a failure in which the speed signal V and mode signal Cv are no longer counted, the counter C becomes inoperable, and even though the mode signal is added so that the counter C overflows during the failure diagnosis period, the counter C continues to count. do not.

Therefore, since there is no overflow and the fault diagnosis result of counter C is "0", the result of the previous speed check is "0".
” signal continues.

Therefore, the failure detection relay RYs is deenergized, and a brake device (not shown) is driven to decelerate the train.

Note that the second AND gate circuit A2 and the first OR gate circuit OR. Even in the case where the mode signal Cv is not allowed to pass due to a failure in the counter C, the counter C does not overflow as described above and its output continues to be "0", so that the brake device can be driven.

Conversely, in the event of a failure in which the counter C counts the speed signal V and mode signal Cv more than they actually are, the counter C naturally overflows during the speed check period, and its output becomes "1".

Therefore, the previous failure diagnosis result of "1" is continued, and the brake command relay RY3 is deenergized, so that the brake device is driven.

Also, due to a failure in the reference oscillator f, counting circuits Q1 to Qn, distribution logic circuit 20, second and third OR gate circuits OR2 and OR3 to n-th AND gate circuits A3 to A, a set signal or clear signal is sent to the counter C. If no pulse is applied, the output state of counter C is the previous "1" or "0".
” continues, the brake command relay RYs is deenergized and the brake device is driven.

As described above, in other embodiments of the present invention, it is possible to provide an automatic train control system that can quickly operate to the safe side even in the event of a failure in the circuit performing the speed check, as well as a failure in the failure detection device itself.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIGS. 2 to 5 are waveform diagrams for explaining the operation of FIG. 1, and FIG. 6 is a block diagram showing the configuration of another embodiment of the present invention. A block diagram showing the configuration, and FIG. 7 is a waveform diagram for explaining the operation of FIG. 6. PG...Pulse transmitter, ATC...Setting signal generator, 1, 2...Gate circuit, meter...
...Timing pulse generation circuit, 4,5...
・Counter, 6...Mode generator, 7...
...Comparator, 8...Logic circuit, 101, 102
... Control circuit, RYI ... Brake command relay, RY2 ... Failure detection relay, TG.
...Speed generator, f...Reference transmitter, Q
1 to Qn...counting circuit, 20...distribution logic circuit, A1 to An...and gate circuit,
OR1~OR3...OR gate circuit, D...
...Diode matrix circuit, C-゜"゜゜゛counter, 103...Control circuit, RY3"""brake finger 1 no

Claims (1)

[Claims] 1. In a system that automatically applies brakes to a train when the actual speed signal of the train becomes larger than the set signal, the set signal and the actual speed signal are alternately time-divided into the speed check period and the failure diagnosis period, and the set signal and the actual speed signal are applied during the speed check period. is applied to perform a speed check, a predetermined failure diagnosis mode signal is applied during a failure diagnosis period to perform a failure diagnosis, and during normal operation, a comparison device alternately emits different comparison signals between the speed check result and the failure diagnosis result; An automatic train control device comprising a brake command device that is constantly energized by different signals of the comparison device and drives a brake device when one of the different signals continues for a predetermined period.