JPS5881659U

JPS5881659U - electronic register

Info

Publication number: JPS5881659U
Application number: JP17696681U
Authority: JP
Inventors: 泰章渡辺
Original assignee: カシオ計算機株式会社
Priority date: 1981-11-27
Filing date: 1981-11-27
Publication date: 1983-06-02

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示す概略システム構成図
、第２図は同実施例のＣＰＵの詳細な回路構成図、第３
図は同実施例の動作を示すフローチャートである。１・・・・・−ＣＰＵ、　４・・・・・・時計回路、５
・・・・・・入力部、５ｂ・・・・・・時刻キー、５Ｃ
・・・・・・モードスイッチ、６・・・・・・表示部、
１０・・・・・・制御回路、１１・・・・・・ＲＡＭ。１２・・・・・・演算部。FIG. 1 is a schematic system configuration diagram showing an embodiment of this invention, FIG. 2 is a detailed circuit diagram of the CPU of the same embodiment, and FIG.
The figure is a flowchart showing the operation of the same embodiment. 1...-CPU, 4...Clock circuit, 5
...Input section, 5b...Time key, 5C
...Mode switch, 6...Display section,
10...Control circuit, 11...RAM. 12... Arithmetic unit.

Claims

[Scope of utility model registration request]

A clock means for measuring the current time; a display means for displaying the amount data or the current time data; a storage means for storing time display data indicating that the current time data is displayed on the display means; When time display data is stored in this storage means, input of key data by key operation is disabled by manual key means, and mode designation means for designating operation modes such as registration, return, inspection, and payment. and when the mode is changed by the mode specifying means, erasing the data during time display in the storage means and making it possible to input key data from the key manual means. Features an electronic register.