JPS5880904A - Fm demodulating circuit - Google Patents
Fm demodulating circuitInfo
- Publication number
- JPS5880904A JPS5880904A JP17952481A JP17952481A JPS5880904A JP S5880904 A JPS5880904 A JP S5880904A JP 17952481 A JP17952481 A JP 17952481A JP 17952481 A JP17952481 A JP 17952481A JP S5880904 A JPS5880904 A JP S5880904A
- Authority
- JP
- Japan
- Prior art keywords
- pll
- modulation
- electric field
- degree
- control voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
- H03D3/24—Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
- H03D3/241—Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits the oscillator being part of a phase locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Noise Elimination (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は位相同期ループ(以下PLLと略称)を含む
FM復調回路の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of an FM demodulation circuit including a phase locked loop (hereinafter abbreviated as PLL).
FM受信方式はAM受信方式に比べ一般にSIN比が大
きくとれるが、復調器へ゛の信号入力が雑音レベルと同
等修こなると急、に雑音が増加する、いわゆるスレッシ
ョルドの現象がある。しかも入力FM信号がこのスレッ
ショルドレベル以下の場合に1−)ムM8ai省虻のS
/Nより悪くなる。PLL復調は上述のスレッショルド
レベルを改善するために帯域圧縮を行いながら復調をす
るよい方法であり、FM受信機に多く採用されている。Although the FM reception system generally has a larger SIN ratio than the AM reception system, there is a so-called threshold phenomenon in which the noise suddenly increases when the signal input to the demodulator reaches the same level as the noise level. Moreover, when the input FM signal is below this threshold level, 1-) M8ai saving S
/Worse than N. PLL demodulation is a good method of performing demodulation while compressing the band in order to improve the above-mentioned threshold level, and is often used in FM receivers.
第1図は従来のPLLを利用したFM@調回調合路す概
略ブロック図である。入方端子叫とは周波数変゛換段(
図示せず)よりのFM中間周波信号が与えられ、このF
M中間周波信号は中間周波帯域フィルタ(2)および中
間周波増幅器(3)により帯域制限および増幅をされた
後、位相比較器(4)、電圧制御発振器(以下■coと
記す)(5)およびループフィルタ(7)からなるPL
L復調回路(6)に入力される。FIG. 1 is a schematic block diagram of an FM@tuning circuit using a conventional PLL. The input terminal noise is the frequency conversion stage (
An FM intermediate frequency signal from (not shown) is given, and this F
After the M intermediate frequency signal is band-limited and amplified by an intermediate frequency band filter (2) and an intermediate frequency amplifier (3), it is passed through a phase comparator (4), a voltage controlled oscillator (hereinafter referred to as ■co) (5), and PL consisting of loop filter (7)
The signal is input to the L demodulation circuit (6).
位相比較器(4)に入力されたFM中間周波信号はv
CO(51よりの出力と比較゛さ“れ、その位相差に対
応した出方がループフィルタ(7)に与えられる。ルー
フフィルタ(7)のローパス出方は■cO(5HC:I
:/トロール電圧として与えられ、前記位相差を0と
するようにV CO(51の発振周波数を変える。即ち
、このループ番こよりFM中間周波信号とV COi5
+出力が位相比較器(4)で位相比較され、両者が等し
くなるようなりC電圧が抵抗(8)、コンデンサ(9)
よりなるデエンファシス回路を通り、出力端子(IGに
現われる。したがって、入力端子(1)から入力された
FM中間周波信号の周波数偏移に対応した検波出力を出
力端子体から取りだすことが出来る。The FM intermediate frequency signal input to the phase comparator (4) is v
It is compared with the output from CO (51), and the output corresponding to the phase difference is given to the loop filter (7). The low-pass output of the roof filter (7) is cO (5HC:I
:/The oscillation frequency of V COi51 is changed so that the phase difference becomes 0. In other words, from this loop number, the FM intermediate frequency signal and V COi5
The + output is phase-compared by the phase comparator (4), and when they become equal, the C voltage is applied to the resistor (8) and capacitor (9).
It passes through a de-emphasis circuit consisting of, and appears at the output terminal (IG). Therefore, a detection output corresponding to the frequency shift of the FM intermediate frequency signal input from the input terminal (1) can be taken out from the output terminal body.
ところ、でこのPLL復調により弱電界におけるSハ比
の悪化を改善する場合、PLLの同調レンジを狭帯域化
し、帯域圧縮する程大きい効果が得られる。しかしなが
ら帯域圧縮を進めていくと、スレッショルド現象が起こ
る弱電界付近においては、ステレオ時のサブキャリア3
8 KHm等に対する帯域の考慮は、通常モノラル受信
に切換えるため必要ないが、変調度即ち周波数偏移が大
きくなった場合同調レンジの上限および下限でインパル
で規定するところのSハ比で大きい改善効果が得られる
のに対し、変調度が大□きくなると前記゛インパルスノ
イズのため歪が大きくなり、実用上問題となってくる。However, in order to improve the deterioration of the S-ratio in a weak electric field by PLL demodulation, the greater the effect can be obtained as the tuning range of the PLL is made narrower and the band is compressed. However, as band compression progresses, subcarrier 3 in stereo mode will decrease in the vicinity of a weak electric field where a threshold phenomenon occurs.
8 Bandwidth consideration for KHm etc. is not necessary since switching to monaural reception is normally done, but if the degree of modulation, that is, the frequency deviation becomes large, there will be a significant improvement in the S-ratio defined by impulse at the upper and lower limits of the tuning range. However, when the degree of modulation becomes large, distortion increases due to the impulse noise, which becomes a practical problem.
そこでこの発明はPLL復調における充分な帯域圧縮に
よるスレッショルド改善効果を得ながら、変調度が大き
くなった場合のインパルスノイズ発生をなくすようにし
たFM復調回路を提供することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to provide an FM demodulation circuit that eliminates the generation of impulse noise when the degree of modulation increases while obtaining the effect of improving the threshold through sufficient band compression in PLL demodulation.
第2゛図はこの発明の一実施例を示す概略ブロック図で
ある。FIG. 2 is a schematic block diagram showing one embodiment of the present invention.
この実施例の構成は以下に述べる点を除き第1図の回路
と同様であるので相当する部分には同一の参照番号を付
して、その説明を省略する。The configuration of this embodiment is similar to the circuit shown in FIG. 1 except for the points described below, so corresponding parts are given the same reference numerals and their explanation will be omitted.
いま弱電界においてPLLによる帯域圧縮の結果、イン
パルスノイズを発生させるような大きい変調がかかった
時、復調出力端子αeより結合容量at+を介して取り
出され、る復調出力は増加し、ダイオードα9および抵
抗a急、コンデンサα4により整流、平滑化され、その
復調出力のレベル即ち変調度に対応したDC電圧も増加
し、インバータαGで反転されてループフィルタ(7)
に与えられる制御電圧は減少し、同期範囲を広げる。即
ち図中の(至)はPLL復調回路(6)の出力からFM
信号における搬送波の変調度に対応した制御電圧を発生
し、該制御電圧を上記PLL復調回路(6)中のループ
フィルタ(7)に与えて弱電界に#ける同期範囲を上記
変調度により制御する変調度検出回路として機能する。Now, as a result of band compression by PLL in a weak electric field, when a large modulation that generates impulse noise is applied, the demodulated output taken out from the demodulated output terminal αe via the coupling capacitor at+ increases, and the output from the diode α9 and the resistor increases. a Suddenly, the DC voltage corresponding to the level of the demodulated output, that is, the degree of modulation, which is rectified and smoothed by the capacitor α4, also increases, and is inverted by the inverter αG and sent to the loop filter (7).
The control voltage applied to is decreased to widen the synchronization range. In other words, (to) in the figure is the FM signal from the output of the PLL demodulation circuit (6).
A control voltage corresponding to the degree of modulation of the carrier wave in the signal is generated, and the control voltage is applied to the loop filter (7) in the PLL demodulation circuit (6) to control the synchronization range in the weak electric field according to the degree of modulation. Functions as a modulation degree detection circuit.
第4図は第2$Jの回路におけるループフィルタ(7)
の−回路例を示すもので、ラグリード型のローパスフィ
ルターである。Figure 4 shows the loop filter (7) in the 2nd $J circuit.
This is a circuit example of a lag-lead type low-pass filter.
位相比較器(4)の出力がフィルタ入力端子αatこ接
続され、フィルタ出力端子(財)の信号はデエンファシ
ス回路へ復調出力として、又■COに制御電圧として与
えられる。抵抗αl(社)、コンデンサ■およびトラン
ジスタ(至)のコレクタ、エミッタ間インピーダンスに
よりPLLの同期範囲が決定される。The output of the phase comparator (4) is connected to the filter input terminal αat, and the signal at the filter output terminal is given to the de-emphasis circuit as a demodulated output and also to CO as a control voltage. The synchronization range of the PLL is determined by the impedance between the collector and emitter of the resistor αl, the capacitor 2, and the transistor.
第2図において変調度が大きくなった結果減少するとこ
ろのインバータ(II小出力このループフィルタ(7)
の制御電圧として端子(ハ)に与えられ、電流制限抵抗
(2)を介し前記トランジスタ(2)のベースに印加さ
れ、コレクタ、エミッタ間インピーダンスを増加させる
。従って弱電界に詔いて平均的な変調度の場合狭帯域で
あった同期範囲は、変調度が大き−くなると、この回路
の動作により、ループフィルタ(7)のRCによる時定
数がかえられて同期範囲は広がり、インパルスノイズに
よる歪の発生を抑える。In Fig. 2, the inverter (II small output of this loop filter (7) decreases as the modulation degree increases)
The control voltage is applied to the terminal (c) through the current limiting resistor (2) to the base of the transistor (2), increasing the impedance between the collector and emitter. Therefore, the synchronization range, which is narrow band in the case of a weak electric field and an average modulation degree, is changed by the operation of this circuit as the RC time constant of the loop filter (7) changes as the modulation degree increases. The synchronization range is expanded and distortion caused by impulse noise is suppressed.
なおPLL復―復路回路−プフィルタとしては、上記の
″ようなラグリード型フィルタ以外にも演算増幅器を用
いたアクティブフィルタであってもよく、この場合液ア
クティブフィルタのゲインコントロール等による同期範
囲のコントロールが可能である。又コントロールの時定
数はPLL動作に異常を起こさないよう、抵抗a3αω
、コンデンサα尋にて最適に設定される。Note that the PLL return circuit filter may be an active filter using an operational amplifier in addition to the above-mentioned lag-lead type filter, and in this case, the synchronization range can be controlled by gain control of the liquid active filter, etc. Possible.Also, the time constant of the control is set by resistor a3αω so as not to cause abnormality in PLL operation.
, the capacitor α is set optimally.
第3図はP L L同調レンジの入力電界レベルに対す
る変化を示す特性図であり、縦軸は入力電界レベルを、
横軸はPLL同調レンジを示す。Figure 3 is a characteristic diagram showing changes in the PLL tuning range with respect to the input electric field level, and the vertical axis represents the input electric field level.
The horizontal axis shows the PLL tuning range.
従来のPLL復調によると、電界レベルの低下にともな
い総合特性上中間周波帯域フィルタの帯域特性にしたが
って同期範囲も低下してくる。これに対し本発明装置で
は、帯域圧縮効果が最適になるよう回路定数を設定した
場合の、ある弱電界入力レベルに詔ける同期範囲が図に
示すようにA−Nの時、無変調および低い変調度ではこ
の帯域が生かされ、S/N比の改善効果を得て、又高い
変調度ではそのレベルに応じて同期範囲をB −B/と
広げることにより、インパルスノイズによる歪の影響を
な、くすることができる。According to conventional PLL demodulation, as the electric field level decreases, the synchronization range also decreases in accordance with the overall characteristics and the band characteristics of the intermediate frequency band filter. On the other hand, in the device of the present invention, when the circuit constants are set so that the band compression effect is optimized, the synchronization range that can be controlled for a certain weak electric field input level is A-N as shown in the figure, when there is no modulation and low The modulation depth makes use of this band to improve the S/N ratio, and at a high modulation depth, the synchronization range is widened to B - B/ according to the level, thereby eliminating the influence of distortion caused by impulse noise. , can be reduced.
以上のよう蕃ここの発明によれば、PLL復調回路の出
力からFM信号の変調度に応じた制御電圧を発生し、こ
れをPLL復調回路のループフィルタに加えて弱電界時
におけるPtLの同期範囲を該制御電圧により制御する
ように構成することにより、弱電界に招けるSハ比の改
善を充分な帯域圧縮により行いながら、変調度が入門い
時、そのレベルに対応してPLLの同期範囲をコントロ
ールし、インパルスノイズによる歪の発生を抑えること
が可能なFM復調回路を提供することができる。As described above, according to the present invention, a control voltage according to the modulation degree of the FM signal is generated from the output of the PLL demodulation circuit, and this is added to the loop filter of the PLL demodulation circuit to control the synchronization range of PtL in a weak electric field. By configuring the PLL to be controlled by the control voltage, the S/C ratio, which is caused by a weak electric field, can be improved by sufficiently compressing the band. Therefore, it is possible to provide an FM demodulation circuit that can control distortion caused by impulse noise and suppress the occurrence of distortion due to impulse noise.
第1図は従来のFM復調回路を示す概略ブロック図、第
2図はこの発明によるFM復調回路の一実施例を示す概
略ブロック図、第3図は入力電界レベルに対する同期範
囲の変化を示す特性図、第4図は第2図のループフィル
タの一例を示す回路図である。
(4)・・・位相比較器、(5)・・・電圧制御発振器
、(6)・・・PLL復調回路、(7)・・・ループフ
ィルタ、命・・・変關度検出回゛路。
代理人 葛 野 信 −FIG. 1 is a schematic block diagram showing a conventional FM demodulation circuit, FIG. 2 is a schematic block diagram showing an embodiment of the FM demodulation circuit according to the present invention, and FIG. 3 is a characteristic showing changes in synchronization range with respect to input electric field level. FIG. 4 is a circuit diagram showing an example of the loop filter of FIG. 2. (4)...Phase comparator, (5)...Voltage controlled oscillator, (6)...PLL demodulation circuit, (7)...Loop filter, Life...Variation detection circuit . Agent Shin Kuzuno −
Claims (1)
めのPLL復調回路と、このPLL復調回路の出力から
FM信号に詔ける搬送波の変調度に対応した制御電圧を
発生し該制御電圧を上記PLL復調回路中のループフィ
ルタに与えて弱電界における同期範囲を上記変調度によ
り制御する変調度検出回路とを備えたことを特徴とする
FM復調回路。<11 A PLL demodulation circuit that has a phase-locked loop and demodulates the FM signal, generates a control voltage corresponding to the modulation degree of the carrier wave that can be transmitted to the FM signal from the output of this PLL demodulation circuit, and uses the control voltage as the PLL demodulation circuit. An FM demodulation circuit comprising: a modulation degree detection circuit that is applied to a loop filter in the demodulation circuit to control a synchronization range in a weak electric field by the modulation degree.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17952481A JPS5880904A (en) | 1981-11-06 | 1981-11-06 | Fm demodulating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17952481A JPS5880904A (en) | 1981-11-06 | 1981-11-06 | Fm demodulating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5880904A true JPS5880904A (en) | 1983-05-16 |
Family
ID=16067269
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17952481A Pending JPS5880904A (en) | 1981-11-06 | 1981-11-06 | Fm demodulating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5880904A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5416530A (en) * | 1992-12-17 | 1995-05-16 | Luly; Robert A. | Video signal noise reduction circuit for a video demodulator comprising a PLL |
-
1981
- 1981-11-06 JP JP17952481A patent/JPS5880904A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5416530A (en) * | 1992-12-17 | 1995-05-16 | Luly; Robert A. | Video signal noise reduction circuit for a video demodulator comprising a PLL |
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