JPS5877316A - Chip-enable-circuit for pll synthesizer integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a PLL synthesizer integrated circuit when the normal power supply is set on and off, by providing a Zener diode between the 2nd power supply having a voltage higher than that of the 1st power supply and a chip-enable-terminal of the PLL synthesizer integrated circuit. CONSTITUTION:Through the circuit constitution as shown in figure, a voltage VCE rises in the same gradient as a voltage VT when the voltage VT exceeds the Zener voltage VZ, and rises with a delay from a voltage VR without fail. When the power supply is turned off, the voltage VCE falls down in the same gradient as the voltage VT and since the gradient of the voltage VT is larger than that of the voltage VR, the voltage VCE falls down faster than the voltage VR without fail. Thus, the voltage VCE at a chip-enable-terminal of an integrated circuit IC2 rises slower than the power supply voltage VR of a PLL synthesizer reception integrated circuit IC1 and falls down without fail, allowing to prevent malfunction of the PLL synthesizer integrated circuit IC2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a chip enable circuit for a PLL synthesizer integrated circuit.

- In equipment that is intended to operate a PLL synthesizer integrated circuit by remote control by combining it with an integrated circuit for signal reception, 1. In order to prevent the backup current from increasing when the power is turned off, the PLL synthesizer is integrated without being
When backing up the memory using a stand-up power supply such as a battery for only m, the power supply voltage of the integrated circuit for receiving remote control drops to p, and its output also becomes zero. When the receiving integrated circuit is powered from the normal power supply, it generates a signal at the level of each output terminal in an emergency state, and when a command signal is applied, it outputs a signal at the output terminal designated by the command signal. from"
rLJ level signal is generated. On the other hand, a "■" level signal is applied to the PLL synthesizer integrated circuit branch and the chip enable terminal, causing an abnormal operation of 9 and 111K, causing the control receiving integrated circuit to Memory contents 1 in response to rLJ level signals generated from each output terminal.
For example, change the selected channel or the reception band of aFM or AM ◎Also. Chip enable lll child Kl
``When an LJ level signal is applied, the backup state of the memory is changed to 9.The oc chip enable terminal trap, which does not change the memory contents no matter what signal is applied from the remote control receiving integrated circuit, is the PLL.
When the voltage of the standard voltage that drives the synthesizer integrated circuit is applied, the contents of the memory can be arbitrarily rewritten when the power is turned on, and the contents of the memory can be rewritten as desired when the power is turned off. I am doing K so that it becomes impossible◎
However, in such a configuration, the voltage at the chip enable terminal may rise earlier or fall more uniformly than the power supply voltage of the integrated circuit for remote control reception depending on the timing when the power supply is turned on and off. PLL synthesizer integrated circuit in normal operating state 11 to 6
Since the output terminal of the integrated circuit for remote control reception becomes rLJ when
JIs changes the stored contents of the memory to a different state. 1 When the power is turned on again, the channel selected immediately before the power was turned off, that is, the last channel, cannot be reproduced, and a different preset is changed. Therefore, the purpose of this invention is to prevent malfunction of the PLL synthesizer integrated circuit when the power is turned on and off. The purpose is to provide a chip enable terminal for a PLL integrated circuit that can be used in a PLL system.
'LL synthesizer device' ft1llllEJ and 2nd
1IIjl based on 1IIK. In Figure 1, I
C-shield remote control reception integrated circuit, IC,
are PLL synthesizer integrated circuits, each of which is powered from the normal power supply B, and the PLL synthesizer integrated circuit IC2
is remote control reception N with diodes D□ and D2
Separated from integrated circuit XC1! L-order backup voltage #lE
Backup is performed from K when the abnormal power supply 10B is turned off. From each output terminal OUT to rHJ
When an input terminal INK command signal is applied via the photodetector diode PD and reception amplification/detection circuit, an rLJ level signal is generated from the output terminal determined by the command signal. On the other hand, the PLL synthesizer integrated circuit IC2 performs normal operation when a signal at the chip enable terminal CEKrHJ level is applied, and rLJ is permanently shifted from each output terminal OUT of the remote control receiving integrated circuit IC.
Since one of the transistor groups TH is turned on in response to the level signal, a signal is input from one of the segment output terminals a to g to the key input terminal □ to one of 3, and the memory is Change memory contents. Additionally, when a signal at the Teragui enable terminal CHKrLJ level is applied, the memory becomes in a backup state, and no matter what signal is given from the integrated circuit IC for remote control reception, the stored contents of the memory do not change. Chip enable terminal CE is connected to 1 normal power supply +B and a high voltage voltage 11 [(For example, a series circuit of a Zener diode ZD and a resistor R is connected to the power supply I[) + BB of the circuit to be connected to the Zener diode ZDI power supply 10BB] Do it! aL, a resistor R3 is connected to the connection point of this Zener diode ZD and resistor R.
After that, when B is on during normal power supply, the contents of the memory can be arbitrarily rewritten. 1 When B is off during normal power supply, it is impossible to rewrite the memory of Mem. I am trying to make it so that ◎ ″ & death, R is paper review, D is diode review, X□ and UX
, #f crystal resonator, C engineering ~ C4Fi conde 7? ,
Lg-L.

is the digit output terminal of the PLL synthesizer integrated circuit IC2.

JI2 shows the rising characteristics of the voltage vT "R"01 when the power is turned on. The voltage V is the voltage vT minus the Zener voltage v2 of the Zener diode ZD), so when the voltage vT exceeds the Zener voltage v2, the voltage V increases with the same slope as the voltage vT. ]! l rises at 9. This means that the voltage rises with a delay of time T from the voltage vT, so that it always rises with a delay from the voltage vT.

FIG. 2 (6) shows that the fall of the voltage vT ``!'' 01 when the power is turned off shows a characteristic. m falls at the same slope as the voltage vT, but the slope of the voltage vT is higher than the voltage v
Since it is greater than the slope of R, the voltage V. ◎ In this way, this actual III'N is connected to the chip input of the integrated circuit IC2 in the PLL circuit via the power supply element BBK Zener diode ZDt, which has a higher voltage than the normal power supply 1B. When the pull terminal CIC is connected and the power supply element B is turned on and off, the power supply voltage of the chip enable terminal CE JEvoB is the power supply voltage vR of the integrated circuit IC for remote and control reception.
Since the rise time is always later and the fall time is always earlier, malfunctions of the PLL synthesizer integrated circuit IC2 can be prevented.

As described above, the chip enable circuit of the PLL synthesizer integrated circuit of the present invention includes the PLL synthesizer integrated circuit and the PLL synthesizer II! A second power supply having a higher voltage than the power supply of 51g1 that drives the circuit, and a connection between this second power supply and the chip enable terminal of the PLL synthesizer integrated circuit KIII! Since it is equipped with a connected Zener diode, it has the effect of preventing malfunction of the PLL synthesizer integrated circuit when the power supply is turned on and off.

[Brief explanation of the drawing]

Figure 1i1 is a circuit g of a remote control PLL system to which a practical example of this invention is applied. Ill'! 18(2) is a characteristic diagram showing the rise of the voltage at each part, and zm@ is a characteristic diagram showing the fall of the voltage at each part. IC, ...PLL synthesizer integrated circuit, +B...
- Excessive voltage If (first voltage If), +BB... power supply (second power supply). E... Backup power supply, ZD... Zener diode

Claims (1)

[Claims] PLL syntax, Isa integrated circuit, and this PLL shift
- a power supply of 1N2 having a higher voltage than the first power supply for driving the SIP integrated circuit; and a Zener diode connected between the second power supply and the chip enable terminal of the PLL synthesizer integrated circuit; Chip enable circuit for integrated circuits without synthesis.