JPS5876961A - 並行非同期プロセツサのスケジュ−ル方法 - Google Patents

並行非同期プロセツサのスケジュ−ル方法

Info

Publication number
JPS5876961A
JPS5876961A JP57176497A JP17649782A JPS5876961A JP S5876961 A JPS5876961 A JP S5876961A JP 57176497 A JP57176497 A JP 57176497A JP 17649782 A JP17649782 A JP 17649782A JP S5876961 A JPS5876961 A JP S5876961A
Authority
JP
Japan
Prior art keywords
processor
processors
request
value
transmission right
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57176497A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6122337B2 (enExample
Inventor
レイモンド・アマンド・ロ−リイ
ハヴイ・レイモンド・ストロング
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5876961A publication Critical patent/JPS5876961A/ja
Publication of JPS6122337B2 publication Critical patent/JPS6122337B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP57176497A 1981-10-27 1982-10-08 並行非同期プロセツサのスケジュ−ル方法 Granted JPS5876961A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US315568 1981-10-27
US06/315,568 US4445197A (en) 1981-10-27 1981-10-27 Weak synchronization and scheduling among concurrent asynchronous processors

Publications (2)

Publication Number Publication Date
JPS5876961A true JPS5876961A (ja) 1983-05-10
JPS6122337B2 JPS6122337B2 (enExample) 1986-05-31

Family

ID=23225037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57176497A Granted JPS5876961A (ja) 1981-10-27 1982-10-08 並行非同期プロセツサのスケジュ−ル方法

Country Status (4)

Country Link
US (1) US4445197A (enExample)
EP (1) EP0078377B1 (enExample)
JP (1) JPS5876961A (enExample)
DE (1) DE3274909D1 (enExample)

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US4891749A (en) * 1983-03-28 1990-01-02 International Business Machines Corporation Multiprocessor storage serialization apparatus
US4722048A (en) * 1985-04-03 1988-01-26 Honeywell Bull Inc. Microcomputer system with independent operating systems
GB8510791D0 (en) * 1985-04-29 1985-06-05 Moller C H Automatic computer peripheral switch
US5053941A (en) * 1986-08-29 1991-10-01 Sun Microsystems, Inc. Asynchronous micro-machine/interface
US5025370A (en) * 1986-09-02 1991-06-18 Koegel Robert J Circuit for preventing lock-out of high priority requests to a system controller
US4823304A (en) * 1987-01-15 1989-04-18 International Business Machines Incorporated Method of providing synchronous message exchange in an asychronous operating environment
WO1989000734A1 (en) * 1987-07-21 1989-01-26 Stellar Computer Inc. Detecting multiple processor deadlock
US5050070A (en) * 1988-02-29 1991-09-17 Convex Computer Corporation Multi-processor computer system having self-allocating processors
US5159686A (en) * 1988-02-29 1992-10-27 Convex Computer Corporation Multi-processor computer system having process-independent communication register addressing
GB2217064A (en) * 1988-03-23 1989-10-18 Benchmark Technologies Interfacing asynchronous processors
WO1990001252A1 (en) * 1988-08-03 1990-02-22 Stellar Computer Inc. Detecting multiple processor deadlock
US4985831A (en) * 1988-10-31 1991-01-15 Evans & Sutherland Computer Corp. Multiprocessor task scheduling system
JPH04152465A (ja) * 1990-10-16 1992-05-26 Fujitsu Ltd データ処理システム及びデータ処理方法
US5317737A (en) * 1991-07-29 1994-05-31 Ncr Corporation Method and apparatus for controlling a re-entrant synchronization lock tenure in a multiprocessor system
US6029188A (en) * 1993-01-18 2000-02-22 Institute For Personalized Information Environment Information processing system for an architecture model capable of interfacing with humans and capable of being modified
JPH0887341A (ja) * 1994-09-16 1996-04-02 Fujitsu Ltd 自動縮退立ち上げ機能を有したコンピュータシステム
CN101617354A (zh) 2006-12-12 2009-12-30 埃文斯和萨瑟兰计算机公司 用于校准单个调制器投影仪中的rgb光的系统和方法
US8358317B2 (en) 2008-05-23 2013-01-22 Evans & Sutherland Computer Corporation System and method for displaying a planar image on a curved surface
US8702248B1 (en) 2008-06-11 2014-04-22 Evans & Sutherland Computer Corporation Projection method for reducing interpixel gaps on a viewing surface
US8621471B2 (en) * 2008-08-13 2013-12-31 Microsoft Corporation High accuracy timer in a multi-processor computing system without using dedicated hardware timer resources
US8077378B1 (en) 2008-11-12 2011-12-13 Evans & Sutherland Computer Corporation Calibration system and method for light modulation device
US9641826B1 (en) 2011-10-06 2017-05-02 Evans & Sutherland Computer Corporation System and method for displaying distant 3-D stereo on a dome surface

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2546202A1 (de) * 1975-10-15 1977-04-28 Siemens Ag Rechnersystem aus mehreren miteinander verbundenen und zusammenwirkenden einzelrechnern und verfahren zum betrieb des rechnersystems
US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking
US4050097A (en) * 1976-09-27 1977-09-20 Honeywell Information Systems, Inc. Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus
US4141067A (en) * 1977-06-13 1979-02-20 General Automation Multiprocessor system with cache memory
US4145739A (en) * 1977-06-20 1979-03-20 Wang Laboratories, Inc. Distributed data processing system
US4223380A (en) * 1978-04-06 1980-09-16 Ncr Corporation Distributed multiprocessor communication system
US4191997A (en) * 1978-04-10 1980-03-04 International Business Machines Corporation Circuits and methods for multiple control in data processing systems
US4384322A (en) * 1978-10-31 1983-05-17 Honeywell Information Systems Inc. Asynchronous multi-communication bus sequence
US4253144A (en) * 1978-12-21 1981-02-24 Burroughs Corporation Multi-processor communication network
US4320457A (en) * 1980-02-04 1982-03-16 General Automation, Inc. Communication bus acquisition circuit
US4374414A (en) * 1980-06-26 1983-02-15 Gte Automatic Electric Labs Inc. Arbitration controller providing for access of a common resource by a duplex plurality of central processing units

Also Published As

Publication number Publication date
DE3274909D1 (en) 1987-02-05
EP0078377B1 (en) 1986-12-30
US4445197A (en) 1984-04-24
JPS6122337B2 (enExample) 1986-05-31
EP0078377A3 (en) 1984-06-06
EP0078377A2 (en) 1983-05-11

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