JPS5873093A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent malfunction and to attain high speed, by providing a means charging a voltage of row lines, rwo decoders, column lines, column decoders, voltage sense circuits of column lines and column lines of nonselection to a value between a ground level and a sense voltage level of the voltage sense circuits. CONSTITUTION:A memory is constituted by forming an integrated circuit of MOSTR on a semiconductor substrate. A voltage sense circuit 7 detecting the voltage of a plurality of row lines 11, 12..., a row decoder 2, memory cells 311, 312, 321, 322... driven via the row decoder and the row lines, a plurality of column lines 41, 42..., a column decoder 6, and column lines, is provided and a bias circuit 20 charging the column lines 41, 42... to a voltage over the ground level and less than the sense voltage of the circuit 7, is provided. Thus, the potential of column lines of nonselection can be kept to a potential higher than the ground level at all times, malfunction can be prevented and the high speed operation can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, a memory using an insulated gate field effect transistor as 41.

In a seed semiconductor memory, the column lines of the cell array are in an electrically floating state when they are not selected.
Changes in the potential of the row lines are picked up as noise and the potential of the column lines changes, resulting in malfunctions and high-speed operation being inhibited.

FIG. 1 shows a conventional example of a semiconductor memory formed as an integrated circuit on a semiconductor substrate. Hereinafter, for convenience of explanation, it is assumed that this semiconductor memory is composed of an N-channel insulated gate field effect transistor. xi, t,...
- is row ll in the cell array, 2 is address Kugata AOI
A1 m”・Am K! IfJ row line 11°12,
A row decoder ゛8o that selects one of...
e i1s# °°°* 8Hs3He °... A memory cell such as an insulated gate field effect transistor (hereinafter abbreviated as xopg'r) is driven by a corresponding row line. A column line that intersects one row line among these memory cells'
1 * 411 If the drain is connected to #..., it stores information such as #i, and the drain is an open end (for example, stores information A).

The source ends of these memory cells are grounded.

Column 1714t a 4g e ・IGF for KFi column selection
FiTs 51 m 51 m, . . . are connected, and the gates of these IGFETs are connected to the column decoder 6. The column decoder 6 selects column selection IGFETs 51 e s, e .
Select one of them and make it conductive. The voltage sensing circuit 7 includes means for supplying current to the selected nine column lines, and if the potential of the selected column line is above the sense voltage level, the intersection of the selected row line and the selected column line is detected. Assuming that there is no Mary 7 file in , that is, 111 information is stored, @
Similarly, if the potential of the selected column line is below the sense voltage level, the voltage sense circuit 7 outputs the memory cell at the intersection of the selected row line and the selected column line. Assume that there exists ``mO'' information, that is, ``mO'' information is stored, and ``0'' information is output as data.

By the way, in the conventional semiconductor memory shown in FIG. 1, s rows m! 11*11e...) - If there is a situation where all but one selected line falls to low level (ground level) K from the low level state, for example, when this semiconductor memory chip is not operating, row 11h, 1g...
If you are using a row decoder with a circuit type in which the level of is high, and this semiconductor memory becomes operational, the row decoder 2 will input address '1 e A2 #...
・If only the 4111 rows selected according to the input information of , Am are at the high level K11t, and the other 2m-1 row lines fall from the high level to the low level, the gate electrode of the memory cell and the voltage All column lines 41 e 42 e・
The potential of ... is drawn to the negative potential side, and as a result, 2n-1 column selection IGFBTs that should originally be non-selected, other than the one selected column selection IGFBT that should be conductive, also become conductive. This has the drawback of causing malfunctions and hindering high-speed operation.

An object of the present invention is to improve the drawbacks of conventional semiconductor memories, such as spinning speed, and to provide a semiconductor memory that can stably operate at high speed.

The semiconductor memory of the present invention is configured of an integrated circuit on a semiconductor substrate, and includes a plurality of row lines, a row decoder for selecting the row line, a memory cell driven via the target row decoder and the row line, and a memory cell driven via the target row decoder and the row line. A plurality of column lines provided for receiving data from memory cells and a column lever for selecting the front array line. and a voltage sense circuit for detecting the voltage of the previous array lines, and means for always charging the voltage of unselected column lines among the previous array lines to a value between the ground level and the sense voltage level of the voltage sense circuit. It is characterized by comprising:

Hereinafter, the intention of the present invention will be explained with reference to the drawings. FIG. 2 shows a circuit of one embodiment of the semiconductor memory of the present invention. In order to make the correspondence with the conventional example of FIG. The circuit of the embodiment of the present invention shown in FIG. 2 is characterized by the column line 41 *
The bias circuit 20 is included to always charge G* to a range above the ground level and below the sense voltage level of the voltage sense circuit 7. The bias circuit 20 includes, in series, a dible V1 type IGFET 22 whose drain is connected to a constant voltage power supply VC and whose source and dart are connected to each other, and an enhancement type IGFET 23 whose drain and gate are connected to each other and whose source is grounded. II! The constant voltage generator and the drain connected to the constant voltage power supply vc are connected to the constant voltage generator VC, and the gate is connected to the IGFET 22 and IGFET2.
The first column line charging IGFgT 2tl, 21g is composed of an enhancement type IGFgT for column line charging connected to the output wiring 24 of the constant voltage generating section consisting of B.

... sources are in the corresponding column 114xe4gs
...is connected to... IGPgT22 and IGFET2B
The constant voltage generation section consisting of
If the threshold voltage of the IGFET is vT, an output of VT 0gg is supplied to the output wiring 24, and as a result, 1GFBTI for column line charging! 11, 21z e...Knob-)K
#i Normally 1fC@value voltage] K means that a voltage higher by α is applied. Therefore, the unselected column m is always charged to the potential of a, so if, for example, row lines 11*ll*... are all selected from a high level condition and all but fCt fall to low level, the conventional For example, the semiconductor memory shown in Figure 1 may malfunction or inhibit high-speed operation.
In the semiconductor memory according to the embodiment of the present invention shown in FIG.
Even if the column line is pulled to a negative potential, the column line charging IGFET21
1.21g, . . . are in a conductive state and quickly charged in the direction of positive potential, so the column line selection IGF'BT, which is originally selected and should be made conductive, is the column line selection IGF'BT.
Since T quickly becomes non-conductive, no malfunction occurs.
Moreover, high-speed operation is not obstructed. Further, the maximum value to which the potential of the selected ninth column line, for example 41, can be charged by the column line charging IGFET 211 is a volt, but since the sense voltage level of the voltage sense circuit 7 is higher than a, the voltage sense circuit 7 operates. IGFET for column line charging in the range
211 becomes non-conductive and does not affect the operation of the voltage sense circuit 7.

As explained above, according to the present invention, it is possible to always maintain the potential of unselected column lines at a potential higher than the ground level. A semiconductor memory that can prevent malfunctions and operate at high speed can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional semiconductor memory, and FIG. 2 is a circuit diagram used to explain an embodiment of the present invention. 11 e 12... Row line, 2... Row decoder, 311*311 m 321 e 322
・River...Marycel, 4114!0. . Column line, 51s5jls...column selection IGFET, 6...
・・・Column data 5-・・・・Voltage sense circuit M, 20・Old・・Bias circuit, 211 # 212
,...IGFET for column line charging. 22... Dibreen Seal fiIGFIT, 23
... Song Enhancement Men) WIGFET, 24... Surface wiring.

Claims (1)

[Scope of Claims] A semiconductor memory formed of an integrated circuit on a semiconductor substrate includes a plurality of row lines, a row decoder that selects the row lines, and a memory that is driven via the row decoders and the row lines. a memory cell, a plurality of column lines provided for receiving data from the memory cells, and a column data for selecting the column lines. a voltage boost circuit for detecting the voltage of the column line; and means for charging the voltage of an unselected column line among the column lines to a value between the normal KII ground level and the sense tfE level of the m power distribution'rx sense circuit. Semiconductor memory is classified as 4I mold by having the following.