JPS5864652A - Noninformation position detecting circuit - Google Patents

Noninformation position detecting circuit

Info

Publication number
JPS5864652A
JPS5864652A JP56164809A JP16480981A JPS5864652A JP S5864652 A JPS5864652 A JP S5864652A JP 56164809 A JP56164809 A JP 56164809A JP 16480981 A JP16480981 A JP 16480981A JP S5864652 A JPS5864652 A JP S5864652A
Authority
JP
Japan
Prior art keywords
output
circuit
counter
terminal
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56164809A
Other languages
Japanese (ja)
Other versions
JPH0368459B2 (en
Inventor
Satomi Takashige
高重 里美
Isao Fujimoto
勲 藤本
Juchu Watanabe
渡辺 重注
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56164809A priority Critical patent/JPS5864652A/en
Publication of JPS5864652A publication Critical patent/JPS5864652A/en
Publication of JPH0368459B2 publication Critical patent/JPH0368459B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/10Indexing; Addressing; Timing or synchronising; Measuring tape travel
    • G11B27/19Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
    • G11B27/22Means responsive to presence or absence of recorded information signals

Landscapes

  • Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)

Abstract

PURPOSE:To facilitate the IC-implementation of a circuit, and to obtain high detection time precision, by detecting a noninformation position of a recording medium digitally. CONSTITUTION:When an input H is applied to the terminal 3 of a noninformation position detecting circuit corresponding to a fast-forwarding or fast rewinding mode, the output of an NAND circuit 4 varies from H to L after the time when the 2nd-stage and 3rd stage output levels of a counter 2 both go to H passes from the time when the output of an oscillating circuit part 1 is applied to the counter 2. An NAND circuit 6 is applied with an output L through an inverter 5, so its output level is at L invariably. Therefore, the output level of an NAND circuit 7 varies depending upon the output of the circuit 4 and an output pulse appears at an output terminal 8 the same time later.

Description

【発明の詳細な説明】 本発明はテープレコーダで用いるテープ等の記録媒体に
時系列的に記録された少くとも2つの情報の間隙すなわ
ち無情叩位置を検出する無情報位置検出回路、特に再生
、録音、早送りあるいは早戻し時において、2つの情報
間に存在する無情報位置を検出する回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a non-information position detection circuit for detecting a gap between at least two pieces of information recorded in a time series on a recording medium such as a tape used in a tape recorder, that is, a pointless position. The present invention relates to a circuit that detects a position where no information exists between two pieces of information during recording, fast-forwarding, or fast-reversing.

たとえば、テープレコーダ等で使用するテープに2曲以
上の曲が記録(録音)されている場合、所望の曲を再生
すべくテープを早送りあるいは早戻しく巻戻し)をする
必要性がしばしば生じる。
For example, when two or more songs are recorded on a tape used in a tape recorder or the like, it is often necessary to fast forward or rewind the tape in order to play back a desired song.

このためには、曲間に存在する無録音部分を正しく検知
し、テープの走行あるいは停止を制御じなければならな
い。また、再生時と早送りならびに早戻し時のテープの
走行渉度は異るため、この違いも考慮して無録音部分の
正しい検知がなされねばならない。
To do this, it is necessary to correctly detect unrecorded sections between songs and control the running or stopping of the tape. Furthermore, since the running speed of the tape is different during playback, fast forwarding, and fast reversing, it is necessary to take this difference into account when correctly detecting unrecorded portions.

このような無録音部分の検出にあたり、従来は大きな時
定数をもつ第1の時定数回路と小さな時定数をもつ第2
の時定数回路とを切換可能な関係で設置し、テープ走行
速度の小さい再生時には時定数の大きな第1の時定数回
路を用いて無録音部分を検出し、一方、テープの走行速
度の大きい早送りもしくは巻き戻し時には時定数の小さ
い第2の時定数回路を用いて無録音部分を検出する方法
がとられていた。
Conventionally, in order to detect such unrecorded parts, a first time constant circuit with a large time constant and a second time constant circuit with a small time constant were used.
The first time constant circuit is installed in a switchable relationship with the first time constant circuit, and during playback when the tape running speed is low, the first time constant circuit with a large time constant is used to detect unrecorded parts, while when the tape is fast forwarding when the tape running speed is high. Alternatively, when rewinding, a method has been adopted in which a second time constant circuit with a small time constant is used to detect unrecorded portions.

しかしながら、このような時定数回路を用いる従来の方
法を駆使する回路の半導体集積回路(IC)化をはかろ
うとした場合、ICに対して外付部品として取り扱わね
ばならない回路部品数が多くなり、外部リード線数に制
限の課せられるICにおいては、このことが大きな不都
合として表面化するばかりでなく、さらに、これらの外
付部品のばらつきに起因する検出精度の低下も生じるの
であった。
However, when attempting to incorporate a circuit that makes full use of the conventional method using such a time constant circuit into a semiconductor integrated circuit (IC), the number of circuit components that must be handled as external components to the IC increases. In ICs where the number of external lead wires is limited, this not only becomes a major inconvenience, but also causes a decrease in detection accuracy due to variations in these external components.

本発明は以上説明した従来の方法における不都合の排除
を意図してなされたものであり、記録媒体の無情報位置
をデジタル的に検出することにより、回路のIC化を容
易にし、また、高い検出時間精度を得ることのできる無
情報位置検出回路を提供するものである。以下に図面を
参照して本発明の無情報位置検出回路の構成と回路の動
作について説明する。
The present invention has been made with the intention of eliminating the disadvantages of the conventional methods described above, and by digitally detecting the non-information position of the recording medium, it facilitates the integration of the circuit into an IC, and also achieves high detection accuracy. The present invention provides an information-free position detection circuit that can obtain time accuracy. The configuration and operation of the non-information position detection circuit of the present invention will be described below with reference to the drawings.

図は、本発明の一実施、例にかかる無情報位置検出回路
の構成例を示す図であシ、所定の周波数fで発振する発
振回路部1、例えば1o個のT形フリップフロップFF
1〜FF10を用いて構成されるとともに、1段目T形
フリップフロップFF1に発振回路部1の出力が入力さ
れ、また、記録媒体が無情報であるときリセットの解除
がなされるカウンタ2、同カウンタの所定の段(FF2
.FF3)の出力ならびに端子3に入力される検出時間
切換信号が入力されるNAND回路4、カウンタ2の所
定の段(FF2)、最終段(FF1o)の出力ならびに
検出時間切換信号音インバータ6で反転した信号が入力
されるNAND回路6ならびにNAND回路4と6の出
力が入力されるNAND回路7とで構成されている。な
お、8は出力端子であり、また端子3に入力される検出
時間切換信号は再生あるいは録音時には低レベル(”L
”)となり、一方、早送りあるいは早戻し時には高レベ
ル(”H″)となる。
The figure is a diagram showing a configuration example of a non-information position detection circuit according to an embodiment of the present invention, and includes an oscillation circuit section 1 that oscillates at a predetermined frequency f, for example, 10 T-type flip-flops FF.
1 to FF10, the output of the oscillation circuit section 1 is input to the first stage T-type flip-flop FF1, and the counter 2 is reset when the recording medium has no information. Predetermined stage of the counter (FF2
.. The output of FF3) and the detection time switching signal input to terminal 3 are input to the NAND circuit 4, the output of a predetermined stage (FF2) of the counter 2, the final stage (FF1o), and the detection time switching signal sound is inverted by the inverter 6. The NAND circuit 6 includes a NAND circuit 6 to which the signal is inputted, and a NAND circuit 7 to which the outputs of the NAND circuits 4 and 6 are inputted. Note that 8 is an output terminal, and the detection time switching signal input to terminal 3 is at a low level ("L") during playback or recording.
”), and on the other hand, it becomes a high level (“H”) during fast forwarding or fast reversing.

以上のように構成された図に示す無情報位置検出回路の
端子3の早送りあるいは早戻しに対応してH”入力が加
えられた場合には次のような回路状態が成立する。
When an H'' input is applied to the terminal 3 of the non-information position detection circuit shown in the figure and configured as described above in response to fast forwarding or fast reversing, the following circuit state is established.

すなわち、カウンタ2の2段目ならびに3段目の出力レ
ベルがともにH”となる時間を食とするとt=e/f(
秒)である。したがって、NAND回路4の出力はカウ
ンタ2へ発振回路部1の出力が加えられた時刻t0から
67を秒の時間が経過したところで”H″からL”へと
変化する。三方、NAND回路6には、端子3に加わる
”H”入力をインバータ6で反転した”L″出力加えら
れているため、その出力レベルは常時”−L”となって
いる。したがって、NAND回路4と6の出力が入力端
子に結合されているNAND回路7の出力レベルはNA
ND回路4の出力に依存して変化するところとなり、出
力端子8にも會。から6/を秒の時間が経過したところ
で出力パルスが発生する。
That is, if we take the time when the output levels of the second and third stages of the counter 2 are both H'', then t=e/f(
seconds). Therefore, the output of the NAND circuit 4 changes from "H" to L when 67 seconds have elapsed from the time t0 when the output of the oscillation circuit section 1 was added to the counter 2. Inverter 6 inverts the "H" input applied to terminal 3 and adds a "L" output, so its output level is always "-L".Therefore, the outputs of NAND circuits 4 and 6 are The output level of the NAND circuit 7 coupled to the input terminal is NA
It changes depending on the output of the ND circuit 4, and also applies to the output terminal 8. An output pulse is generated after a time of 6/seconds has elapsed.

一方、再生動作に対応して端子3に−”L″入力加えら
れた場合には、NAND回路401つの入力が“L”に
固定されるため、その出力レベルは“H”に固定される
。一方、NAND回路6の入力にはカウンタ2の2段目
、10段目の出力ならびにインバータ6で″′L#入力
を反転して得た“H″出力加えられている。ところで、
2段目出力ならびに10段目出力は時刻t□  から(
29+2)71秒の時間が経過したところでともに”H
”となる。したがって、NAND回路6の出力レベルは
時刻t から(29+2)/f秒後に“H”0 から′L″へと変化し、この時点と時を同じにして出力
端子8に出力パルスが発生する。
On the other hand, when a -"L" input is applied to the terminal 3 in response to the reproduction operation, one input of the NAND circuit 40 is fixed at "L", so its output level is fixed at "H". On the other hand, the outputs of the second and tenth stages of the counter 2 and the "H" output obtained by inverting the "'L# input" by the inverter 6 are added to the input of the NAND circuit 6. By the way,
The 2nd stage output and the 10th stage output start from time t□ (
29+2) When 71 seconds have passed, both “H”
Therefore, the output level of the NAND circuit 6 changes from "H" 0 to 'L' after (29+2)/f seconds from time t, and at the same time, an output pulse is sent to the output terminal 8. occurs.

なお、図示した回路では0、NAND回路4と6の双方
にカウンタ2の2段目出力を結合しているが、この構成
をとることにより端子8に生じる出力パルスの幅が上述
した双方の動作状態の下でも一定となる。
Note that in the illustrated circuit, the second stage output of the counter 2 is coupled to both the 0 and NAND circuits 4 and 6, but by adopting this configuration, the width of the output pulse generated at the terminal 8 can be adjusted to match both operations described above. It remains constant under various conditions.

このように動作する本発明を用いた回路では、カウンタ
2のリセットを、テープからの信号入力がある場合と、
無音部分の検出がなされ、さらにこの状態が所定の時間
以上にわたり継続しているときにかけるようになすなら
ば、カウンタ2のリセットは信号入力が途だえたところ
で解除され、この時点から発振回路部からの入力パルス
の計数を開始する。そして、上記のように、テープ走行
速度の遅い再生時には長い検出時間の設定がなされ、一
方、テープ走行速度の早い早送りあるいは早戻し時には
短い検出時間の設定がなされる。
In the circuit using the present invention that operates in this manner, the counter 2 is reset in two different ways: when there is a signal input from the tape;
If a silent part is detected and this state continues for a predetermined period of time, the reset of counter 2 will be canceled when the signal input stops, and from this point on, the oscillation circuit section will be reset. Start counting input pulses from . As described above, a long detection time is set during playback when the tape running speed is slow, while a short detection time is set during fast forwarding or fast reversing when the tape running speed is high.

以上説明したところから明らかなように、本発明のテー
プ位置検出回路によれば、単一の回路で長短2種の検出
時間の設定が可能であり、しかも時間設定に関与する回
路がデジタル回路構成であるため、全てをIC化するこ
とが容易となる。また、検出時間の設定が発振回路部1
から出力される発振出力信号周波数に基いてなされてい
るため、設定精度、すなわち検出精度を著るしく高める
こともできる。
As is clear from the above explanation, according to the tape position detection circuit of the present invention, it is possible to set two types of detection time, long and short, with a single circuit, and moreover, the circuit involved in time setting has a digital circuit configuration. Therefore, it is easy to integrate everything into an IC. Also, the detection time setting is
Since this is done based on the oscillation output signal frequency output from the oscillation output signal frequency, the setting accuracy, that is, the detection accuracy can be significantly improved.

なお以上の説明はテープレコーダで用いるテープの無情
報位置の検出を例に行ったが、本発明は、VTR用テー
プあるいはビデオディスク等の記録媒体における無情報
の位置検出に用いて同様の効果をうることかできる。
Although the above explanation has been made using the example of detecting a position with no information on a tape used in a tape recorder, the present invention can be used to detect a position with no information on a recording medium such as a VTR tape or a video disc to achieve the same effect. I can do it.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例にかかる無情報位置検出回路の構
成を示すブロック図である。 1・・・・・・発振回路部、2・・・・・・カウンタ、
3・・・・・・・検出時間切換入力の印加される端子、
4゜6.7・・・・・・NAND回路、5・・・・・・
インバータ、8・・・・・出力端子、FF1〜FF10
・・・・・・T形フリップフロップ。
The figure is a block diagram showing the configuration of a non-information position detection circuit according to an embodiment of the present invention. 1...Oscillation circuit section, 2...Counter,
3...Terminal to which the detection time switching input is applied;
4゜6.7...NAND circuit, 5...
Inverter, 8...Output terminal, FF1 to FF10
...T-type flip-flop.

Claims (3)

【特許請求の範囲】[Claims] (1)所定の周波数で発振する発振回路部と、分周器を
多段接続して構成されるとともに、情報記録媒体の記録
情報の消失点でリセットが解除され、前記発振回路部か
らの出力信号を計数するカウンタと、前記情報記録媒体
の走査速度の大小に対応してレベルが変化する切換信号
の入力される端子と、同端子に加わる前記切換信号と前
記カウンタの所定の分周段からの出力に応じて動作する
論理回路部とを備え、前記切換信号のレベル変化で前記
カウンタの分周比が変化し検出時間が変化することを特
徴とする無情報位置検出回路。
(1) It is constructed by connecting an oscillation circuit section that oscillates at a predetermined frequency and a frequency divider in multiple stages, and the reset is released at the vanishing point of the information recorded on the information recording medium, and the output signal from the oscillation circuit section is a terminal for inputting a switching signal whose level changes depending on the scanning speed of the information recording medium; a logic circuit section that operates according to an output, and a frequency division ratio of the counter changes according to a change in the level of the switching signal, and a detection time changes.
(2)  論理回路部が、切換信号を位相反転するイン
バータと、カウンタ中の第1の分周器の出力発生点と切
換信号の入力される端子に入力端子が繋る第1の論理積
回路と、カウンタ中の第2の分周器と、前記インバータ
の出力発生点とに入力端子が繋る第2の論理積回路と、
第1および第2の論理積回路の出力発生点に入力端子が
繋る第3の論理積回路で構成されていることを特徴とす
る特許請求の範囲第1項に記載の無情報位置検出回路。
(2) The logic circuit section includes an inverter that inverts the phase of the switching signal, and a first AND circuit whose input terminal is connected to the output generation point of the first frequency divider in the counter and the terminal into which the switching signal is input. and a second AND circuit whose input terminal is connected to a second frequency divider in the counter and an output generation point of the inverter;
The information-free position detection circuit according to claim 1, characterized in that it is constituted by a third AND circuit whose input terminal is connected to the output generation points of the first and second AND circuits. .
(3)第1および第2の論理積回路の双方に、第1およ
び第2の分周器より前段側に位置する第3の分周器の出
力が結合されていることを特−とするtし←叡 特許請求の範囲第1項泰命6献第2項に記載の無情報位
置検出回路。
(3) The first and second AND circuits are both coupled to the output of a third frequency divider located at a stage before the first and second frequency dividers. An information-free position detection circuit according to claim 1, paragraph 2 of the patent.
JP56164809A 1981-10-14 1981-10-14 Noninformation position detecting circuit Granted JPS5864652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56164809A JPS5864652A (en) 1981-10-14 1981-10-14 Noninformation position detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56164809A JPS5864652A (en) 1981-10-14 1981-10-14 Noninformation position detecting circuit

Publications (2)

Publication Number Publication Date
JPS5864652A true JPS5864652A (en) 1983-04-18
JPH0368459B2 JPH0368459B2 (en) 1991-10-28

Family

ID=15800323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56164809A Granted JPS5864652A (en) 1981-10-14 1981-10-14 Noninformation position detecting circuit

Country Status (1)

Country Link
JP (1) JPS5864652A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5794951A (en) * 1980-12-01 1982-06-12 Pioneer Electronic Corp Setter for recording start position of tape recorder

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5794951A (en) * 1980-12-01 1982-06-12 Pioneer Electronic Corp Setter for recording start position of tape recorder

Also Published As

Publication number Publication date
JPH0368459B2 (en) 1991-10-28

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