JPS586426A - Detector for optical energy - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a light energy detection device, and more particularly to an infrared light energy detection device using a charge transfer amount sensing device.

There are two types of thermal imagers: gaze and non-gaze. The non-gazing device includes an optical assembly for focusing infrared radiation emanating from a scene entering the field of view, a scanning assembly for scanning the focused infrared radiation, and a signal scanning assembly for scanning the focused infrared radiation. and an infrared detector for converting into an electrical signal representative of the scene to a processing device. The signal processing device includes a preamplifier that amplifies the electrical signal to an operational level for processing into a video signal. The signal emitted by a prior art infrared detector without time delay and integration is directly proportional to the time it takes for the smallest resolvable pixel to cross the detector (integration time). That is, the noise limited by the background radiation (raatation −'
background -11m1ted noise
) and background-restricted ( bacJround −1
1m1tecL)8N ratio is directly proportional to the square root of the integration time. The integration time is set depending on the image scanning speed and size of the detector.
Therefore, the integration time cannot be increased arbitrarily in prior art detectors.

An infrared detector fabricated on an infrared sensitive material such as mercury-cadmium-tellurium (Hg0dTe) already includes a parallel shift register read out to the floating date or diode output of the unit.

This parallel register has two, three or four phases per stage. The circuit used in floating r-) is (1)
Output and reset field effect transistor (E
FT) or (2) a silicon chip with output and reset field effect transistors. Each stage in the shift register constitutes one infrared detector, so a shift register with "n" stages has rnJ infrared detectors read out from one floating date or diode output.

The infrared detector is used in conjunction with a mechanical scanner that moves the infrared image parallel to the direction of charge transfer in parallel registers. The moving speed of the infrared image is made equal to the average moving speed of the charge in the register. Therefore, when an infrared pixel (pixel) is scanned simultaneously with a phase shift, each bit of data output from the parallel register is
Viewing the same infrared pixel moving across parallel registers.

Therefore, a problem in the prior art was that the charge packets in the potential wells of parallel shift registers increased in size from the first stage to the last stage and overflowed after saturation. To prevent this overflow, the integration time for the signal photons must be reduced. However, since the signal output is directly proportional to the integration time, the limit set by this overcharging is very detrimental. Prior art devices have been set up by field breakdown in empty wells on infrared sensitive materials such as high volume mercury-cadmium tellurium. In the present invention, greater capacitance is obtained by using successively increased voltages and well depths along the parallel shift registers. That is, the background infrared radiation increases along the length of the shift register.
ero aharge). This background7 at zero charge can be set to preserve the available charge capacity and the electric field coefficient along the length of the shift)ll'Q register.

In a charge-coupled device (0 (ID) shift register, 7
fat zero charge
must be placed into the well to completely fill the surface states and improve charge transfer efficiency. The 30% 77 zero requirement is a typical requirement for good charge transfer efficiency. A fat zero charge is typically placed at the far end of the 77 register, and this 7 fat zero charge reduces the charge capacity available for storing charge generated by the infrared background and signal. In an infrared background, the continuous clock used in operating the stages of parallel registers causes the charge generated by the infrared radiation or by the dark current to collect. This charge generated by the infrared detector or dark current constitutes an additional 77 zero charge that increases from the first stage to the last stage of the OOD. The presence of this larger fat zero charge in the stage after iIk and the presence of a smaller 7 fat zero charge in the first stage results in superior charge transfer efficiency (
OTIC) and a substantially degraded OTH in the first stage where charge transfer efficiency has the greatest impact on operation.

It is therefore an object of the present invention to provide an infrared detection and imaging device with improved sensitivity and 8N ratio.

Another object of the present invention is to improve infrared collection efficiency through increased integration time.

Yet another object of the invention is to increase the storage capacity of an infrared storage location.

Yet another object of the invention is to improve charge transfer efficiency for transferring infrared charge packets.

Briefly stated, the present invention comprises a forward facing infrared (IFLIR) device that includes a lens assembly, a scanning assembly, a detector assembly, and video electronics. The detector assembly includes a ramped charge transfer device (O
T'D) consists of a matrix. The matrix includes a plurality of charge transfer device elements arranged in columns and rows. Each pair of this array of elements constitutes a stage, and each family of elements in each stage is an OTD having a preselected number of phase electrodes. It is selectively used to collect and transfer this charge packet to the next stage. An increasing (ramping) voltage is applied to selected elements of each stage to sequentially increase the charge collection capacity of the matrix. These two voltages are applied in synchronization with the scanning speed. Each stage of the element therefore sees the same image, and after the first stage, the next stage takes charge packets from the previous stage and adds to this further charge packets representing the same scene part. . In this way, the voltage representing the scene increases substantially with l becoming the actuation voltage, and the integration time increases substantially.

A preferred embodiment of the present invention will be described in detail below with reference to the drawings. In the drawings, like parts are given the same reference numerals to make the components and features of the invention clearer and easier to understand.

Referring now to FIG.
．． It consists of a video electronics circuit 18 and a display or light source 20. The lens assembly 12 is comprised of three lens elements (not shown) and may include three aluminum elements for operation in the infrared region.

These elements collect infrared energy emanating from the scene and concentrate this energy onto a rotating mirror of scanning assembly 14, not shown.

The rotating or changing mirror may be, for example, a double-sided plane mirror. The first side, or front side, of the mirror is used to receive and receive infrared energy, and the second side, or back side, of the mirror is used to scan the modulated visible light from the light source 20. The scanning mirror has its rYJ axis perpendicular to the optical axis, and its rXJ
The axis is placed at an angle of 45° to this. The scanning mirror is rotated by a small synchronous motor or possibly a solenoid at a speed that provides a preselected frequency, such as 60 or 60 scans per second. The solenoid moves the mirror against the return spring, causing it to vibrate.

The scanning mirror reflects the infrared radiation to a folding mirror, not shown, and to a detector array of detector assembly 16, which will be described in detail below.

The detector play converts the infrared energy into an electrical signal for processing in video electronics circuitry 18. The video electronics provides signal processing assistance for modulating the output of light source 20 or other display device. The light source or display device 20 can be an array of light emitting diodes or a cathode ray tube (OR?). These desirable features of suitable construction of the above-mentioned elements [opto-mechanical devices for phase shift compensation of vibrating mirror scanners]
evioe For Phase13hift OOm
Penaration Of Oscillating
Mirror8oannars) 197 in the name of J
Rlchard G, Hoff on October 14, 2015
U.S. Patent No. 3,912.9 granted to man% I
Please refer to No. 27.

Referring now to Figures g2a and 2b, the detector play assembly 16 consists of a charge transfer device (0'I'D) and an infrared sensing matrix 22. The TD matrix 22 preferably comprises a charge coupled device (OOD) matrix. The OOD matrix 22 is essentially a plurality of parallel 00D shift registers with OOD elements arranged in rows and columns. Although a 6.times.6 array 22 of elements is shown for illustrative purposes, it will be appreciated that in practice much larger plays may be used. Each element 24 (Fig. 2a) and the semiconductor substrate 26 (Fig. 6)
Configure above. This substrate is, for example, an n-made water@/cadmium/tellurium (Hg0dTe) substrate.

Another tight material is Pt+ 8n To *E8'
kt and Ga engineering n8b. For example, a layer 2B of an insulating material, such as Zn, is formed on the substrate 26, and this layer is metallized with an infrared transparent metal, such as nickel, for example 100-150 µm thick. ) to form a plurality of electrodes 30 and 32 of the second level. Another layer 34 of insulating material is formed over the first layer 28 and over the electrodes 30 and 32, and this second layer is metallized with another infrared transparent metal such as thin nickel and has a plurality of layers. Another level electrode 36
and 38. Electrodes 36 and 38 The electrodes 30 and 32 are formed so as to be partially electrically conductive. Those skilled in the art desiring detailed information regarding the construction of OOD resistor elements may refer to "Narrow Pandey Semiconductor 00D Imaging Device and Manufacturing Method" (Nar.
row Bandgap Iiismiaonduct
or OOD engineeringDevioe and M
See U.S. Patent Application No. 950,191, filed October 10, 1978.

Electrodes 30.32.36 of each stage of parallel shift register
, and 38 connect to metalized motherboard #44. A clock driver 40 that connects the metal busbar directly to a four-phase parallel clock generator 42 or provides several different amplitude (ramp) pulses on the phase-2 and phase-4 waveforms.
valve and connect indirectly to the clock generator. The frequency of the parallel clock generator is set to a value that provides the period of the moving potential well and the moving infrared image.

The detector elements 24 of each column are connected to the busbar in the following manner. That is, the electrodes of phase 1 of each element are connected together, the electrodes of phase 2 are connected one after the other in pairs, the electrodes of phase 3 are connected together 11' in a row, and the electrodes of phase 4 are connected one after the other. Connect in pairs. The phase 1 and phase 3 electrodes receive a preselected voltage Vl as the transfer date.

The phase 2 voltages of stages B1 and O are respectively preselected voltages Vie, e v21. s and v2°.

Moreover, the phase 4 electrodes of stages B and 0 have given voltages v, a, v, b, v, respectively. receive. Voltage V, 1LI
Vabe Vg□ (and V4@a 741) e
v40) is a two-volt voltage that is small at the first stage and becomes maximum at the last stage. For purposes of disclosure, the phase 2 and phase 4 electrodes are in pairs. 1 per clock amplitude, based on a compromise between the requirement for a nearly continuous increase in amplitude (linear ramp) and the requirement to limit the maximum number of bond pads to multiple clock amplitudes and multiple busbars. Other combinations can also be used, such as three or more for each clock amplitude.

The serial shift register 46 is connected to the output r-) 45 K] to the output of the parallel shift register 220 column. The serial shift register 46 is also a four-phase 00D shift register (Figure 4) whose parts are identical to those of the parallel shift register, but each potential well has a width similar to that shown in Figure 2a. is wide and has a constant value (slope (ram
p) ramped parallel shift register matrix by a series of clocks
Provides enough charge capacity to hold the charge packet output. A serial clock generator 48 (FIG. 2) controls the phase operation of the serial shift register.

The output of the serial shift register 46 is a floating r-) 52 or diode fabricated on an infrared sensing semiconductor (FIG. 4).
I'll go. The floating r-) 52 (FIG. 4) is a metal-insulator-semiconductor (Mzs) structure.

That is, it consists of a semiconductor substrate supporting an insulating layer,
It has a metallized electrode on top of an insulating layer manufactured in the same way as the phase electrode. The floating date has sufficient capacity to hold each integrated charge packet. Sufficient capacity at maximum voltage of the empty well is obtained by increasing the area (ie, width or width and length). Floating RT 52 or diode connects to buffer circuit 55, reset FIT 54, and flange, sample and hold circuit 56 of video electronics circuit 18. The clock-sample-and-hold circuit 56 is fabricated on a separate silicon chip from the infrared sensing chip.

In one embodiment, the buffer FM'T and the reset FI
T is fabricated in an infrared sensing semiconductor. In another embodiment,
A buffer FIfT and a reset FET are fabricated on a silicon chip in contact with an infrared sensing semiconductor chip.

In lamp operation (figure g5), the clock voltage vl.

V11 & books V, b and v2° are used for each stage of the parallel register matrix 22 (FIG. 2a). 2 bing is most important for longer wavelengths (narrow bandgap) 00D, and 4 to obtain a significant improvement in the 8M ratio.
~12 parallel stages are sufficient: C.

As illustrated in FIG. 5, clock pulses of voltage Vl are applied to OO
It is simultaneously applied to the phase 1 electrode of each D element. Shortly before the phase 1 clock pulse turns off, the voltage vII
a# v, bs and v, g. Four pulses are applied to the phase 2 electrodes of the OOD element pairs making up stages, Bl and 0, respectively. Then, shortly before this clock pulse to the phase 2 electrodes is turned off, a clock pulse of voltage v1 is simultaneously applied to each phase 3 electrode, with concomitant turning off of the phase 1 clock pulse.

Finally, shortly before the phase 6 clock pulse turns off, the voltage v4! L·v4b1 and v4° clock pulses are applied to the phase 4 electrode, respectively, with concomitant turning off of the phase 2 clock pulse.

As already explained, the average speed of clocking is synchronized with the scanning speed of the device. Therefore, as shown in FIG. 6, at time t1, a bright 1ffii image is scanned and focused on the second phase 2 potential well, and at time t2, a charge packet representing the bright image of stage A is scanned. coincides with the collection of a bright image identical to that detected in the second scan, i.e. stage B of the fourth phase 2 potential well.
The potential well of o#I2 is reached, and at time t3, the integrated charge packets of step M and B are focused at the same bright ll1j image as that detected in the first and second stages, and at the same time the sixth phase is detected. 2, the second potential well of stage 0 is reached. The ramping voltage of FIG. 5 provides a constant capacitance for the total charge in the charge packet, including the charge generated by the infrared background and the signal. The integrated charge packets are then output to a serial shift register and clocked out to the floating r-toad. Each element of the serial shift register is large enough to hold an integrated charge packet. Thus, the device has a time delay as well as an integration.

FIG. 7 illustrates the potential well of a prior art device using the same integration time.

As shown, the potential well at time t3 is insufficiently deep to hold the charge packet, which causes an overflow or avalanche. In the prior art, the maximum charge capacity is set by the maximum voltage in the first stage and the depth of the empty well, and in the ramped array of Figure 05M6 this maximum value is set by the electric field breakdown in the infrared sensing semiconductor. , #l The maximum voltage in empty stage 1 is low to avoid field breakdown, and the wells in the last stage are deep enough to accommodate the entire charge. The field breakdown in the sixth well of FIG. 6 is avoided by the background generated in this last well.

A series of shift registers (Figure 2a), one for each column (
(Fig. 8) can be replaced by a plurality of floating dates. In this embodiment, each floating r-) has its own preset and buffer PET. The structure of each is that shown in FIG. 2b, ie, that of FIG. The embodiment of FIG. 8 has at least the following two advantages. (1) the complexity of serial shift registers and clocks is not required; and (2)
The frequency bandwidth to be given to the signal processing circuit is the second
This means that it is much lower than what is required for signal processing of the output from the array in Figure a. Smaller electronic bandwidth means narrower noise in the buffer IPET.

While several embodiments of the invention have been described herein, it will be appreciated by those skilled in the art that various modifications may be made to the details of construction shown and described without departing from the scope of the invention. It will be obvious.

[Brief explanation of drawings]

1 is a block diagram of a forward facing infrared device, FIGS. 2a and 2b are diagrams showing the matrix and associated circuitry of the Hiro charge transfer device, and FIG. 3 is a parallelism obtained along the line Moom in FIG. 4 is a partial sectional view of the series shift register taken along line B-H in FIG. 2a; FIG. 5 is a partial sectional view of the shift register; FIG. Figure 6 shows the clock pulses or voltages corresponding to the division of the clocks in phase 2 and 4;
FIG. 7 shows the formation of signal, signal and background charges in a tilted well while bright image vixels move simultaneously with the potential well; FIG. FIG. 8 is a plan view of another embodiment of the present invention. Description of symbols 10... forward-facing infrared device, 14... scanning assembly. 16...Detector assembly, 18...Video electronics circuit, 22...Charge transfer device extra-radiation sensing matrix,
24... Charge coupled device element, 30.32.36° 38... Electrode, 44... Bus bar, 40... Clock driver, 42... Parallel clock generator, 46...
Serial shift register, 48... serial clock generator,
52...Floating r-t, 54...Reset FIIfT
, 55... buffer circuit. Agent Kogai Asamura Engraving of the drawings by 4 people (no changes to the content) O Ftgz/ - Procedural amendment (method) February 170, 1932 Commissioner of the Japan Patent Office 1, Indication of the case Showa Taro Patent Application No. 99otyZ 2. Name of the invention: 2 & Meibutsu (Tachi) 3. Relationship between the person making the amendment and the case Patent applicant 4. Agent 241-January 2019 6. Number of inventions increased by amendment 7. Subject of correction

Claims (1)

Claims: (1) A light energy detection apparatus comprising: a) a scanning assembly for scanning light energy emanating from a scene at a preselected rate; and)) a scanning path of the scanning assembly. a matrix of optical energy detectors of a charge transfer device arranged in rows and columns for converting incident optical energy within the receiver into electrical charge packets representing the optical energy received; comprising a plurality of charge transfer device elements, the elements of said charge transfer device columns being selectively connected together to form a plurality of integrating stages and synchronized with said scanning assembly; means for applying voltages of a plurality of selected amplitudes to the integrating stages, thereby converting the electrical charge packets of the first stage into the charges of each successive stage of the plurality of integrating stages; With the packet! C) said light energy detector matrix for providing a time delay with the integration of charge packets representing the same scene; and C) for processing said integrated signal into a video signal representative of light energy emanating from the scene. The optical energy detection device characterized by: a signal processing device; and a wire comprising: (2. Scope of claims! In the first item, the optical energy detector ff) The optical energy detecting device is characterized in that the optical energy detector ff is a charge-coupled device. (3) In claim 2, each charge-coupled device comprises a first preselected number of electrodes constituting a potential well and a second constituting a transfer r-). means for connecting a preselected number of electrodes and corresponding preselected pairs of potential well forming electrodes to a selected ramp voltage; and means for transferring electrical charge packets from one potential well to another. and means for connecting the pre-transfer date electrode to a preselected voltage for the purpose of transferring the light energy to a predetermined voltage. (4) The optical energy detection device according to claim 1, wherein the device for applying voltages of the plurality of selected widths is a lamp generator. (5) Claim 1 is characterized in that the elements of the row of charge transfer devices are assembled together in a preselected number to form a preselected number of stages. The optical energy detection device. (6) % Allowance In claim 1, the charge-coupled device of the detector matrix is Hg0dT. Pb8nTe, engineering! 18 b e engineering nAa8bs G
The optical energy detection device is fabricated on a semiconductor material with a narrow bandgap selected from the group consisting of a-nib. (7) As defined in claim 1, wherein each detector stage of the plurality of stages includes one stored potential well date, and a ramp generator of 3111
The optical energy detection device is characterized in that it is connected to each storage potential well to provide a ramped bias increasing from stage to last stage. (8) In claim 2, each charge-coupled device of the matrix has four electrodes, a clock generator and a clock driver for four-slide operation, and has a clock generator and a clock driver for phase 2 and phase 4 electrodes. Separate connections 4, a first set of connections to each phase 1 electrode and another to all of the phase 3 electrodes.
The optical energy detection device is characterized in that it is provided with two sets of connections to provide pseudo two-phase operation. (9) 4! In claim 1, the 1g
a serial shift register for multiplexing the integrated charge packets of the charge transfer device detection matrix; and a serial shift register at the end of the serial shift register for converting the charge packets into voltage signals for video processing. t- The optical energy detection device characterized in that it comprises a floating f-). (11) In claim 9, the series shift register includes wells having a capacitance substantially greater than the capacitance of the potential wells of each detector column so as not to ramp charge from the detector column. The optical energy detecting device is characterized in that the potential well of the serial shift register is configured such that the potential well of the serial shift register does not cause electric field breakdown. A floating r connected to the output date of each column of the charge transfer device detector matrix for
-) The optical energy detection device. 03. In claim 11, the floating gate has a potential well capacity sufficient to accommodate the output of the ramped charge without causing field breakdown before receiving or taking the ramped charge. The optical energy detection device characterized by: