JPS5863883A - Electronic clock provided with recording function - Google Patents

Electronic clock provided with recording function

Info

Publication number
JPS5863883A
JPS5863883A JP56163330A JP16333081A JPS5863883A JP S5863883 A JPS5863883 A JP S5863883A JP 56163330 A JP56163330 A JP 56163330A JP 16333081 A JP16333081 A JP 16333081A JP S5863883 A JPS5863883 A JP S5863883A
Authority
JP
Japan
Prior art keywords
circuit
storage
signal
contents
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56163330A
Other languages
Japanese (ja)
Other versions
JPH0259438B2 (en
Inventor
Hitomi Ayusawa
仁美 鮎澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP56163330A priority Critical patent/JPS5863883A/en
Publication of JPS5863883A publication Critical patent/JPS5863883A/en
Publication of JPH0259438B2 publication Critical patent/JPH0259438B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G99/00Subject matter not provided for in other groups of this subclass
    • G04G99/006Electronic time-pieces using a microcomputer, e.g. for multi-function clocks

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)

Abstract

PURPOSE:To easily decide the meaning of an alarm tone by reading out and controlling a pair of storage circuits in which contents with different recognition rates each other are stored through different frequency signals respectively. CONSTITUTION:The operation mode of the titled clock is turned to a voice input mode by depressing a switch 16 to use a speaker as a microphone. The inputted voice is stored in the 1st storage circuit 9 through an I/O switching circuit 13 and an A/D converter 7. On the other hand, voice signals have been already recorded in the 2nd storage circuit 10 at the time of its production. When a coincidence circuit 5 detects an optional set time, a memory controlling circuit 8 is actuated to read out the contents of the storage circuits 9, 10, select any one of the circuits 9, 10 through a selecting circuit 11 and inform the recorded contents from a speaker 15 through the circuit 13. In said circuit configuration, a RAM and a ROM are used for the storage circuits 9 and 10 respectively, and at the reading out from the circuit 10, the frequency of a sampling frequency signal is increased and the circuit 9 is controlled.

Description

【発明の詳細な説明】 本発明は、音声を録音できるようにした録音機能付電子
時計に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic watch with a recording function that can record audio.

近年、電子時計は、多機能化が進み、アラーム機能等を
備えたものがある。
In recent years, electronic watches have become more multifunctional, and some are equipped with alarm functions and the like.

そして、任意に設定されたアラーム時刻に、なった時に
、規定の周波数信号により、ブザーを駆動して、報音し
たり、或−は、メロディ−を報知して、使用されてLA
fco しかし、アラーム音は、メーカーサイドに1って決めら
れた固定の音、或すは、メロディ−しか報音する事がで
きなかった。この工つな機能の場合には、使用者の好み
に合わなかったり、あ^てきたりするものであり、しか
も、アラーム音を伺んのために鳴らしたのかを、自分で
記憶しておかなければならなかった。
When an arbitrarily set alarm time is reached, a buzzer is driven by a specified frequency signal to sound a sound or a melody, and the LA is used.
fco However, the alarm sound could only be a fixed sound determined by the manufacturer or a melody. In the case of this unconventional function, it may not suit the user's tastes or may turn him off, and what's more, he has to remember when the alarm sounded to ask for it. I had to.

本発明は、これらの欠点を改良したものであり、使用者
が容易に操作でき、アラーム音が、何を意味しているの
かを容易に判断できる電子時計を提供する事を目的とし
てrる。
The present invention has been made to improve these drawbacks, and aims to provide an electronic timepiece that can be easily operated by the user and allows the user to easily determine what the alarm sound means.

2− 以下に図面を用すて、一実施例にエリ詳細に説。2- One embodiment will be explained in detail below using drawings.

明する。I will clarify.

第1図に示すのは、本発R11による録音機能付電子時
計の回路構成図である。
FIG. 1 is a circuit diagram of an electronic timepiece with a recording function according to the present invention R11.

■は発振回路であり、時間標準となる基準信号全出力す
る。発振回路1の出力を、分周回路2で分周して、泪時
に必要な低固波に分周する。そして、カウンター回路3
に工って、時刻がH1測される。4は、アラーム設定カ
ウンター回路であり、スイッチNt制御回路6の出力信
号にエリ、使用者が任意に時刻を設定する事ができ、ア
ラーム設定カウンター回路4と、カウンター回路3の一
致を、一致回路5が検出すると、メモ’I  flil
l m1回路8が動作し、第1の記憶回路9.或いは第
2の記t(3回路10の内容を読み出し、選択回路11
に工っで、第1の記憶回路9.或すは、第2の記憶回路
IOの、符号化された音声信号を選択し、デジタル−ア
ナログ変換器12 (以下、D/Af換器と記−1−)
に工っで、音声信号を合成し、入出力切り換え回路13
全通し、増幅回路・フィルタ−14′ft通して、スビ
ー3− カー15力)ら報音される。スイッチ16が、操作され
、音声入力モードになると、チャタ防止鵞スイッチ制御
り路6によって、メモリー制御回路8から、入出力切り
換え回路13に、入力制御の信号が入力され、スピーカ
ー15を、マイクとして使用できる状態となる。そして
、音声が入力されると、アリーログーテジタル変換器7
(以下、Aμ変換器と記す)によって、音声・は号が、
符号化され、第1の記憶回路9に店き込せれる。そして
、アラーム時刻の一致、或いは、スイッチ操作に1って
、音声を出力する時は、前記に説明したように動作する
(2) is an oscillation circuit, which outputs the entire reference signal that becomes the time standard. The output of the oscillation circuit 1 is frequency-divided by a frequency divider circuit 2, and is frequency-divided into a low frequency wave required at the time of crying. And counter circuit 3
The time is measured by H1. 4 is an alarm setting counter circuit, which allows the user to arbitrarily set the time on the output signal of the switch Nt control circuit 6; 5 is detected, the memo 'I flil
The l m1 circuit 8 operates, and the first memory circuit 9. Alternatively, in the second note (read the contents of the three circuits 10 and select the selection circuit 11
Specifically, the first memory circuit 9. Alternatively, the encoded audio signal in the second storage circuit IO is selected and the digital-to-analog converter 12 (hereinafter referred to as D/Af converter-1-)
The input/output switching circuit 13 synthesizes the audio signal using
The signal is transmitted through the amplifier circuit and filter 14'ft, and a sound is output from the speaker 3-car 15'. When the switch 16 is operated to enter the audio input mode, an input control signal is inputted from the memory control circuit 8 to the input/output switching circuit 13 by the chatter prevention switch control path 6, and the speaker 15 is used as a microphone. It becomes ready for use. Then, when the audio is input, the Allilog digital converter 7
(hereinafter referred to as Aμ converter), the sound and sign are
The data is encoded and stored in the first storage circuit 9. When the alarm times match or when a switch is operated, the sound is outputted as described above.

以上、説明したように、第1の記憶回路に書き込捷れた
音声信号は、特にウォッチの場合、使用者が、入力した
ものであり、その音声を聞いた時の認識率は、非常に高
いものとなる。父、第1の記憶回路は、書き込み・読み
出しの可能な記憶回路(例えば、RAM)で構成されな
ければならず、音声を符号化する時のサンプリング周波
数によっては、非常に大きな負荷となってしまう。例え
ば、量子化を6ビツト、サンプリング周波数1(l K
 Hz4− とすると、1秒間の音声をF t、&するのに、印キロ
・ピットの記憶回路を必要とする。しかし、使用者が、
音声を入力して使用する製品では、前記に説明したよう
に、認識率が非常に高いために、サンプリング周波数を
低(して、音質が悪くなっても、充分に使用可能である
。しかし、第2の記憶回路10に、記憶されている音声
信号は、製造段階で作り込せれたものでJ・す、認識率
は、低(なる。
As explained above, the audio signal written to the first memory circuit and interrupted is input by the user, especially in the case of a watch, and the recognition rate when listening to the audio is very high. It will be expensive. Father, the first memory circuit must be composed of a memory circuit that can be written to and read from (e.g. RAM), and depending on the sampling frequency used to encode the audio, this can result in a very large load. . For example, if the quantization is 6 bits and the sampling frequency is 1 (l K
Assuming Hz4-, a kilo-pit storage circuit is required to store one second of sound as Ft,&. However, the user
As explained above, products that use voice input have a very high recognition rate, so they can be used even if the sampling frequency is lowered (and the sound quality deteriorates).However, The audio signals stored in the second storage circuit 10 were created at the manufacturing stage, so the recognition rate is low.

しかし、第2の記憶回路10は、読み出し専用の記憶回
路(ROM)であるため、IC化する場合、その集my
は、非常に高い。
However, since the second memory circuit 10 is a read-only memory circuit (ROM), when integrated into an IC, the
is very high.

以上の理由にエリ、本発明では、第1の記憶回路9をR
AMで構成し、@2の11;憶回路1()をROMで構
成し、第2の記憶回路10のデータf読み出す時は、メ
モリー制御回路8に1って、選択回路11が、第2の記
憶回路のデータを選択して、D/A変換器に供給すると
共に、第2の記t@回路lOの読み出しを制御するサン
プリング周波数信号の周波数を、第1の配憶回路9を1
1111 ?llAlするよう制御される。
For the above reasons, in the present invention, the first memory circuit 9 is
When the memory circuit 1 () is configured with a ROM and the data f in the second memory circuit 10 is read, the memory control circuit 8 is set to 1, and the selection circuit 11 is The data of the first storage circuit 9 is selected and supplied to the D/A converter, and the frequency of the sampling frequency signal that controls the readout of the second memory circuit 10 is selected and supplied to the D/A converter.
1111? llAl.

5− 以上、述べた工うに本発明を採用すれば、使用者が、登
録を行なう音声出力と、製造段階で作り込1れた音声出
力の認識朋を、簡単な回路の追加にエリ、同程囲にする
事が可能であり、記憶回路のIC上での負担も、集fJ
tlffの低め第1の記憶回路のとットレート全低(、
集積朋の高い第2の記憶回路のビットレートを高い方式
であるため、製品構成上は、問題とはならなり0
5- If the present invention is adopted as described above, the user can easily recognize the voice output for registration and the voice output built in at the manufacturing stage by simply adding a circuit. It is possible to reduce the burden on the IC of the memory circuit and reduce the burden on the IC.
Low tlff Overall low hit rate of the first storage circuit (,
Since the bit rate of the highly integrated second memory circuit is high, there is no problem with the product configuration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図・・本発明による録音機能付電子時計の回路構成
図 1・・発振回路 2−・分周回路 3・・カウンター回
路 4・−アラーム設定カウンター回路5・・一致回路
 6・・チャタリング防止・スイッチ制御回路 7・・
A/D変換器 8・・メモリ→制御回路 9e・第1の
記憶回路 1()・・第2の記憶回路 11−・選択回
路 12・・D/A変換器 13・・入出力切り換え回
路 14・−アンプ・フィルター 1511−スピーカ
ー(マイク)  16・・スイッチ群。 6−
Figure 1: Circuit configuration diagram of the electronic watch with recording function according to the present invention 1: Oscillator circuit 2: Divider circuit 3: Counter circuit 4: Alarm setting counter circuit 5: Matching circuit 6: Chattering prevention・Switch control circuit 7...
A/D converter 8...Memory→control circuit 9e*First memory circuit 1()...Second memory circuit 11-*Selection circuit 12*D/A converter 13*I/O switching circuit 14 -Amplifier filter 1511-Speaker (microphone) 16...Switch group. 6-

Claims (1)

【特許請求の範囲】 外部から入力される音声を符呆化する符呆化手段、この
符景化手段からの符号1ヒ悟号が、壱六込オれる第1の
記憶回路、予め固定的に、将兵化された信号を配憶して
いる第2の記憶回路、前記、配憶回路の符号化信号を読
み出し、音声信号に変換する音声合成回路、音声合成回
路の出力により、音声を発生する発音手段と、前記、記
憶回路の読み出し、及び書き込みを制御する制御回路を
有する録音機能付電子時計におめで、前記、第1の記憶
回路の読み出し、1′#込みf制御する周期信号と、第
2の記憶回路の読み出しを制御する周期信号が、異なり
、第2の記憶回路fr Il+御する周期信号の方が、
周期の短い信号を出力する工う制御される制御回路′f
有する事を特徴とする録音機能付電子時計。 i−
[Scope of Claims] Encoding means for encoding audio input from the outside, a first memory circuit into which the code 1 Higogo from the encoding means is fixed in advance, a second memory circuit that stores the generalized signal; a speech synthesis circuit that reads out the coded signal of the memory circuit and converts it into a speech signal; and a sound generator that generates speech by the output of the speech synthesis circuit. and a periodic signal for controlling the reading and writing of the first storage circuit; The periodic signals that control the reading of the second storage circuit are different, and the periodic signal that controls the second storage circuit frIl+ is
A controlled control circuit 'f that outputs a signal with a short period
An electronic clock with a recording function characterized by: i-
JP56163330A 1981-10-13 1981-10-13 Electronic clock provided with recording function Granted JPS5863883A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56163330A JPS5863883A (en) 1981-10-13 1981-10-13 Electronic clock provided with recording function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56163330A JPS5863883A (en) 1981-10-13 1981-10-13 Electronic clock provided with recording function

Publications (2)

Publication Number Publication Date
JPS5863883A true JPS5863883A (en) 1983-04-15
JPH0259438B2 JPH0259438B2 (en) 1990-12-12

Family

ID=15771799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56163330A Granted JPS5863883A (en) 1981-10-13 1981-10-13 Electronic clock provided with recording function

Country Status (1)

Country Link
JP (1) JPS5863883A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005287288A (en) * 2004-03-03 2005-10-13 Mikuni Corp Stepping motor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005287288A (en) * 2004-03-03 2005-10-13 Mikuni Corp Stepping motor

Also Published As

Publication number Publication date
JPH0259438B2 (en) 1990-12-12

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