JPS5860865A - Picture recording system - Google Patents

Abstract

PURPOSE:To improve the operability of a picture recording system, by specifying a selective recording mode of a recording mechanism at a readout part. CONSTITUTION:A picture recording means 300 uses plural recording mechanisms for recording, and records data on a recording medium in plural recording modes. A picture recording means 100 is arranged separately from the means 300, and the means 100 and 300 are coupled together by a signal transmitting means 700. The means 100 selects a recording mechanism and a recording mode of the means 300 through the means 700. The means 700 uses an optical communication means to speed up communication and also to reproduce a picture signal securely.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image recording system having an image recording means and an image reading means arranged at a distance of lI from each other.

If the image reading section and the image recording section are separated and the image signal read by the reading section is supplied to the recording section via a predetermined transmission path for recording, high-speed communication is possible and the image A transmission method that reliably reproduces signals is desired.

Therefore, the inventor examined in detail the advantages and disadvantages of various pulse modulation methods, taking as an example the case of 'JII image transmission by spatial optical communication. Below are the results of □. 1) Regarding the 8/N ratio or C7N ratio, to increase the 87N ratio (signal/noise ratio) or C7N ratio (carrier/noise ratio), minimize the communication bandwidth as much as possible. It is desirable that A note on this point - a) FM requires twice the bandwidth as NRZ, but R
It is equivalent to Z.

b) MFM requires the same bandwidth as NRZ.

2) Freedom of installation location When separating the reading section and recording section, it is desirable to change the installation location as necessary. As a result, fluctuations in the communication signal strength (modulated light strength f) inevitably increase. (In the case of optical fiber, etc., there is almost no level fluctuation once installed, but FBS means that the installation location can be changed arbitrarily.) In the case of optical intensity modulation, this fluctuation in the communication signal strength is particularly Rise of playback pulse waveform.

This causes fluctuations in the fall timing, making synchronization of transmission lock difficult. In this regard, Toge FM, MFM
In this case, since timing information is always included during the l-bit or l-bit time, it is easy to synchronize.

b) NRZ, RZ method Teha "0" mar) f, r
/J If 11 times are repeated, timing information cannot be sent.

5) Regarding simplification of circuit configuration and frame synchronization, it is desirable that the circuit configuration be simple. For this purpose, it is best to immediately communicate the read N image signals without providing a 2-data storage means, etc. To do this, the period of 1 frame is equal to one scan in the direction perpendicular to the document feeding direction, In other words, it is preferable to set the amount for l main inspection. As a result, the time interval between frames becomes shorter. In this regard, a) NRZ and RZ require a pulse train for frame synchronization, a frame header called a so-called pre-angle. In principle, this is not necessary for FM and MIFM.

(Actually, a frame header is attached to ensure synchronization.) b) The number of bits of the l frame of the II image signal is, for example, 1721 bits or 20441 bits.

It is generally set to a large value. In NRZ and RZ, there is a strong possibility that synchronization will occur in the frame and the image will be distorted.

4) Necessity of bit synchronization in ML image signal transmission Even if glass noise is mixed into the iI image signal during both image signal transmission, its influence can be reduced to a certain extent. On the other hand, loss of synchronization is directly linked to the phenomenon of so-called picture movement, and from this point of view, focus synchronization information is essential in image transmission. In this respect, NfLZ and RZ are unsuitable for image transmission.

5) Regarding real-time transmission The image signal read by the reading mechanism is transmitted in real-time. In other words, it is preferable to transmit the image signal immediately from the viewpoint of simplifying the circuit configuration and other aspects. By the way, when this method is adopted, since signal retransmission is impossible, it is necessary to use a transmission method that does not cause local errors.

In this respect, the FM method is preferable, and in the case of the MFM method, the demodulation circuit needs to be devised.

6) Regarding the meaning of reducing redundant bits as much as possible, error recovery codes, synchronization bits, etc. are redundant bits when viewed from the image signal. Addition of such an X-length bit widens the required frequency band and leads to the complexity of the circuit.

Therefore, choosing a transmission method that does not require the addition of redundant bits is advantageous in various respects.

In addition, the recording unit may have multiple recording mechanisms,
If the recording mechanism can record in various recording modes (for example, a mode in which a red original is recorded in black), it is desirable that these modes can be selected from the reading section.

The present invention has been made based on the results of such studies, and its purpose is to provide an image recording system that can meet the various demands described above.

Hereinafter, the present invention will be described in detail based on the drawings.

JI! The figure shows an example of an image transmission device to which the present invention is applied, in which reference numeral 100 denotes a distributed reading section, which reads an image of a sheet-like original using a one-dimensional solid-state image sensor.

For example, COD? It is read by an in-image sensor and converted into time-series image data TDA. This image data VD
A'& quantize this image data VD and Ki@g
The reading unit t reads the instruction data CD for performing the operation 3oo.
The signal is supplied to the inter-liquid circuit in the OA, and a pulse frequency signal II (or MFM) is generated using a predetermined clock signal and these signals (hereinafter collectively referred to as "data signal DB"). The output signal of the pulse frequency modulation circuit, that is, the pulse FM signal FM8, is supplied to the light transmitting section 100, and as shown in FIG. drive

Referring to FIG. λ, the light emitted from the light emitting element 10/ is condensed by a lens jO2 to form a light beam Lt, and this light beam Ltg is supplied to a light receiving unit 700 attached to a ceiling or the like.

The light receiving element 7Q/, for example, an avalanche photodiode, built in the light receiving section 700 converts the strength of the light beam Lt into an electrical signal and generates the above-mentioned pulsed IFM signal FM.
Reproduce 8. This signal F is transmitted via the synchronous cableter 00.
The MS is supplied to the recording unit JOO. The recording unit 300 extracts image command data CD from the supplied pulse IFM signal FM8. The recording section 300 performs a predetermined image recording operation based on each of these signals.

FIG. 3 shows an example of the reading mechanism of the reading unit 100, where 10/ is a sheet-like original, and 102 and 103 are originals 10.
/ toa is a platen provided in the document feeding path, and this platen i
One image of the lower surface of the document 10/ passing through the position AV is sequentially read. IO! Hold down the original 10/ and focus (
This is a document feed guide that functions to form an image. /It
and 107 are document position detection means for detecting the paper edge of the original @ 10/, which detects the point in time when the paper edge of the fed document 10/ obstructs the progress of light from the light emitting element 106 to the light receiving element 107. do. This detection signal is used to control the recording section SOO.

Reference numeral 10r denotes a rod-shaped light source for document illumination, such as a halogen lamp, which illuminates the reading position A of the platen from below. 1
0P is a folding error, which folds back the image light Lr reflected by the original 10/ passing through the reading position A as shown in the figure. ito is an imaging lens.

It functions to form an image of the image light Lr on the light receiving surface of the COD line image sensor ///. This COD line image sensor /// converts the imaged image light Lr into time-series image data VDA of a predetermined number of bits.
30/B is a first recording mechanism, and 30/B is a second recording mechanism. In this embodiment, the λ recording mechanisms 30/A and 3o
tBcD III construction is exactly the same, only the code "301" which refers to the entire recording mechanism is WJ! With the code rAJ or "BJtt" to distinguish the recording machine and the second recording mechanism,
Codes indicating details of the recording mechanism are (-The same code is used for the misaligned recording mechanism.

The i/recording mechanism 30/ and the second recording mechanism 10/B each include λ recording heads, for example inkjet heads 302 and 303. Each inkjet head is a full-line inkjet head in which a plurality of recording elements are arranged in a straight line in a direction perpendicular to the drawing shown in Figure 1, and is driven according to image data TDA from the COD line image sensor //. Make a record. In this example,
The 30 inkjet heads perform black normal mode recording of 14 donts/yen, and the 30 inkjet heads
3 is r dot/wi.

shall be recorded in red normal mode. Each recording machine @! 0/A and 30/B are vertically stacked in two stages by a support (not shown).

30 is a recording paper storage cassette, 30! is the recording paper stored in this cassette, 306 is paper feed row 2.107
301 is a guide plate, 301 is a registration straw yS3ot is a first conveyance roller, 210 is a platen having a large number of pores,
J// is a fan, 31λ is a second transport roller, J/J is a suspension roller, 3/u is a transport belt, 31j is a paper discharge tray, and 3/6 and 3/7 are ink tanks.

Next, the recording operation in the above mechanism will be explained, except that the inkjet heads 30 and 303 are selectively used by signals sent from the reading section 100. Since the operations are exactly the same, only the recording mechanism 10/mu will be described here.

The recording paper 30j stored in the paper cassette 304A is fed along the guide plate 307 by the rotation of the paper feed row 2304 to the registration row 230r, which has stopped rotating, and forms an appropriate looseness. Next, as the registration roller 30r rotates, the recording paper is rotated by the registration roller 30r.
01 and the first conveyance roller JOde, and is conveyed toward the inkjet heads 302 and 303. At this time, on the same side as the inkjet head 302 and the JOJ, a platen 310 having pores and a fan J/
/ is distributed, and the rotation of the fan 31/ blows air to T7j in the figure.

Therefore, the recording paper 30 that has passed through the first conveyance roller 23Q
1 is being sucked by fan J//, 12 ten 310
The upper part is transferred to the second transport row 23,120,000.

During this transfer process, the inkjet head 302 or 3
0! CCD line image sensor supplied to //f
Recording is performed by the drive circuit according to the image data VD from :. After recording, the leading edge of the recording paper JOrO is transferred to the second conveying roller 231, and then the leading edge of the recording paper JOrO is transferred to the second conveying roller 231.
2 and conveyor belt iiiu, the recording paper III is discharged onto the paper discharge tray 30.

FIG. 1 shows the control circuit of the reading section 100 and the light transmitting section soo.
t#, where /// is the CCD line image centimeter described above, and the drive circuit //J is controlled by the timing signal from the tizing control circuit l/co.
, and generates time-series image data VDA. //$ is a quantization circuit that quantizes the image data TDA. Transmission control circuit for quantized image signal VD //
supply to j. //6 is the central processing unit, and the memory consists of random access memory, read-only memory, etc. //
The operation of each part of the reading section 100 is controlled according to the control program written in the reading section 7. tie is a boat for controlling the reading mechanism, and a flashing signal to halogen rung/(M,
Sends a drive signal to the brake and clutch for rotating or stopping the feed roller 102 and tO3,
Detection signals from document position detection devices 104 and 107 are received. /l is a console input port which receives a recording unit control signal from a control console disposed on the cover /20 on the top surface of the percentage reading unit 100. Control console/2/ Select recording mechanism and recording color≠
It has two digital buttons /2/1 to /2/d, a recording start button /2/@, and a cancel button /fi. When the button /2/& is pressed, the transmitted image data (2) is supplied to the black inkjet head 30 of the seventh recording mechanism 30/A, and recording is performed using black ink. The following table shows the relationship between each button, recording mechanism, and recording color.

Note that the recording mode is not limited to this example.

The following modes can be used:

(1) Enlargement/reduction mode.

(■) A recording mode that specifies an area on a document using a predetermined color and performs recording processing inside and outside that area. Regarding the configuration example of this mode, one applicant previously filed a patent application filed in 1987-10.
It is described in detail in No. 04At, etc.

/22 is a command data boat, and various command data CD'% for controlling the recording operation of the recording mechanisms 30/A and 30/B are supplied to the transmission control circuit llj. , sends a transmission control signal to the transmission control circuit //j to control its operation. The transmission control circuit its performs predetermined processing on the image data VD supplied from the quantization circuit 114A or the command data CD supplied from the command data boat /lλ according to the transmission control signal and timing signal 1. , its output signal,
(Data signal) D8 is supplied to the frequency modulation circuit lkoda.

In this embodiment, in order to distinguish between the image data VD and the command data CD, an image header VH with different bit contents, which also serves as a synchronization signal V, is placed at the beginning of the image data VD or command data CD, as shown in the figure. Alternatively, an instruction data header CH is added. The data signal DS with these headers added is supplied to the pulse frequency modulation circuit/24c. This pulse FM circuit ix pulse-frequency modulates the clock signal CKM supplied from the timing control circuit //2 using the supplied data signal D8.

Modulation circuit/J4C output FMS to LED driving amplifier/
23, and its output drives a light emitting diode 10/'%' of light transmission @100. light emitting diode ro
As mentioned above, the output light of t is focused by the lens jO to form the light beam Lt, and this beam Lt&light receiving B700
supply to.

Figure 7 shows the control circuit 1 of the recording section 300 and the light receiving section O.
Q, and the light beam Lt from the light transmitting section 200 described above is 7.
It is converted into an electrical signal, ie, a pulse signal FMS, by a photodiode 70/. 702 is this signal FM
8, and its output signal is supplied to the narrowband amplifier 3λ0 of the recording section 300 via the coaxial cableter 00 mentioned above. The output signal of the narrowband amplifier riI3 is supplied to the demodulation circuit 12/.

The demodulation circuit 3 extracts a demodulated clock signal CKD and a demodulated data signal D8 from the supplied signal PMS. Demodulated clock signal CKD9I: Timing signal generation circuit J
Supply here. This circuit 3 generates a write control clock signal CIc%V. This signal CK%V is used to control the writing timing of the recording mechanism 30/k or 30/B. The demodulated data signal D8 is supplied to the U7A/parallel conversion (B) path 3-3. This conversion circuit 3
23 converts the demodulated data signal D8, which is a serial (time series) pulse signal, into a 2-barrel (parallel) pulse 2 signal PS, which is sent to the image header flower detection circuit 32,
Instruction header CH detection circuit J2r and latte circuit J21
．． When the image header detection circuit 32 detects the image header VH shown in FIG. 4, it outputs the image header detection signal vH8. Gate circuit jJ7 K is supplied to open this gate J27, and the image data VD at that time is recorded in the recording mechanism 30/M or 30/B.
directly or indirectly through the image memory 3o/M'l that temporarily stores image data. When the instruction header detection circuit 3j detects the instruction header CH shown in FIG. 6, it generates an instruction header detection signal CH8. This signal CH8 is supplied to delay circuit 3, delayed by a predetermined number of bits, and supplied to latch circuit 3 as a latch signal.

As a result, the command data signal CDI+-? Tsuchi. This command data signal CD specifies an interrupt request, start timing, recording mechanism 30/71/B to be used, recording color, etc., and the recording mechanism is controlled according to this signal CD. Image header detection circuit J Koda and instruction header detection circuit! 21 also supplies a detection signal to the dead time generation circuit 330 via the OR circuit 3J at the time when each header is detected. Dead time generating circuit JJO generates dead time signal DT8 in response to this detection signal.

The respective header detection circuits 324A and ! This dead time signal D'I'8 is supplied to 21. While this dead time signal DT8 is being supplied, the respective Helada detection circuits 3 and 3 stop operating for 7 times.

As a result, if there is an image header ■ in the image data VD,
Alternatively, even if there is a part with the same bit configuration as the instruction header CH, this is prevented from being detected as a header part or CB.

No. rFl! J is an example of the circuit configuration of the pulse FM circuit l in the reading unit 100, where /30 is a positive edge detection circuit, /J/ is a negative edge detection circuit, and /32 is a latch circuit. The supplied clock signal CKM is supplied to these edge detection circuits /JO and /J/, and also to the latch signal input terminal of the latch circuit 13λ. Transmission control circuit ll! The data signal Da (see the figure) supplied from the latch circuit/J is supplied to the data input terminal of the latch circuit/32.The latch circuit/32 doubles this data signal DS in accordance with the positive edge of the clock signal CKM. . The negative nip detection pulse NIP of the negative etch detection circuit /J/ and the output signal LD of the latch circuit /JJ are supplied to an AND circuit /77, and the output As and the positive edge detection pulse PIF of the positive edge detection circuit /30 are connected to an OR circuit. /3+1. The output 'rp of OR circuit 13μ is 2
It is supplied as a toggle pulse to the decimal counting circuit/3j. Output of co-adc counting circuit/31, that is, pulse FM signal FM8
is supplied to the LID drive amplifier l, as described above.

The operation of this modulation port 1/2'l is as follows.

First, if the data signal DS is in the "O" state, the output LD of the latch circuit 13-2 also maintains the "Q" state, and the output A8 of the AND circuit /33 also maintains the rOJ state. Therefore, the output TP of the OR circuit 13≠ becomes r/J only during the period when the positive edge detection circuit /30 detects the positive edge of the clock pulse CKM and outputs the positive edge detection pulse PIP'li. The level of the output FMS of the co-adc counting circuit 13j is inverted every time the pulse TP arrives from the OR circuit /Ju.

That is, when the data signal D8 is "O", the output FMS of the co-advanced counting circuit 13j is equal to the time interval of the positive edge PE of the clock pulse CKM (period TC of the clock pulse CKH).
KM time interval).

On the other hand, assume that the data signal DS becomes r/J at a certain point in time, as shown in FIG. In addition, "?" in the waveform diagram
” indicates that the contents of the subsequent data signal DS are unknown. The latte circuit /32 lattes this "l" signal in accordance with the positive edge PE of the drop pulse CKM, and its output LD becomes "l". Next, when the negative edge (2) of the clock signal CKM arrives, the negative etch detection circuit/
J/ generates a negative edge detection pulse NIP. Therefore,
During the period when the detection pulse NIP is r/J, the output A8 of the AND circuit/33 becomes r/J, and this output As inverts the repe/L/ of the output FMS of the co-adc counting circuit/35.

That is, when the data signal DS is r/J, the output FM8 of the co-adc counting circuit is inverted not only when the positive edge PI of the clock pulse CKM arrives, but also when the negative edge PI arrives, and the time interval of two inversions is is half of the period TCKM of the clock pulse CKM.

Therefore, on the rir3BJOO side, the data signal D8 can be reproduced by detecting the difference in the time interval of level inversion of the pulse FM signal FM8.

FIG. 10 shows an example of the circuit configuration of the demodulation circuit 32/ of the recording section SOO. Here, 310 is an internal clock signal generation circuit, which generates an internal clock pulse CKI.

In this embodiment, this internal clock pulse CKI.

The period TCKI is the pulse FM signal of the reading section 100 mentioned above/
The period of the clock signal CKM supplied to the clock signal CKM is set to t/ls of TCKM. The internal clock pulse CKI is supplied to the edge detection circuit 33 and the counting circuit 33. A pulse FM signal FMS is supplied to the edge detection circuit JJ/. Etch detection circuit JJ
/ generates a nip detection pulse IDP in synchronization with the internal clock pulse CKI when the positive and negative edges of the signal FMS arrive. This pulse EDP is supplied to AND circuits 3Jt and 337. Counting circuit! 32 represents the number of internal clock pulses CKI V jff. The count value CO is supplied to the timing generation circuit 333 in the form of a D parallel co-decimal code.Timing generation circuit 333
generates each signal according to the content of this count value CO.

The contents and destination of each signal are shown in the table below.

The output pulse A8P of the AND circuit 334 is supplied to the set terminal S of the RSS free lag frog 33. AND circuit 3
17 output pulses A8C are supplied to the reset terminal a of the counting circuit 332. Output signal y of flip-flop JJj
yO is supplied to the signal input terminal of the latch circuit.

The operation of this demodulation circuit 3 will be explained with reference to the time chart shown in FIG. First, the edge detection circuit 33/
When the data signal D8 in the read M/DO is "l", the pulse FM signal FM8 supplied to the FM signal has a pulse period Tcm of the modulating clock signal CKM (see the diagram), as shown in FIG. It is reversed at a period of approximately %. Here, the abbreviations are used because the pulse FM signal FMS is distorted depending on the characteristics of each circuit element in the process of being transmitted from the reading section 100 to the recording section 300, and the time interval of its reversal is not necessarily That is, the time interval from a certain positive etch PE to the next negative edge NIC may not match the time interval from the noble edge Nl to the next positive etch P'M. This also applies to the time interval between the positive etch PE and the negative edge Nl when the data signal D8 is "O".

Taking this into consideration, in the waveform diagram of the pulse FM signal FMS in Fig. 1, the point in time at which the next negative edge NEJ is located is shown with diagonal lines, based on the negative edge IJE/ at a certain point in time. Expressed within a predetermined range. In addition, WS//
In the other signal waveform diagrams in the figure, when the point in time at which the navel edge, etc. is located corresponds to the point in time at which the edge of the pulse FM signal FMS is located, the time point at which it is located is similarly located within a certain range with diagonal lines. express it.

When the pulse FM signal FMIII is supplied to the edge detection circuit 33/, the edge detection circuit 33/ of
At the time of the arrival of the positive and negative edges of
Generate P. At this time, since the level of the etch selection signal 1g is "l", the output ABC of the AND circuit 337 becomes rlJ.

Counting circuit J2 is reset and this counting circuit JJJ
The count value CO becomes "0".

When the count value CO reaches rl, the timing generation circuit 333
A latch pulse LP is supplied to the latch circuit 33 from
This latch circuit 3314 receives the signal 5yrQ'y? which is supplied to the data input terminal at that time. Tweet. In addition,
At this time, the output signal FIPQ of the FRI 717971 circuit 331 that is latched is the data signal D8 that is 7 bits earlier.
．． That is, the data signal Da ri J expressed in one cycle from the negative edge NE1 of the signal FMs to Nleλ,
The content of the data signal D8 for l bits ago is "V*", but it is unknown whether the data signal D8 for l bits before is "0" or rlJ, so in Fig. 1, the content is "?".
” (1).

After being reset, the counting circuit 3J counts the internal clock pulse CKI and supplies the counted value CO to the timing generation circuit 333. As described above, the timing generation circuit 333 generates each signal corresponding to the count value CO. That is, first, when the count value reaches rlJ, a reset pulse R is applied to the reset terminal R of the free lag flop 3Jj.
Supply 8F.

As a result, the output FF (
7 becomes rQJ. Also, the count value CO changes from “!” to “l”.
During this period, the etch selection signal 'BS becomes "O". 1st
/In the example shown in the figure, the pulse FM signal FM8 is inverted during this period in response to the data signal D8 being rlJ, and the edge detection circuit! 3/ detects the positive or negative etch (Pl in FIG. 1/) and generates an edge detection pulse IDP.

As mentioned above, the trap and edge selection signal B8 is inverted and supplied to the A and D circuits 33B. Therefore, during the period when the inverted signal of the etch selection signal I8 is rlJ, that is, during the period when the count value is from rjJ to "/ko",
When the edge detection pulse 'EDP is supplied to this AND circuit 334, its output ASP becomes rlJ. As a result, R8 flip-flop IJJj is set, and its output F'F0 becomes rlJ.

When the count value CO exceeds "12", the etch selection signal IS
returns to "l" again. After this, pulse FM signal signal FM
When there is an inversion of 8, the edge detection circuit 37/ generates the edge detection pulse EDP again. At that point, the etch selection signal E8 is rlJ, so the previous negative edge N
As in the case of l/, both inputs of the AND circuit 1370 are rl
J, therefore its output AsC becomes r/J, and the counting circuit 33 restarts counting from r7J. This count value C
0 is "OJ", the latch circuit 33da outputs the value "l" of the output yyO of the free lag flop 3Jj, that is, the positive edge between the negative edge Nl/ of the signal FMS shown in FIG. Latch the value r/J of data signal D8 as represented by the presence of P1.

When the data signal Da to be transmitted is "0", the edge selection signal B8 is "0", that is, during the period when the inverted signal r/J is supplied to the AND circuit Jj&, the pulse There is no level inversion of the FM signal FM8, so the edge detection pulse IDP is not supplied to the AND circuit 33&. Therefore, the output FFQ of the flip-flop 133B remains "0", and the value r of this output FFO
When the next edge Nl or PR arrives, l is doubled by the latch circuit 3J, and the value rQJ of the data signal D8 is output.

In addition, in the example shown in Fig. 1, the data signal D to be transmitted is
When Br/J, the pulse FM signal 7M8 reversed its level from "negative edge" to "positive etch" to "negative nip", but in the completely opposite form, the data signal D
Of course, there is a level inversion representing B "/J.

The output of the demodulation circuit 32/, that is, the demodulated data DB and the demodulated clock signal CKD, are supplied to the serial-to-parallel conversion circuit 323 and the timing signal generation circuit 32, as shown in FIG. 7, and recording is performed based on these signals. An action is taken. In this case, the demodulated clock signal CkD generated by the demodulating circuit 3 is completely synchronized with the transmitted pulse length signal VMS. Therefore, even if there is distortion in the time interval between the edge and the nip as described above, by operating the microprocessor, each recording mechanism 30/etc., based on this demodulation clock pulse CKD, the data can be processed. The signal D8 can be reproduced correctly.

Figure @/2 shows the procedure of the reading section in the image recording system of the present invention. First, a power-on reset is performed in step 81, and various devices are initialized in step S2. If the start button is pressed in step 8J, the state of the recording mode button is read in step B4c, and feeding of the document is started in step 8j.

If the edges of the document are detected in step S6, step S7
The document feed is stopped in step sr, the document illumination light source is turned on in step sr, and the document feed is resumed in step s.

Next, the hand If B10 opens a communication channel, and in step 811 the recording mode is transmitted to the recording unit SOO. Furthermore,
A copy command is transmitted in step 81λ, and transmission of image data is started in step 8/J. When the document reading is completed, in step 8/u, the light is turned off, the communication channel is closed, and step Sl! At , the document is ejected and feeding is stopped.

As described above, in the present invention, the selection recording mode of the recording mechanism can be designated from the reading section, so the operability of this type of image recording system is greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram showing an example of the image recording system of the present invention;
Figure 2 is a diagram showing an example of data transmission through space, mushrooms, and communication; IJgJ diagram is an internal configuration diagram showing an example of the configuration of the reading section; Figure @4' is an internal configuration diagram showing an example of the configuration of the recording section. ,
Figure 5 is a block diagram showing an example of the configuration of the control circuit and light transmitting unit of the reading unit, Figure 6 is a diagram showing an example of the bit configuration of the data signal, and Figure 7 is the control circuit and light receiving unit of the recording unit. A block diagram showing an example of the configuration of the part, the second figure is the Pal 77M.
2 is a block diagram showing an example of the circuit; FIG. 2 is a time chart of the circuit shown in FIG. 1; FIG. 10 is a block diagram showing an example of the pulse demodulation circuit; FIG. The figure is a flowchart showing the procedure of the reading section of the present invention. Lt...Light beam, Lr...Reflected light from the original, VDA...Image data read by CCD! ...-Blowing direction, VD...quantized image data, CD...command data, D8...data signal (general term for image data and command data). 7M8...Pal 77M circuit output (pulse movement signal),
WCK...Pa writing control, B...Document feed direction, A...Document reading position, CKD...
Demodulated clock signal, CKW--Write control clock, ps--Parallel pulse signal, CKM--Modulation clock signal, TCIiM--Clock signal period, ■--Image header, CH--Instruction header. "vHs-...Image header detection signal, CBS...Instruction header detection signal, DT8...Dead time signal, NIP...Negative edge detection pulse, LD...Latch circuit output signal, R8... AND circuit output, PIP'...positive etch detection pulse, TP-...OR circuit output, PI...positive edge, NB...negative edge, TSf, CKI...internal clock pulse, IDP...・Edge detection pulse, ms...
・Etch selection signal, AsC...AND circuit output pulse, R8F...Flip-flop preset pulse, LP.
...Latch pulse, IPFO...R8 flip-flop output, CO...count value, A8
F...AND circuit output pulse. /DO-・Reading unit 10/... Sheet-like original, 102.103
... Feeding roller, 104k... Platen,
10j... Document feeding guide, 706... Light emitting element, 107... Light receiving element. 101... Rod-shaped light source, 109... Reflection mirror, /10... Imaging lens,
1tit...CCD line image sensor, //
Co...timing control circuit, //J...CCD drive circuit, //4A...quantization circuit, 112...transmission control circuit, //1...
・CPtJ. //7...Memory, //r...Reading mechanism control boat, //De...Console input board, Coco0...Reading unit top cover, /J/...Control console, 1/a % f
...button, l here...command data boat, /23...transmission control boat, 12-...7M circuit, 12!・-LID driving amplifier, /30...Positive edge detection circuit, /J/...Negative edge detection circuit, 13
．． 2...Latch circuit, 133...AND circuit, 13≠...OR circuit, 13j...co-adc counting circuit. 300-... Recording unit jO/A-... First recording mechanism, 30/fJ... No. 1 recording mechanism, 30/M... Image memory, 30... Inkjet head (black), 303・・・
・Inkjet head (red), 30μ... Recording paper storage cassette 1, IOj? -・-Recording paper, JOA...
Paper feed o-'). 307--Guide plate, 3Ot...Registration row 2.30--First conveyance roller, 310-
...Platen, J//...Fan, 31 pieces...2nd
transport row 2), J/J...suspended row-y, J
/4A...Transport belt, Jts medium output tray, 3/
la, J/7... Ink tank, 3 pieces 0... Narrow band amplifier, 321... Demodulation circuit, 3 pieces λ... Timing signal generation circuit, 323... Serial to parallel conversion circuit, 32 Hiro -・Image header detection circuit, J2! ---Command header detection circuit, 326---2
Tsute circuit, 3 cores...-gate circuit, 3 cores ・
...Delay circuit% 32ri...OR circuit, 330
...dead time generation circuit, JJ/-...edge detection circuit, 33co...counting circuit, 333...timing control circuit, 334g...latch circuit, 33j...flip-flop. 336, 337...AND circuit, zro-...internal clock generation circuit. 200...Light sending part jO/...Light emitting element, ! 102-・Lens. 700... Light receiving section 70/...-light receiving element. riOQ...Coaxial cable. Patent applicant: Canon Co., Ltd.

Claims (1)

[Claims] 1) An image recording means capable of recording with IN number of recording mechanisms and/or recording on a recording medium in two or more recording modes, and an image recording means arranged 11M apart from the image recording means. It has an image reading means, and a signal transmission means for transmitting signals between the image reading means and the image recording means, and the selection and/or recording mechanism is selected from the reading means via the signal transmission means. Alternatively, a double-image recording system characterized in that the recording mode is selected. 2. The image recording system according to claim 7, wherein the recording mode is an enlargement mode. An image recording system comprising a reduction mode and an area specification mode. 3) The image recording system according to claim 1, wherein the signal transmission means is based on an optical communication method.