JPS5860487A - Storage device - Google Patents

Abstract

PURPOSE:To simplify a sense circuit and to read memory cells at a high speed by using readout transistors (TR) which perform current switching operation between memory cells, and providing a common sense circuit to plural digit lines. CONSTITUTION:When a memory cell M11 among memory cells M11-M22 in (2X2) matrix arrays is selected, a TR Qy1 for digit line selection is turned off, and TRs QR11 and QR12 for readout signal detection are turned on to switch current paths. Then, constant currents from constant current sources J11 and J12 flow to the cell M11, and information in the cell M11 is read out through the TRs QR11 and QR12 and a differential amplifier DIFA forming a common sense circuit. Other digit line couples are the same, and one sense circuit is provided in common to plural digit lines to simplify the sense circuits; and current paths are switched by two TRs which operate in parallel to perform high-speed readout operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device suitable for a bipolar high-speed semiconductor memory circuit.

A memory cell having a plurality of emitters, that is, a combination of two multi-emitter transistors, is suitable as a memory cell for a large-capacity semiconductor storage device because it occupies a small area when integrated into an integrated circuit.
An example of a memory cell using this is shown in FIG.

In the figure, a memory cell M includes multi-emitter transistors Ql and Q2 with two emitters, and the collectors of each transistor Ql and Q2 pass through load resistors R1 and R2, respectively, and are commonly connected to a power source through a resistor R3. The collectors of the transistors Ql and Q2 are each cross-connected to the base of the other, and the first emitters of each transistor are commonly connected to the emitter drive terminal E1 for selecting a memory cell. Each second emitter is connected to write and read amplifiers 81 and 82, which will be described later.

In this way, a flip-flop circuit as one memory cell is formed. Note that the transistor Ql.

Each second emitter of Q2 is commonly connected to the second emitters of transistors constituting a plurality of other memory cells, but is omitted in FIG. 1 for simplicity.

Write/read amplifiers 81, 82 each include transistors Q3, Q4 and Q5 . . . , which constitute a differential amplifier. The emitters of Q3 and Q4 and Q5 and Q6 are commonly connected to the second transistors Q1 and Q2, respectively.
It is connected to the input terminal 1 through resistors R5 and fL7, which are connected to the emitter and defines the read current or write current of the memory cell M, and to the transistor Q3,
The collector of Q5 is connected to output terminals TI and T2, respectively, and is grounded via resistors R4 and l'L6.

Further, a reference voltage (2) is applied to the bases of transistors Q3 and Q5, and transistors Q4. Input signals ■wo and vwl for information writing are added to the et base of Q6.

Next, in the selection 1 of 0 memory cell M whose operation will be explained, the voltage Vxo of the collector power supply terminal C1 is kept constant, and the voltage vx1 of the emitter drive terminal E1 is set to a low level when not selected, and set to a high level when selected. It is carried out by In this case, it is assumed that transistor Q1 is cut off, Q2 is in a conductive state, and each collector voltage is . ,,Vo2
0 memory cell M is in the unselected state, that is, terminal E
When the emitter drive voltage X1 applied to the transistor Q1 is at a low level, a constant current flows through the first emitter of the transistor Q2.
sT: is flowing, but no current flows through the second emitter. Therefore, the emitter resistance R of the write/read amplifier S2
7 flows through the resistor R7 rather than the transistor Q5, so the output voltage V of the transistor Q5. ul is V (ill l -v.c -α・R,6-I.

However, α: Only a low voltage shown by the common base current amplification factor of the transistor appears. Note that the resistance R5, R
Each operating current flowing through the circuit 7 is set to the same current value ■8.

Next, when the memory cell M is in the selected state, that is, the emitter drive voltage VX1 of the terminal E1 is at a high level, the transistor Q
A current 8 flows through the second emitter of the input terminal '1'2, which flows into the emitter resistor R7 of the input/readout amplifier S2, so that the current flowing through the collector resistor R6 decreases, and the current flows through the output terminal '1'2.
The voltage at the output terminal TI of the input/read amplifier S1 increases by 1, and the information 1 is read out. Since the transistor Q1 is in the cutoff state, the voltage at the output terminal TI of the input/read amplifier S1 is the emitter drive voltage rf.
Regardless of the change in the j pressure vx1, it is at a low level, and information of "0" is read out.

Note that X added to the first emitters of transistors Ql and Q2
The magnitude of the high level of the address voltage Vx is the reference voltage V
The voltage V at the collector of transistor Q1 with respect to r a f. l is high, l・Collector voltage of transistor Q2■
c2 is chosen to be low.

In addition, when the memory cell M is in the selected state as in the case of reading 2, the base of the transistor Q4, Q6 is connected to the collector of the memory cell at a level higher than the high level of the d voltage or the reference if. , pressure V r e I
By adding signals of the following levels, information of "]" or 0 is written.

In addition, in the above explanation, when selecting, emitter drive/vore pressure vx1
It was assumed that only changes from low level to high level,
It is known that depending on the type of memory cell, it is effective to change not only the emitter drive voltage but also the collector power supply voltage Vxo from a low level to a high level. Needless to say, the present invention can also be applied to memory cells using this method.

In this method, the reading transistors Q3 and Q5 form an emitter-coupled current switching circuit with the cell transistors Q2 and Ql, so that cell information can be read out at high speed, and the current switching target is Read current ■8
Therefore, there is an advantage that no separate current source is required. However, when a large number of memory cells are arranged in a matrix, it is desirable to provide a common digit line for all digit lines.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a memory device in which transistors in a memory cell and transistors in a sense circuit perform current switching operations, and in which the sense circuit is commonly provided to a plurality of digit lines.

Hereinafter, a case where the present invention is applied to a memory cell matrix in which m×n memory cells M and write/read amplifiers S1 and 82 shown in FIG. 1 are provided will be described with reference to FIG. 2. In this case, for the sake of simplicity, the case where m = n = 2 will be described.

Mll, M12. M21. In the four memory cells M22, the g2 emitter of each transistor constituting the flip-flop circuit connects to two pairs of digit lines DLll.
DLl□1I) are connected to L21 and DL2□ respectively,
Each collector is connected to a collector power supply or a collector drive line (first word line) through a load resistor, and voltages Vx1o and Vx2° are applied thereto, and each first emitter is connected to an emitter drive line (second word line). Then, a pressure of 1 x 11 + x 2 is applied.

■ Operating current for reading or writing. Current source J11. J12. J21. J22 are the digit lines DL□1. D0.1□l I) L 21 r DL
22. Read information detection transistor QR
Each emitter of I l l QILI□+ QR21HQB2□ is connected to the above-mentioned digit line, and each collector is connected to each digit line on the "0" side and "1" side, and the respective collector resistors R8 and f't9 are connected to each other. It is connected to ground through the circuit and led to the differential amplifier DIFA.

Write control signal 2. ■I. is the transistor Qw 1,
+ QW12 r QW21 + Added to QW22.

Further, the transistor Q yl + Qy2 receives each digit line (Y line) selection signal vY1. ■By increasing the potential of the unselected digit line pair in accordance with Y2, the second emitter of the transistor constituting the flip-flop circuit in all memory cells connected to that digit line pair is cut off, and the digit line pair is The current of the current source connected to the line pair is read from the read information detection transistor Q R1□I
QRI□r Q B21 + QR2□ acts to prevent it from flowing.

That is, the memory cell to be read (for example Mll)
For selection of collector drive line voltage x1o, x
11 is selected. For example, while keeping x1 constant, the voltage x1o is set to a high level.

Furthermore, the voltage vY□ is selectively set to a low level.

The voltage ``Y2'' for other digital nodes 1 remains at a high level.

The high level of this voltage vY1 is the read transistor QR.
1□～Q,. Base of 2' ridge pressure ■. , or higher than either of the base voltages of the two multi-emitter transistors of the selected memory cell ~111. Also, the low level of voltage vY1 is set low for any of these base voltages.

As a result, digit line pair 1〕1□1　 with 1 note of unlucky.

Among the bases of the various transistors connected to DL2□, the base voltage of transistor QY2 becomes the highest, and current source J21. All the bladder current from J22 flows to the transistor QY□, but the readout transistor QI
L□1. It does not flow to QIL□2.

Therefore, these −It combinations reduce the resistance bCl(,8
, l'L 9 voltage does not change. On the other hand b; “III”
<Sa) 1) connected to each of the digit lines DX and 10.1) L2 'IIf, the pressure V r a f becomes the highest. Therefore, the read current 8 from sources Jll and J12 is directed to either of these transistors by current switching operation. That is, for example, read current IPL from current source Jll flows to memory cell Mll, and current source J12
The read current from ■□ is the read transistor Q R1□
, or current from current source Jll flows through transistor QR41, and 'jtA from current source J12 flows through transistor QR41.
I, flows to memory cell Mll. Therefore, the resistance R
, 8, and R9, a read current flows through one of them, which is determined by the storage contents of the memory cell Mll. Therefore, the differential amplifier DIF'A resistors R8, R9 and each read transistor Q
Since it is connected to the connection point of RI 1 to QR2□,
Different voltages are output depending on the read contents of the memory cell. In this way, when the read current ① of each digit line is not selected, it flows through the transistor Qyl+QY2, so it does not affect the voltage of the commonly provided resistor R8゜R9, and furthermore, this transistor Qyl+
Since Qy2 and the read transistors QR1 and QR□2 form a current switching circuit, the selection of the digit line can be switched at high speed.

In the memory circuit shown in FIG. 2 above, if the power consumption due to the operating current of the memory is P and r, then PT = 2n''
a' l VBm l, and the drawback is that the PT is large. That is, power consumption increases in proportion to the number of memory cell rows n, which poses a major obstacle to increasing the density of memory cells by integrating them. Also, write control signal ■7□, vw
.

is the transistor QWII I Q, WI2 + QW
21 + Since it is applied directly to the digit line via QW22 and the digit and - potentials fluctuate due to the digit line selection signal, the recovery time for the digit line's acid pressure becomes long, and changes in the digit line segment occur. This has drawbacks such as noise to the memory cells and an increase in the required miscellaneous sweat margin of the memory cells.

FIG. 3 shows an embodiment of the present invention with reduced consumption power,
If the operating current ■1 is supplied, the current source is set as one set for a plurality of digit line pairs, and the supply of the operating current to each digit line is performed using the digino l [I (Y line) selection signal ■Y1. ■7゛8゛Qy1 whose base potential is controlled by 7゜
1r QY+2 + QY21 +QY2□ and the reference transistor Q B s write signal ■wo to which the reference voltage V r e f 2 is applied to its base.

Write control transistor Q to which 4w1 is applied to the base
Switching is performed by a multi-input current switching circuit formed by WO+QW+. Note that the write signals Vwo, V
It is also possible to omit the reference transistor QR by making the low level of , , equal to the reference voltage V r 6 f 2 . Also, the read signal detection transistor Q R
11l QR12+ QR2+ 1 QR2□ is the same as that in FIG. 2 above.

When reading a memory cell, for example Mll, the pressure xIo
It is the same as in Fig. 2 to set x1□ to a high level and keep x1□ at a low level.
y□ is unnecessary and the high level selection signal ■Y1 is a current switching transistor Qyll.

Apply to QY12. As a result, the transistor of memory cell Mll and the read transistor QR□1.

Current switching operation is performed between QR1□. As a result, memory cell Ml of transistor QRIIIQIL+□
Only one of the resistors I'L8, I'L, and 9 is turned on, and a read current (2) flows through one of the resistors I'L8, I'L, and 9. On the other hand, since no read current flows through the unselected digits +-S, the current flows through one of the resistors 1 and 8 degrees R9 depending on the stored information of the memory cell read out.
8 flows, and the detection output V o is detected by the differential amplifier D1FA.
u l can be obtained.

As is clear from the above, in the μ embodiment shown in FIG. 3, when a digit line is not selected, the read IF, f51U does not flow to that digit line. No additional transistor is required to prevent the read current for a line from flowing through the read transistor for that digit line. In addition, in such a configuration, the power consumption PT due to the operation 'rPL flow' of the memory is given by P = 21
become. In other words, the power consumption is only for one column (actually one memory cell) no matter how many columns n of IJ boxes are formed by memory cells. Also, the number of write control transistors is n in the case of FIG.
Another advantage of this configuration is that it is reduced to 1/2.

Furthermore, a write control transistor Qwo.

Since the digit line is not directly driven by the emitter of QWl, there is an advantage that the noise voltage appearing on the digit line is significantly reduced.

Next, the circuit shown in FIG. 3 is further improved to eliminate the risk of the potential of the digit line rising when it is not selected, thereby preventing malfunction of the memory cell and the disadvantage of limiting the achievable cycle time. FIG. 4 shows an embodiment in which noise generation in the digit line is reduced.

In the same figure, transistor Q Yll IQYI□.

QY□1 r When Qy2□ is in the cutoff state, the potential of the corresponding digit line is approximately the reference voltage V r a
I I to Q R11I QRI21 QIL□I I
A resistor of 1 t is used to set the value obtained by subtracting the base-emitter forward pressure of each l transistor, which is QIL22.
i I, l'tl 2.

By connecting R21 and R22 between each digit line and the negative voltage source V□, the digit line, voltage rise and noise generation are prevented.

For example, the transistor 'ILI□, uc anti-1]1
゜Negative power supply■. , the leftmost digit line in the diagram is not selected, and therefore the current 18. When is not flowing,
Transistor QIL + 1 + resistor 1 (, 11, negative power supply ■□
Because current flows through the path formed by V r e t l , the voltage on this digit line is held at a voltage determined by V r e t l. In this way, by providing a means for holding the voltage of the digit line for which ;l< is not satisfied at a predetermined value, an increase in the voltage of the unselected digit line 11L and generation of noise can be prevented. In this way, the current path consisting of the transistors Q and 11, the resistor R11, and the negative power supply vHB serves to maintain the voltage. Furthermore, this circuit is a simple circuit in this embodiment since it consists only of the transistor Q IL I and other small circuits. In particular, when the read transistor QR□1 is used as it is as the acid pressure holding transistor as in this embodiment, the voltage holding circuit becomes even simpler.

As described above, in the present invention, a sense circuit can be provided in common to a plurality of digit lines by using an offset transistor that performs a current switching operation between memory cells, which simplifies the sense circuit and Cell reading speed can be increased.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a current switching type multi-emitter memory cell and a read/write circuit; Figure 2 is a circuit diagram of a memory matrix using the memory cell shown in Figure 1;
The figure is a circuit diagram showing one embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams of other embodiments of the present invention. C1...Power supply terminal, El...Emitter drive terminal, R2, R3...Power supply terminal, I) IFA
... Curved differential amplifier, Jl, J2. Jll, Jl2. J2
1゜J22...Current source, M, Ml 1,
+V+ 12, M 21. M22...Memory cell %Q],,Q2...
...Memory cell transistor, QR...Reference transistor, Q, 1, ~QR121QIL2□~Q1
, 2□... Read signal detection transistor, Q
WO+ Qwl...Pledge control transistor, QY,...~QY□21QY21~QY□2...
・Digit line selection transistor, 81.82...
...Write/read amplifier 'Vref...Tune reference voltage, ■
Engineering 0. ■Y2...Dicts l-line pair selection signal,
■wo, VW□・・・Write control signal, 101, R
12, R21,) (,22...Resistance for preventing music noise. 1 Desired L-~-I J J
Continued from page 1 0 Inventor: Teruo Isobe, Hitachi, Ltd. Central Research Laboratory, 1-280 Higashi-Koigakubo, Kokubunji-shi 0 Inventor: Masahiko Yamamoto, 538- Hitachi, Ltd. Central Research Laboratory, 1-280 Higashi-Koigakubo, Kokubunji City

Claims (1)

[Claims] 1. The transistor has transistors for a plurality of word lines and a plurality of pairs of digit lines, and the emitter of each transistor is connected to one of the corresponding digit line pair, and the emitter of each transistor is connected to each digit line. a readout current source, a readout transistor whose emitter is connected to each digit line, a digit line selection transistor whose emitter is connected to each digit a, and a readout transistor connected to the collector side of the successive readout transistor. , differential detection means provided in common to each digit line pair, the read current for an unselected digit line pair flows through the selection transistor for the digit line pair, and the read current for the selected digit line pair flows through the selection transistor for the selected digit line pair. A memory device comprising means for applying a voltage for performing fla switching operation between a read transistor for the digit line pair and a selected memory cell to the bases of the selection transistor and the successive read transistor. 2. The differential detection means includes a first resistor commonly connected to the collectors of the readout transistors connected to corresponding one of each pair of digit lines, and a first resistor connected to one of the digit lines corresponding to each other of each pair. A second resistor commonly connected to the collector of the successive transistor connected to the other, and means for differentially detecting a voltage at one end of the first and second resistors. 1. Storage device. 3. A memory cell having a plurality of word lines, a plurality of pairs of digit lines, and a pair of cross-connected transistors arranged at the intersections of each word line and each digit line pair,
The emitter of each transistor is connected to one of the corresponding digit line pairs, a pair of readout current sources provided in common to the plurality of pairs of digit lines, and a pair of readout current sources connected to the pair of digit line pairs. a switch circuit for selectively connecting the digit line to the digit line; a first resistor connected to the collector of the transistor d tff'?, which are connected to each other, and the collector of the read transistor connected to the corresponding other of each pair of digits; a second resistor commonly connected to the digit line, and means for differentially detecting the voltage at one end of the first and second resistors.4. A third voltage holding circuit is provided on each digit line to hold the value at
Storage of terms.