JPS5859220U - gain control circuit - Google Patents

gain control circuit

Info

Publication number
JPS5859220U
JPS5859220U JP15440681U JP15440681U JPS5859220U JP S5859220 U JPS5859220 U JP S5859220U JP 15440681 U JP15440681 U JP 15440681U JP 15440681 U JP15440681 U JP 15440681U JP S5859220 U JPS5859220 U JP S5859220U
Authority
JP
Japan
Prior art keywords
analog switch
control circuit
gain control
input
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15440681U
Other languages
Japanese (ja)
Inventor
伏木 達郎
Original Assignee
ヤマハ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ヤマハ株式会社 filed Critical ヤマハ株式会社
Priority to JP15440681U priority Critical patent/JPS5859220U/en
Publication of JPS5859220U publication Critical patent/JPS5859220U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の利得制御回路の構成を示す回路図、第2
図は本考案の第1実施例の構成を示す回路図、第3図は
本考案の第1実施例において、Dkとしてバイナリ信号
を使用した場合の利得を示すグラフ、第4図は本考案の
第2実施例の構成を示す回路図である。 1.2,7,8.9・・・・・・OPアンプ、3・・・
・・・制御信号発生回路、4・・・・・・アップ・ダウ
ンスイッチ、5・・・・・・パワーアンプ、6・・・・
・・スピーカ、A1゜A2. A3・・・・・・反転増
幅器、Sl・・・・・・第1のアナログスイッチ、S2
・・・・・・第2のアナログスイッチ、r1〜r6・・
・・・・直列抵抗群、rl 2. r23. r34゜
、  r45.r55・・・・・・入力抵抗群、Do〜
D4・・・・・・デジタル信号、Vi・・・・・・入力
信号、Vo・・・・・・出力信号。
Figure 1 is a circuit diagram showing the configuration of a conventional gain control circuit;
The figure is a circuit diagram showing the configuration of the first embodiment of the present invention, Figure 3 is a graph showing the gain when a binary signal is used as Dk in the first embodiment of the present invention, and Figure 4 is a graph of the gain of the first embodiment of the present invention. FIG. 2 is a circuit diagram showing the configuration of a second embodiment. 1.2,7,8.9...OP amplifier, 3...
... Control signal generation circuit, 4 ... Up/down switch, 5 ... Power amplifier, 6 ...
...Speaker, A1゜A2. A3... Inverting amplifier, Sl... First analog switch, S2
...Second analog switch, r1 to r6...
...Series resistance group, rl 2. r23. r34°, r45. r55...Input resistance group, Do~
D4...Digital signal, Vi...Input signal, Vo...Output signal.

Claims (1)

【実用新案登録請求の範囲】 OPアンプによる反転増幅器の入力側に設けられ、; 入力信号を多段に分圧する直列抵抗群と、一端を前記直
列抵抗群の各接続点に接続され、かつ他端を2系統に分
岐され1.一方は第1のアナログスイッチを介して前記
反転増幅器の反転入力に接続され、他方は第2のアナロ
グスイッチを介してアースまたは仮想アースされた入力
抵抗群と、前記第1のアナログスイッチと第2のアナロ
グスイッチとを相補的にオン、オフさせるスイッチング
制御手段とからなることを特徴とする利得制御回路。
[Claims for Utility Model Registration] Provided on the input side of an inverting amplifier using an OP amplifier; a series resistor group that divides the input signal into multiple stages; and one end connected to each connection point of the series resistor group, and the other end was branched into two systems: 1. a group of input resistors, one of which is connected to the inverting input of the inverting amplifier via a first analog switch, and the other to ground or virtual ground via a second analog switch; What is claimed is: 1. A gain control circuit comprising: an analog switch; and switching control means for turning on and off the analog switch in a complementary manner.
JP15440681U 1981-10-17 1981-10-17 gain control circuit Pending JPS5859220U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15440681U JPS5859220U (en) 1981-10-17 1981-10-17 gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15440681U JPS5859220U (en) 1981-10-17 1981-10-17 gain control circuit

Publications (1)

Publication Number Publication Date
JPS5859220U true JPS5859220U (en) 1983-04-21

Family

ID=29947005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15440681U Pending JPS5859220U (en) 1981-10-17 1981-10-17 gain control circuit

Country Status (1)

Country Link
JP (1) JPS5859220U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60206209A (en) * 1984-03-29 1985-10-17 Teac Co Sound volume controller
JPH0321110A (en) * 1989-06-19 1991-01-29 Hitachi Ltd Gain control circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60206209A (en) * 1984-03-29 1985-10-17 Teac Co Sound volume controller
JPH0321110A (en) * 1989-06-19 1991-01-29 Hitachi Ltd Gain control circuit

Similar Documents

Publication Publication Date Title
JPS5859220U (en) gain control circuit
JPS583612U (en) amplifier circuit
JPS58135116U (en) Muting circuit
JPS5843032U (en) filter circuit
JPS5877930U (en) analog switch
JPS6047316U (en) Amplifier
JPS5832598U (en) Gain switching circuit
JPS5950115U (en) Protection circuit for switching type amplifier
JPS6074341U (en) switching circuit
JPS5883837U (en) semiconductor switch circuit
JPS59154934U (en) analog switch circuit
JPS62100800U (en)
JPH02130116U (en)
JPS5881616U (en) Output voltage adjustment circuit
JPS5882022U (en) Audio output level variable device
JPS58150134U (en) Multiple key press detection circuit
JPS60123057U (en) multiplication circuit
JPS5885250U (en) integrator
JPH0290539U (en)
JPS5996916U (en) variable gain amplifier circuit
JPS60160628U (en) electronic volume
JPS6095744U (en) Sample and hold type deglitch circuit
JPS60108022U (en) mixing circuit
JPS5883817U (en) audio amplifier
JPS6126315U (en) Amplifier muting circuit