JPS5857824A - Programmable logic array - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a PLA (programmable logic array), by individually controlling clocks of a plurality of internal registers of the PLA with gate circuits of PLA construction. CONSTITUTION:In inputting a clock 1 to a register 7 being one of internal registers, an enable gate 6 is provided to be controlled based on enable signals. The control signal is determined with the logical architecture of an AND matrix 41 and an OR matrix 51, and an input 01. Logical operation is done for data with an AND matrix 42 and an OR matrix 52 and the result is outputted to the register 7. Since the same matrix constitution is provided for each internal register, the timing of clocks can be programmed for each register.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit, that is, a PLA (programmable logic array), which has a function of selectively configuring a commonly prepared AND-OR gate network according to the purpose of use by simple rewriting means. 〇 Conventionally, a medium-sized and comparatively high-speed logic N circuit as described above, which has 8 human power, 8 outputs, and 8 internal registers in the inner layer of the PLA, has not been commercialized. . That is, 8
The positive signal of the main input signal and the internally inverted negative signal and 8
From a total of 32 signals (positive and negative signals) of the internal register, one logic unit outputs 8 multi-ND output signals from the 8132 AND gate network, and outputs the IO from this one ND output signal.
The R output selectively generated from the 1x goa genito network is input to an internal register consisting of a D-7 lip-flop, and is output to the internal register by a commonly supplied clock signal. Further, the register output signal of the internal register is outputted as an output signal via an enable gate controlled by a commonly supplied enable signal. Eight such logic units are integrated into one integrated circuit (118 units), and the user can realize any medium-sized functional circuit by electrically fusion-connecting or breaking the AND or OR gate network according to the purpose. 〇On the other hand, when these are actually used, the range of use of the eight internal registers is often limited because the clock signals of the internal registers are common. In control logic circuits that are often implemented by PL engineers, it is not easy to integrate a plurality of individual small-scale logics into one PL system.

The purpose of the present invention is to enable the individual small-scale control logic required for a medium-sized PLM to be integrated and stored in one PL system, and to make it possible to efficiently use general-purpose logic circuits without waste. According to the present invention, it is possible to provide a method for configuring a PL system that can be used for general purpose purposes.According to the present invention, a simple gate for the lock signal is provided which is common to all the medium-sized PL systems currently in use. By providing this, it is possible to improve the internal registers so that they can be used for individual control purposes without changing the size of the input/output signals or internal circuitry. The invention will be explained in detail. The figure is a block diagram showing one embodiment of the present invention. Logical unit) O is one of the eight logical units that make up a medium-sized PI, as an example, and the other seven units 〇The logic unit has one input signal o1 and one output value 4#1) 2. Furthermore, the clock signal 1 and enable signal 2, which are commonly provided to each logic unit, are connected to the amplifier W and the adder. connected via. Roughly speaking, the logic unit O is composed of an input T pump Oo, an input NOT gate 3, an AND gate network 41, 42, an OR gate network 51.5N, a clock gate 6, an internal register 7, and an enable gate 8. AND gate networks 41 and 42 each receive a count signal consisting of the positive and negative signals of the input signal o1 and the input signals of the other seven units, and the internal register 7 and the other seven units.
Positive and negative output signals yoi and rot of internal registers of the unit
This is an 8x32 AND gate network that supplies a total of 32 signals (16 signals, etc.) to eight ANDN-gate groups, etc.

This AND gate network is constructed by connecting the pre-separated intersection points, for example 400, with appropriate electrical melting means, so that the 0AND gate group 43, etc., which are AND-connected in the row direction, is connected to the OR gate network 51, 52. Then, with the same configuration as the AND gate network, the OB game) 534! OR by
Logic is created. The output g1 520 of this 08 gate network 52 becomes an input signal to the internal register 7 consisting of a D flip-flop. On the other hand, the output signal 51 of the OR gate network 51
0 is provided for gating the amplifier output signal of common lock signal 1 by clock gate 6, the output 60 of clock gate 6 being provided to internal register 7. Thus, the AND corresponding to the data signal.

AND and OR gate network 41. which is applied to the black signal with a configuration similar to that of OR gate network 42.52. By providing the sl and i9F gate 6, the user can
D, OR gate network '1% For the configuration of zero or more units, the clock signal to the internal register 1 can be generated individually for each unit by programming the intersection of 51, its operation is extremely fast. Although the details are omitted because they are easily determined, the point to pay attention to in 41 is the timing of the clock signal to the internal register 7 and the data signal 520. In other words, generally at the time of supplying the clock signal, The data signal 520 is statically determined, and the output signal s1 from the gate having a configuration similar to that of this data signal 520 is also statically determined.However, the clock gate 6 is statically determined. Since the clock signal 1 is gated by the gate 4i 510, correct operation is guaranteed, and
Compared to the case without the enable gate 6, the delay increases by only one stage, and this delay is sufficiently small compared to the delay of the internal register and enable gate ◎ This concludes the details of the present invention. Although I have completed the explanation about
The number of logical units (O) and the MND gate network 41
．． 42s 01 gate network! il, 52 &) Changes in quantitative scale have nothing to do with the essence of the project, but include it.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention.
On the right, O is one of a plurality of logic units, %01 is its input signal, 02 is its output signal, l and 2 are the logic units, and do not indicate the clock signal and enable compilation signal supplied to the logic unit. --- ・-AND gate network, 51
．． 52 -------OR gate network, 6------
---Clock gate, 7...Internal register,
5-------enable gate, 0O1lO1
20...--Amp, 3...Fist...
Input tightening force is NOT gate.

Claims (1)

[Claims] A plurality of input signals and an NΦ gate network and an OR gate network are selectively configured to be variable by electrical rewriting means from the positive and negative signals of the output signals of the plurality of internal registers, which are included in the input signals and output signals of the plurality of internal registers. In the programmable logic array that outputs the output signal from the internal register, a common clock signal supplied to the internal register is connected to a gate circuit network having a similar configuration to the AND gate network and the OR gate network. The invention is characterized by having means for individually controlling the clock signals to the plurality of internal registers by dating the output signals.