JPS5856535A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To reduce the phase lock pulling-in time while using a highly stable voltage controlled oscillator, by generating a large phase unlocked state in a phase locked loop forcedly until the phase lock is done. CONSTITUTION:A reference signal Vf1 is inputted to a frequency divider 11 via an AND gate 22-2, and a phase difference between a signal 1/n1-frequency- divided at the frequency divider 11 and a signal 1/n2-frequency-dividing a signal from a voltage controlled oscillator at a frequency divider 15 is detected at a phase detector 12. A phase difference discriminating circuit 21 discriminates whether or not this phase difference is within a prescribed range and when it discriminates as outside of the specified range, the circuit 21 starts a rectangular wave oscillator 22-1, switches the gate 22-2 almost periodically and interrupts the signal Vf1 from being inputted to the frequency divider 11. Thus, a large phase unlock is caused in a PLL forcedly, allowing to close the phase difference to zero rapidly. When the phase difference comes within the prescribed range, the circuit 21 stops driving of the oscillator 22-1 and an H output is kept being applied to the gate 22-2. An output of the detector 12 controls the oscillator 14 via an LPF 13 to output a signal Vf2 in a desired frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase synchronized highly stable oscillator circuit for Kinoi 811FX oscillator circuit 1%.

Using a reference signal of MIIIi several ft, it is often done to generate an oscillation output t''4 of a highly stable frequency fa in phase synchronization with this reference signal.The purpose of this method is to use the phase cycle mentioned in the non-invention. This oscillation circuit is a highly stable oscillation circuit in the form of a 7-phase cruiser (PLL), including a voltage-controlled keepsake oscillator (CVCO) as described later.
Although it forms the.

It is often accompanied by inconvenient problems. This inconvenience causes phase locking to take an unusually long time.

For example, it may take about an hour. The reason why such a problem occurred is that a highly stable VCO was used. This is because the more stable the VCO, the more control input voltage C
This is because the relationship between V) and oscillation output frequency (1) is moderate. In other words, even if the control human power room 8E(1')'fr: is changed greatly, the oscillation output frequency does not change that much. Then, the relationship between (V) and (1) is sensitive, and the above-mentioned problem can be solved by using co. This idea holds true. However, a VCO with a sharp (V) vs. (f) ratio of 05 is generally a VCO with poor stability. It is unsuitable as a second VCO.

Therefore, an object of the present invention is to propose a highly stable oscillation path of the phase synchronization type which can significantly shorten the one phase synchronization pull-in time compared to the conventional one while using highly stable co'Jk.

In accordance with the above object, the present invention is characterized in that a large out-of-phase state is forcibly caused within the seven-way lock loop until it reaches a one-phase synchronization pull-in state.

FIG. 1 is a block diagram showing the configuration of a general phase-locked and highly stable oscillation circuit. In this figure, V,1 is a reference signal, which is a highly stable reference oscillation signal with two frequencies jt. Vf* is the desired signal.

This is an oscillation output signal with a frequency ft that is phase synchronized with the reference signal V,1. A voltage controlled keepsake oscillator (VCO) 14 is used to send out this oscillation output signal V, . VCO (Vol.
stage Controlled 0s6illato
r) All output signals from the 1-order difference detector Hd@12 are received through the 14i low-pass filter filter (LPF) 13f, and this is used as the voltage control input. This voltage control input has a voltage proportional to the phase difference between the signal V/1 and the signal Vf, and a voltage (V) at a level proportional to the phase difference is applied to VCOl4.
oscillation output frequency U). This phase difference is detected by the phase difference detector (PD).
or) detected by 12. As a result, the phase difference detector 12 passes through the M1 divider (divider ratio π1) Ilf to the next reference signal V, , ig2, W6W (minute [ratio 32) 1
The oscillation output signal V□ is input to the 5'i communication L7, and the phase difference between the two is detected. Just in case this phase difference converges to zero.

This is to ensure that the signal V/, is phase synchronized with the signal V,1.

Here, a so-called 7A's Loc Loop (PLL) is formed.

By the way, as mentioned above, when VCOl4 is extremely stable and co-2 is used, the relationship between voltage (V) and wave number (f) is very gentle, and oscillation occurs even though the phase difference is quite large. The output frequency a does not change that much. As a result, it often happens that it takes a longer time t to pull in the two-phase synchronization. In general, the phase synchronization can be completed by the phase synchronization pull-in time T. However #N
: Frequency division ratio of the second frequency divider (n 2 ) + K : Phase difference (ra
d) e Gv* Gain of VC'O14 (rad/s
ee mV), V,: VC when input signal is cut off
Ol 4 human powered electric power EE (V) -Vo: V at synchronization
This is the input voltage (V) of COl 4.

For example, center frequency fn=3720kHz, variable characteristic I
Using f = 0.075 ppm/V OVCOt-, the maximum phase synchronization pull-in time T for N''1000-Va-Ve''I V is given by the gain of the VCO being G-211-no/'fn''0-075 X 10
Since X 2πX3720 x10ν = e 1.75 rad / age * V.

N 1000 times tp approximately 59 minutes and 50 seconds. It takes such a long time and is extremely inefficient.

FIG. 2 is a block diagram showing the configuration of a phase-locked and highly stable oscillation circuit according to the present invention, and FIG. 3 is a waveform diagram used to explain the operation of the circuit of FIG. 2. The structure FiC of the present invention will be explained below with reference to FIGS. 2 and 3. However, in Fig. 2.

The same reference numbers or symbols are given to the same nine elements as in FIG. 1. Therefore, 21.22-1.22- in Figure 2
This means that the second-class block and the connections around it have been added to the new nine. 21 is a phase difference determination circuit, to which a signal -
A disconnection circuit (22) is attached. Signal momentary interruption [Reference g to 22
! This is a circuit that instantaneously interrupts the signals V and 1 at approximately IIJ intervals.For example, a square wave oscillator 22-1 (which outputs "H"H when not driven) and an AND game)
22-2. The phase difference determination circuit 21 determines whether the phase difference from the output of the zero phase difference detector 12 is within a predetermined range (rad). If it is within a predetermined range, one phase synchronous pull-in must be performed. For this purpose, the square wave oscillator 22-1 is activated. This oscillation output waveform is shown in column 6) of FIG. 3, and is further applied to one input of the AND gate 22-2. Then, the AND gate 22-2 opens and closes approximately periodically* a
) The reference signal CI/, □) t-1) There is a momentary interruption as shown in #. By momentarily interrupting the reference signal, a large out-of-phase condition is forcibly created in the 7A p-to-loop (CPLL). As a result, the shape of PI, L is greatly changed by 1 m. For example, the initial phase difference φ1 becomes instantaneous interruption tl, t2. t3 (see column J)) decreases in large steps such as 1, -I,
The phase difference rapidly approaches zero. If the phase difference falls within a predetermined range, the second judgment circuit 21 deactivates the oscillator 22-It.
# The as output continues to be applied to the AND game) 22-2. In other words, we return to the circuit equivalent to that shown in Figure 1.0 Furthermore, 51g3
The pair of pulse frames in each of columns d) to f) in the figure are drawn to schematically express the phase relationship between the reference signal V71 and the oscillation output signal V/1, for example, the phase difference detector 12. It corresponds to a pulse obtained by converting the two human forces from a sine wave into a rectangular wave, and then differentiating the rising edge of the wave.

Also, in columns d) to f) of Fig. 3, the phase difference is −”→φ”→φ
I have shown an example where I gradually decreases, but in some cases.

Not everything changes sequentially like this, even in the dark box it changes randomly.
It is clear that, for example, if one minute passes, the phase difference will drop to a predetermined range of one phase difference. Timing when a desired small phase difference appears while forcibly disturbs the 7-axis lock loop CPLL) [Waiting]. This disturbance is given at a rate of 0 Hz, for example 10 Hz. That is, the rectangular wave oscillator 22-1 is, for example, a 10 Hg oscillator.

In this way, the optimum phase difference can be formed quickly,
It is impossible to require a long time, for example about one hour, as in the past.

As explained above, according to the present invention, a phase synchronized oscillation circuit is realized which is highly stable and can significantly shorten the total phase synchronization pull-in time.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a general phase-locked type and highly stable oscillation circuit; Fig. 2 is a block diagram showing the configuration of a phase-locked type and highly stable oscillation circuit based on the invention; 3
This figure is a waveform diagram used to explain the operation of the circuit of FIG. 2. 12... Phase difference detector, 14... Voltage controlled oscillator. 21...Phase difference determination circuit. 22-1 and 22-2...Reference signal disconnection l112 circuit. V...Reference signal, V□...Oscillation output signal. Patent applicant Fujitsu Ltd. Patent application agent Akira Aomizu 9Pj]! Kazuyuki Nishidate Patent Attorney Yukio Uchida Masu Sankuju Akira Yamaguchi Figure 1 1'D Figure 2

Claims (1)

[Scope of Claims] 1. A voltage-controlled keepsake vibrator that sends out an oscillation output signal whose phase is to be synchronized with a reference signal, and a voltage-controlled keepsake that detects a phase difference between the reference signal and the oscillation output signal. Shaker electric E
In a phase synchronized oscillation circuit having an EIIJ signal input and a phase difference detector forming a 7-Azroz cruise together with the voltage-controlled replica oscillator. a phase continuous foot circuit that determines whether the phase difference from the phase difference detector exceeds a predetermined range; and a phase continuous foot circuit that determines whether the phase difference falls within the predetermined range. 2. An oscillation circuit characterized in that the oscillation circuit further includes a signal-disconnection circuit that momentarily interrupts the reference signal substantially periodically.