JPS5856180B2 - magnetic bubble memory chip - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in magnetic bubble memory chips, particularly double-layer conductor film current-driven magnetic bubble memory chips.

Conventional double-layer conductor film type memory chips have the advantage of being capable of high-speed operation, but on the other hand, they require a large current to obtain the magnetic field necessary for bubble drive, which places a heavy burden on the drive system.

Therefore, first of all, in order to highlight this drawback,
A, a brief explanation of the general structure and operation of a conventional memory chip will be given with reference to FIGS.

As shown in FIGS. 1A and 1B in plan view and cross-sectional view, respectively, the magnetic bubble transfer path includes a first-layer conductor film 3 provided on a substrate film 1 that carries bubbles via an insulating spacer 2, and a A second layer conductor film 5 is formed via two insulating spacers 4, and a pair of opening buttons 3a+5a are provided in the first and second layer conductor films 3.5 in a predetermined overlapping relationship with each other, and these are arranged in the propagation trajectory direction A. A plurality of them are arranged at a predetermined interval λ (a length four times the bubble diameter) along the line, and each pair of open buttons constitutes one bit.

The main structure of the transfer path basic block is as described above, but normally a chip protection film 6 is provided on the second layer conductor film 5 as shown in the figure.

In such a configuration, as shown in FIG. 2A, the current (2) to the first layer conductive film is controlled to have positive and negative phases P1. At P3, the current ■' to the second layer conductor film is changed to a predetermined sequence (Pl + P2, P3, P4...
...When applying in the I and I' directions shown in the first diagram according to the above, the positions under the edge of each hole in Figure 1 with the same reference numerals corresponding to the respective phases PI + P2 r P3 + P4 +
A bubble, or information propagation, takes place along the...

Here, it is assumed that the bubble has downward magnetization, but the same applies below.

The loop, which is the basic construct for retaining and transferring information, consists of two of the above linear transfer paths lined up, each with 18 mm at both ends.
Formed by connecting at 0 degree corner.

Then, these n loops of equal length rnl y
rn2 +...2m as a minor as shown in the third diagram.
A plurality of rows of loops are arranged in parallel to form a storage area, and these loops are formed on the second layer conductor film (or another layer) via an insulating spacer, and are used as a transfer film with a switch function. A major-minor loop configuration is connected to a major loop, which is an input/output area, through a gate T.

Arranged on the major loop are components that perform input/output operations with the outside, ie, a bubble generator G1 for writing information and a detector G1 for reading information.

The major and minor loop lengths are typically
It is chosen to be equal primarily due to performance requirements, so the chip is approximately square.

However, in such a conventional chip, current is supplied in parallel between a large number of opening battens, and an extremely large current is required as a whole.

Furthermore, the chip resistance as a load becomes extremely small, making it difficult to match the impedance with the power supply cable.

In response to this, it has been proposed to make the chip elongated to reduce the current and to match the impedance.
This is undesirable as it significantly impairs performance and space factors.

In this case, there are also proposals to improve the space factor by bending the elongated chip, but this does not lead to improved performance and is not a fundamental solution in any case.

In view of the above, it is an object of the present invention to provide a memory chip that can easily reduce chip drive current and match impedance with a power supply cable without degrading performance.
The main purpose of this design is to make it possible to obtain the same current density and therefore drive magnetic field as in the prior art even if the supplied current is reduced.

The present invention substantially relates to minor loop formation tilting of a two-layer conductor film of a chip and improvement of the minor loop.
Briefly, the minor loop forming region of the two-layer conductor film is divided into multiple row regions with slits, and each row region is provided with at least one row of small loops, and the same loops are arranged in the adjacent row regions. Parts of the inner corners of the small loops included in the column across the slit are connected to each other using a swap gate, while adjacent row regions are electrically connected so that the magnetic bubble propagation direction of each of the small loops is the same. These are connected in series.

The major loop may be integrated with the bottom row (or top row) two-layer conductor film head region in the chip area that can be used as a memory, or may be divided.

In addition, major
Separate the loop and minor loop and transfer
A method of connecting with a gate has already been proposed.

However, this method and the improvement of the minor loop itself of the present invention are completely different in concept.

That is, in the past, a minor loop was itself a complete loop, and it was impossible to think of dividing it with a slit in the middle.
This is because no means of constructing one minor loop from several small loops had been seen.

On the other hand, the present invention succeeds in connecting minor loops using a swap gate to form one minor loop.
As a result, the current path inevitably becomes longer, increasing the resistance and reducing the current.

Examples of the present invention will be described below.
Constituents, currents, and phases that may be the same as those in the figure are given the same symbols.

In the embodiment shown in FIG. 4, a book slit S1 + 82 +". When the number is even, a part of the right end is cut off, and when the number is even, a part of the left end is left uncut, so that the entire chip has +1 row area Co, C1, . . . , C.
These are divided into k equal parts and connected in series in a meandering manner.

In this case, the row area C8 in the bottom row becomes the area for the major loop M, and the row areas C1 to Ck as a whole serve as the minor loop forming area.

Then, each line head area C in this minor loop forming area
For i, i=1, 2, ++・, k, there is a small loop III of n columns s 1 +mi2 , "'rr
l t j”'min + 1 ”” C2,...
, a small loop m, . . . exists in the adjacent row region Ct, C1+1 and is included in the same column J.

Swap game 1 between the corners of mi+1j
-Ti+, so that one minor loop mj is formed for each column J, and the function as a whole is equivalent to the conventional minor loop group shown in Figure 3. There is.

In this way, the current-resistance is approximately (k+1) while maintaining the same performance as the conventional chip shown in Figure 3.
It is possible to realize a chip that operates twice as fast and, if necessary, has expanded functionality compared to the conventional chip.

Regarding the former basic effect, increasing the number of divisions means further reducing the required current, which also has the following effect.

In other words, by increasing the number of slits and decreasing the spacing between the slits, the current flowing between them is more strongly influenced by the slits. area) increases.

On the other hand, as an incidental effect if necessary, the latter is Swara Two Gate T1. T2. . . . is closely related to the independence of each drive circuit of Tk.

For example, if all are dependent, i.e. all gates are driven simultaneously by a single gate drive circuit,
The above chip only functions as a single loop.
But the major loop and minor loop mlj, j=1,
2,...,n.

By making only the gate T1 between them independent, the chip can have the same functionality as a conventional chip.

The function is expanded as the number of independent gates is further increased, and if all are made independent, any small loop can be created.

It has advanced functions such as exchanging information blocks between mi'j.

However, as the number of independent gates increases, the number of gate drive circuits and bonding will naturally increase.
This number may be determined based on the function to be obtained and the trade-off between the drive system and process.

As described above, the major loop generator G1 and the detector shown in FIG. 4 are the same as those of the prior art.

By the way, when adopting the minor loop configuration of the present invention,
A swap gate that connects small loops and can exchange information at the same time is an essential component, but at present there are no swap gates that can be applied to such double-layer conductor film type memory chips. , only those separately disclosed by the applicant.

Therefore, this embodiment will be described as using this swap gate, but if a swap gate with a different configuration is developed in the future, it may of course be used as long as it performs the same function. However, as long as the memory chip structure of the present invention is adopted, there is no doubt that it falls within the scope of the present invention.

Based on this premise, the swap gate in this embodiment will be explained as an example with reference to FIG.

Swamp 0 gate 'ri+1 is provided at the position corresponding to the i+1st slit si+, and
In the drawing of Figure A, the upper pair of vertices become part of the corner of the small loop mi+lj located above, and the lower pair of vertices become part of the corner of the small loop rnlJ located below. Pair 3b, 5b1 and slit si+1
The conductor 7a is arranged to surround the conductor 7a.

7b, and the reciprocating line as a whole (i.e. conductor 7a,
7b is connected at one end thereof).

The portion other than the gate of each small loop is constituted by the opening tabs 3a and 5a of the first and second layer conductor films as in the conventional case, but the direction of the current flowing between the opening tabs is determined by the slit s.
In the upper and lower conductor film row regions C1°Ci+1 with i+1 as the boundary, the directions are opposite to each other from the above-described configuration.

The positive current phase P1. The same explanation can be given even if it corresponds to P3, so here it is assumed that the right direction in the plane of the upper row area C1+1 is positive.

The same applies to the gate current ■G.

Also, as mentioned above, bubbles have downward magnetization.

2nd A illustrated sequence (Pt l P21 P3 +
In the upper half plane C1+1, the positions of the bubble trapping points corresponding to P4, . . . are located at positions P1, . P2゜P
3. P4. ..., similarly P1', P in the lower half plane C1
2'P, P, ....

In this way, in the case of small roof frost...3 4 mi + 1j, the bubble propagation direction is the same, and the position of the bubble trapping point is reversed on the half-plane between the upper and lower ends, so that on the gate opening pattern pair 3b, 5b. In this case, the upper and lower hole edges of each opening serve as capture points at the same time, and the two bubbles located at corresponding positions in the upper and lower small loops are simultaneously sucked from this opening slam.

Therefore, at the moment when the buffer is absorbed into Po and P1', a current I is applied to the gate conductor 7 at the timing shown in Figure 2B.
When G is applied, the bubble changes from P1 to
Propagation is performed along the paths P2 and P□'→P2', or P1→P2' and P1'→P2.

When the gate current Iδ is applied, the region N shown in Figure 5B,
Potential peaks and valleys are formed in P, and the bubble is repelled from region N and attracted to region P, taking lateral paths P1→P2 and P1→P2, resulting in intra-loop propagation.

When IG is applied, the potential becomes the opposite polarity and the bubble is prevented from propagating in the lateral direction, so the path P1 → P2'
and P1'→P2 and move to the upper or lower adjacent bubble capturing point.

That is, information is exchanged (swap operation) between the small loops rni j and rni + 13.

If necessary, a plurality of pieces of information can be replaced by repeatedly applying a gate current as shown in Figure 2B.

However, in order to cause intra-loop propagation, it may be necessary not to apply the gate current IG.

In addition, each of the openings 3b and 5 forming a pair of crossed opening slams
Regarding the shape of b, the crank shape may be reversed to form an H-shape as a whole as shown in Figures 6A and B, or any other equivalent shape, and the shape of the opening itself may be rectangular instead of elliptical. It may be hexagonal, but the dimensions should be long enough (approximately 4 times the bubble diameter) that the interaction between these two bubbles can be ignored, since the bubbles in the upper and lower loops are simultaneously sucked under the upper and lower hole edges. must be set.

In addition, as shown in FIG. 5B and FIG. 6A, in the crossover pair, the intersection portions 3b and 5b of the virtual lines are slits s t
Please note that it is notched by +1.

On the other hand, regarding the gate conductor 7, each region N, P shown in 5B is
It is only necessary that peaks and valleys or valleys and peaks of the potential can be formed at predetermined timings, that is, that an equivalent current loop can be formed in the regions N and P, and there are no limitations on the shape and arrangement thereof.

For example, as shown in Fig. 7A, B, and C, the conductor may have a square, round, or ■-shaped shape, or as shown in Fig. 7, the minimum distance between the conductors 7a and 7b is smaller than the slit width. It may be arranged in a smaller size.

Further, as for the layer in which the gate conductor 7 is provided, as long as it satisfies the above-mentioned effect, even if it is a layer below the first layer conductor film,
It may be between the first and second layer conductor films or above the second layer conductor film.

Above, we have explained the case where the chip is divided into equal parts using linear slits, but strong driving force can be achieved by changing the slit spacing appropriately or by using curved slits. It is also possible to increase the current density where it is needed.

In addition, as mentioned earlier, the slit at the boundary with the conductor film row region Co at the lower end that constitutes the major loop is completely isolated from others without leaving any current-carrying parts, and a current is applied by a dedicated power supply. By doing so, the major loop and the minor loop (consisting of a group of minor loops) may be operated independently.

In the above explanation, the adjacent line head areas Ci and Ci+1 are connected by leaving either the left or right end of the slit s1+ uncut, but it goes without saying that each line area is completely cut out.
The connection may be made using an external lead wire, or the upper and lower conductor films may be meandering in the left and right directions.

Finally, when implementing the present invention and commercializing it, desirable considerations will be described and provided for reference.

In this type of current-driven magnetic bubble memory chip, the current flowing through each conductive film causes the 8th A
A current flowing in the vicinity of the open button in the first layer conductor film shown in the figure (although the first layer conductor film is illustrated in FIG. 5, the same can be said of the second layer conductor film) flows into the substrate film 1 The vertical component H1 of the generated magnetic field is deviated positively or negatively (vertical magnetic field deviation) as shown by the solid line in FIG. 8B.

This polarity and magnitude are determined by the direction of the current, the density, the width and length of the conductor film region, etc., but the absolute amount increases as it approaches the periphery.

A portion where this value exceeds the range in which bubbles stably exist cannot be used as a memory, but such a portion generally covers a wide area on the chip, making it difficult to achieve high integration and low cost.

In contrast, the present inventor has discovered that in addition to the first and second layer conductor films,
A third conductor film having slits (not having an open opening) is provided at the same position as these, and this is connected to the above two conductor films 3.
, 5, a current ■3+■3' with a direction and magnitude that cancels the vertical magnetic field deviation created in the substrate film by the currents I and I' flowing through the substrate film.
A separate invention has been made to solve the above-mentioned inconvenience by applying .

Here ■3. (3'6) Currents I and I' in the first and second conductive films, respectively, are currents for canceling the vertical magnetic field deviation created in the substrate film.

To give a more detailed explanation, the component (3) of the current flowing through the third conductor film, which corresponds to the current (2) in the first layer conductor film, creates a perpendicular magnetic field H2 in the substrate film as shown by the broken line in FIG. 8B.
is formed.

Therefore, the vertical component H of the composite magnetic field created in the substrate film by the currents ■ and ■3 flowing through the first layer conductor film and the third conductor film
3 is only the variation due to the opening slam (magnetic field variation for driving the bubble) as shown in Figure 8C.

Current ■′ of the second layer conductor film and current I of the third conductor film
Similarly for 3/, it can be confirmed that the vertical magnetic field deviation is eliminated over the entire chip area.

Therefore, since the disadvantages of the conventional chip are improved, it is preferable to apply this third conductive film to each row region in the present invention as well.

In this case, ■3. ■The size of 3' is the substrate film and the first layer,
It is determined by the distance between the second layer and the third conductor film, the thickness of the substrate film, the currents I and I' of each conductor film, etc.

Since the third conductive film only needs to satisfy the above-mentioned functions, it may be provided between the substrate film and the first conductive film, between the first and second conductive films, or above the second conductive film. However, it is highly desirable to have this on the same layer as the bubble detector leads, generator, and swap gate control conductors to reduce mask levels and simplify the manufacturing process. .

Although it is relatively easy to construct the lead wires of the bubble generator and the detector in the third conductive film, when applied to the present invention, the construction of the swap gate control conductor requires some ingenuity.

That is, as shown in FIG. 9A, the gate conductor 7 is the first,
The slits in the second layer conductor film (as described above, these have the same shape and the same arrangement.

) must have a shape that surrounds and does not cross the virtual slit 8a (shown as a single line) projected onto the third conductor film 8.

The details of the circled parts 9 and 10 in FIG. 9A are shown in B and B, respectively.
As shown in Figure C, the slit width of the third conductor film is larger than that of the first and double-layer conductor films by the amount of the gate conductor 7 and the insulation gap 11 between the conductors 7 and 8. However, since the deviation between the end faces of the upper and lower conductor films is smaller than the 1-bit interval, this effect can be ignored (the magnitude of the magnetic field deviation in this part is not so large that it deviates from the condition for the stable existence of bubbles).

In Figure 9A, the gate conductor is connected to three power sources IGm +'IG
Although the case of driving with O, IQe is shown as an example, it is also possible to drive these as a whole with a single power supply, or with IQe.
Go.

(2) It is possible to drive Ge as a whole with two power supplies, or to drive it independently with more power supplies.

As described in detail above, according to the present invention, it is possible to reduce the drive current of the bubble memory and to match the impedance between the chip and the power supply cable, thereby reducing the burden on one drive system and, if necessary, By dividing swap gates into groups and driving them independently, it is also possible to expand on-chip data manipulation capabilities.

[Brief explanation of drawings]

1A and B are respectively a plan view and a sectional view of a two-layer conductive film type magnetic bubble transfer path, and 2A and B are explanatory diagrams of the driving current sequence of the transfer path and the swap gate used in the present invention, Fig. 3 is a schematic diagram of an example of a conventional major-minor loop configuration, Fig. 4 is a schematic diagram of an embodiment of the memory chip of the present invention, and Figs. 5A and B are used in the embodiment of the present invention. An explanatory diagram of the swap gate and an explanatory diagram of the magnetic potential distribution in the vicinity of the cross-opening button pair at the gate, Figures 6A and 6B are respectively a plan view of a modified example of the cross-opening button pair, and Figures 7A and B are respectively Figures C and D are respectively plan views of modified examples of the gate conductor, and Figure 8A. Figures B and C are plan views of the open Ropakun in the first layer conductor film, current in the first layer conductor film, and current ■3 in the third conductor film, respectively.
9A, B, and C are explanatory diagrams of the perpendicular magnetic field distribution created in the substrate film and the combined magnetic field distribution, respectively. FIG. 2 is an enlarged view of main parts of regions 9 and 10. In the figure, 1 is a substrate film as a bubble carrier, 2 and 4 are substrate films, insulating spacers between the first layer conductor film and between the first and second layer conductor films, and 3 and 5 are the first and second layers. Conductor film, 6 is a chip protection film, 7 is a gate conductor, 8 is a third conductor film, C1 is each row region, m is a minor loop, m is a small loop, Ti
is a swap 3 gate.

Claims (1)

[Scope of Claims] 1. A magnetic bubble memory chip in which a minor loop and a major loop are formed by opening tabs provided in a two-layer conductive film on a substrate film that carries magnetic bubbles, the above-mentioned portions of the two-layer conductive film comprising: The minor loop forming area is divided into multiple row areas with slits, each row area has at least one column of small loops arranged in parallel, and the small loops belonging to the same column in the adjacent row areas are Parts of the corners facing each other across the slit are connected to each other by a swap gate, while the adjacent row regions are electrically connected in series so that the magnetic bubble propagation direction of each of the small loops is the same. A magnetic bubble memory chip characterized by: