JPS5856043A - Parity check system of byte mark - Google Patents

Abstract

PURPOSE:To reduce hardware by making a parity check only by the parity of all transmitted byte marks without providing parity bits per minute for every transferring. CONSTITUTION:A parity check circuit has a flip-flop FF, which is inverted on arrival of every write signal DBRWT from input and output equipment. Namely, this FF calculates the odd parity of all byte marks written in all byte mark registers. After tansfer from the input an output equipment ends or after all data buffer registers are full, transfer to a CPU starts. In this case, the FF is inverted by the output BMP of a parity generator when a readout signal EXTRD arrives from the CPU. Namely, the FF is inverted when the BMP is 1, and is not inverted when 0. When there is no parity error, the value of the FF after final transmission is 1 if the register is divided into even-numbered parts. For this purpose, the value of the FF is sent out as a byte mark error signal BME to judge an error.

Description

[Detailed Description of the Invention] The present invention buffers data sent in bytes from an input/output device in an input/output control device, aligns it to an n-byte boundary, and sends it to a higher-level device (channel or processing device). This invention relates to a parity check method for byte marks added to data to indicate valid byte positions when

Generally, when transferring such data, data and byte marks are divided into ``tn bytes'' and transferred multiple times, but conventionally, when creating byte marks, parity is generated for each byte mark. Buffer it and
A parity check is performed when sending to the upper device,
If it is normal, the parity is added as is and sent out, and if there is an error, that fact is reported to the host device. Therefore, the byte mark register requires a parity bit, which has the disadvantage of increasing hard violet.

The purpose of the present invention is to eliminate such conventional drawbacks, and does not have parity pits for each transfer portion, but performs a parity check using only the parity for all sent portions. This will be explained below with reference to the drawings.

Figure 1 is a block diagram of an embodiment of the present invention.
O~3 are 4-byte data buffer registers each, and To5. Data is written from the input/output device in 1-note units. BMKO-3 is a 4-bit no(ite).

A mark register in which each bit indicates the validity of the byte in the corresponding DBR.
Every time data is written to, @1" is set at the corresponding bit position. DAB uses the number bit address register to instruct which position in DBR the data 'i' from the input/output device is to be stored, and writes 1 byte. It is incremented by 1 each time it is entered.PC) is a parity generator that generates a parity for a 4-bit byte mark, and pc is a harness check circuit which will be described in detail later.

Transfer between the host device (for example, 0PU) is performed in 4 bits, and a maximum of 16 bits is transferred in 4 times. DBRO-3 and BMKO~3 each have a shift register function. When transferring to the CPU, the data is transferred from the DBR3 and BMK3 after 7 steps between each register.

] (The parity for the mark BMK is generated by the generator PG, and the parity for the mark BMK is
O (default value is @11). That is, this I
FIF is.

This means that the odd parity of the entire byte mark written to BMKO~3 is calculated.0 At this point, when the transfer from the input/output device ends or DBRO~3 becomes full, the CPU
Move on to transfer. In this case, the read signal KX from opσ
Output BMFI of parity generator PO when TRD is present
From C, yyYt is inverted.

That is, if BMP is @II', FP is inverted, and if BMP is @□IT, it is not inverted. This is performed a maximum of four times, which corresponds to the parity of the entire bite mark plus the parity of each of BMKO to 3. Therefore, if there is no parity error, the value of the FF after the final transmission should be ``1'' (because the register has 4 stages and is divided into even numbers). Therefore, if the value of FF is sent as the byte mark error signal BMIIII in synchronization with the transfer end signal TRND from the OPU, cpt
The presence or absence of an error can be determined on the r side.

As described above, in the present invention, when writing to BMKO~3, the parity of the entire byte mark is counted as 't11, and when sending to the CPU, the parity of each bit is generated and added to the value of 'QFF. Since the integrity check can be performed on the entire byte mark, there is no need for bits for retention in the buffer register, and hardware can be reduced.Also, transfer with cptr requires only 1 bit.
Since 6 bytes is one unit, 4)
Even if error checking is performed by attaching parity to each byte, processing such as data retransmission is generally performed in bytes, and error detection is also 16 bytes (it is sufficient if it can be done in bytes). j＞夛、In fact, it also has the effect of being easier to control.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a detailed diagram of the integrity check circuit shown in FIG. , BM! [) to 3 are byte mark registers, DAB
is the address register, PG is the parity generator, and PC is the parity check circuit.

Claims (1)

[Claims] It has a buffer register that stores data from an input/output device and a byte mark register that stores a byte mark indicating the effective byte position in the buffer register. The input/output control device for transfer is provided with a means for calculating the parity of the entire byte mark to be sent and a means for calculating parity for each byte mark to be sent. A byte mark parity check method characterized by checking for parity errors based on the above-mentioned overall parity.