JPS585445B2 - Shingouno Jikanjikuhenkansouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time base conversion device for analog signals such as audio signals.

In general, in tape recorders, etc., even if a magnetic tape recorded at a normal tape running speed is run at a speed faster or slower than the normal tape running speed, if it is run at the normal tape running speed. It is necessary to perform so-called time axis conversion in order to obtain reproduction frequency characteristics similar to the above.

Now, the time axis conversion in tape recorders etc. is TSC (
It is a function that allows you to arbitrarily change the playback speed of a magnetic tape on which audio is recorded, and also performs frequency conversion so that the playback frequency is the same at any tape speed. .

In order to realize such a function using electrical circuit technology, the time axis of the reproduced electrical signal must be expanded or compressed depending on the reproduction speed.

Conventionally, this type of technology involves appropriately sampling the reproduced signal, converting it into binary code, temporarily storing it in a digital memory, and reading and demodulating it at an appropriate speed according to the reproduction speed. There was a method of restoring the audio signal to a different time axis, making it the same frequency as the original signal but with a different time axis.

In principle, a memory element is necessary for time axis conversion, but
Devices based on such digital technology have the disadvantage that the central memory has a large capacity, the circuit configuration is complex, and it is difficult to realize it at a practically profitable cost.

The present invention provides a novel time axis conversion circuit device that can realize the TSC function with a relatively simple circuit configuration, and the technical content thereof will be explained below.

In FIG. 1, reference numerals 1 and 2 denote write and read delay devices that sample input analog signals using clock pulses and store and transfer the sampled values, for example, BBD (Backet).
A semiconductor memory element called Brigade Device is used.

The device of the present invention first inputs the audio signal into the BBDI for writing, and when the storage capacity is reached, switches the clock to an extremely high frequency to transfer the contents to the BBD 2 for reading in a short time, and then, The data is read from the BBD2 at an appropriate lock frequency and simultaneously written to the BBDI again.

This will be explained in detail according to FIG.

Common contact dd' of changeover switches 3 and 4 to move first
is connected to the contact ff' as shown in the figure, the signal of the magnetic tape 6 reproduced by the head 5 is amplified by the preamplifier 7, and this audio signal is further supplied to the BBDl having N elements through the analog gate 8. Ru.

The analog gate 8 opens when the output of the N-ary ripple counter 9 is "H" (High).
The output of the clock pulse generation circuit 10 is connected to the AND gate 11
, controls a two-phase clock pulse generation circuit 13 via an OR gate 12.

Generally, BBDs perform storage transfer operations using two-phase clock pulses with a 180° phase difference, and this device also uses two-phase clock pulses with a frequency that is half the control clock pulse.
Two-phase clock pulse generation circuit 1 for obtaining phase clock
3 and 14 are used.

Such two-phase clock pulse generation circuits 13 and 14 are as follows:
For example, as shown in FIG. 2, it can be easily constructed with a flip-flop 15 and some logic gates.

As shown in the figure, a rectangular wave f with a duty of 50 is repeatedly applied to the control input terminal a while the J- terminal of the flip 7-amp is kept at a high level at all times.

When input, the two-phase output terminal C receives a control input clock pulse f as shown in the figure.

Duty 25 with a phase shift of 180° at half the frequency of
The relevant clock pulse is obtained.

Note that 16 is impark, 17 and 17' are NAND gates,
18 and 18' are inverter amplifiers; 19 and 19' are amplifiers for converting the signal level to the clock level of BBD1 and BBD2, respectively.

When the frequency of the clock pulse of the first clock pulse generation circuit 10 which determines the write sampling frequency is fina, the output clock frequency of the two-phase clock pulse generation circuit 13 becomes fin/2, so the sampling frequency of the BBD becomes fin/2, and the frequency of the BBD is fin/2. When the number of elements is N, the delay time until the input signal reaches the final output stage of the BBD is N/fin.

Note that since the BBD generally repeats sampling and transfer, the storage capacity is N/2 for the number of elements N.

The clock output of the OR gate 12 is supplied to a two-phase clock pulse generation circuit 13 and also supplied via an inverter 20 to an N-adjustable pull counter 9, which inverts its output every time it counts N clocks.

When the counter 9 counts N clocks fin of the clock pulse generation circuit 10 after BBDI starts writing, BBDl has just completed writing to its full capacity, and at the falling edge of the Nth clock. The output of the counter falls to the L"Low level, and the analog gate 11 is closed to cut off the input audio signal and the input sampling clock. At the same time, the A-ND gate 22 is opened via the inverter 21 for high-speed transfer. Output clock pulse f of the clock pulse generation circuit 23.

The contents of B-BDl are transmitted through the cascaded amplifier 24,
Like BBDl, it is transferred to BBD2, which has N elements.

The high-speed transfer clock pulse is supplied to a two-phase clock pulse generation circuit 14 similar to the two-phase clock pulse generation circuit 13 through an OR gate 25, and therefore the BBD2
performs a write operation in synchronization with BBDI, and
The output of is stored sequentially.

In order to transfer data from BBDI to BBD2 in this way, an appropriate synchronization relationship is required between each phase clock output of the two-phase clock generation circuits 13 and 14. For this purpose, for example, the two-phase clock pulse generation shown in FIG. In the case of a circuit, it would be sufficient to apply an appropriate reset to the R terminal 26 of the flip-flop at the time of start, but such a synchronous circuit is omitted because it is technically easy and is not shown in the drawings.

During this transfer period, analog gate 2 cascaded to BBD2
7 is closed like 8 above, and BBD2 during high-speed transfer.
The output of is cut off.

Clock pulse frequency f for high-speed transfer.

Since it is better to have as high as possible, the value is selected to be as high as possible based on the characteristics of BBD.

Specifically, common BDs respond well to 500 KHz.

Now, if the number N of elements in BBDl and 2 is 512, then f.

-500KH2 is approximately 1m5EC (5121500X1
03), the audio output will be blank, but there is no problem in terms of human auditory characteristics.

When the high-speed transfer is completed and the counter 9 counts N clocks, the output of the counter 9 is inverted again and becomes High.
become.

As a result, analog gates 8 and 27 open, and AND
Since the gate 22 is closed and the AND gate 11 is opened, the BBDl again writes the audio signal according to the clock of the write clock pulse generation circuit 10.

At the same time as the output of the N-ary counter 9 becomes High, AND
Since the gate 28 is opened, the memory contents of the BBD2 are read out by the reading clock pulse generation circuit 29 having the frequency fout, and the contents transferred from the BBD1 are sequentially read out.

The signal read out in this way is smoothed by a low-pass filter 30 via an analog gate 27, an amplifier 31, an attenuator 32 such as a variable resistor, an amplifier 33, and a speaker 34.
is supplied to

In the present invention, the read clock pulse generation circuit 2
While the clock frequency fout of the write clock pulse generation circuit 10 is constant, the clock frequency fout of the write clock pulse generation circuit 10 is constant.
in is controlled in relation to the running speed of the tape 6.

That is, if the ratio of the tape's changed running speed Sv to the tape's rated running speed Ss, that is, Sv/Ss, is P, then the write clock frequency fin and the read clock frequency font
The oscillation frequency fin of the clock pulse generation circuit 10 is changed by appropriately controlling the terminal 35 so as to maintain the relationship fin=P·fout...1 during this period.

This control operation is of course performed in conjunction with the operation for determining the running speed of the magnetic tape 6.

Specifically, for example, the clock pulse generation circuit 10 is configured with a voltage controlled oscillation circuit VCO, and this control voltage is applied to the terminal 35.
An appropriate method is to simultaneously control the speed of a drive motor (signal sending device) (not shown) for the magnetic tape 6.

As a result of the write clock frequency fin being P times the read clock frequency fout, the time axis of the output audio signal is converted to 17P with respect to the input audio signal.

However, the audio signal generated by the magnetic head 5 is originally P times the original sound frequency (the audio signal frequency when reproduced at the rated speed), and therefore, by using the device of the present invention, the tape running speed differs from the rated speed. Despite this, the frequency of the output restored audio signal is equal to that during rated speed playback.

For example, when P>1, high-speed reproduction is performed, and the tape 6 runs at a speed (P times) faster than the rated speed.

Therefore, the input signal frequency to the BBDI is P times the original sound frequency at any instant.

As mentioned above, this audio signal is sampled at a sampling frequency of fin/2.

Every sampling time N/fin seconds, these N/2 analog quantities are almost instantaneously (with respect to the sampling period) transferred as they are to the BBD2, and then each bit information is transferred to the fo
It is read out at a frequency of ut/2 (-fin/2P).

As a result, the time axis is expanded by P times, and the restored signal frequency becomes equal to the original sound signal frequency.

The number of signal bits read from BBD2 is (N/fin)X(fin/2P)-N72P-2, so the signal for each cycle is discarded.

Since P=1 indicates that the tape running speed does not change, switches 3 and 4 are connected to the ee' side, and this circuit device is not used.

P<1 means slow playback, the tape runs slower than its rated speed, and the input audio signal frequency is P times the original sound frequency at every instant, but is processed in the same way as BB.
The restored signal frequency, which is the output of D2, undergoes time axis expansion by P times, that is, time axis compression by 17P times, so that it becomes equal to the original sound frequency.

N/2 information is clocked out at a sampling frequency of font/2.

That is, since the signal is extracted in synchronization with the clock pulse, a period of time in which there is no audio occurs for each sampling.

For example, N=512 bits, fout=40) (Z, P=
For 1/2, this blank time is 12.8m5EC, which is the same <12. &nAlthough this is a repetition of the audio part of 5EC, it only causes a slight decrease in sound quality and sound pressure, and is practically no problem.

Generally, the frequency band of human voice signals is 200Hz to 5K.
H2, the sampling frequency fin/2 is required to sample and further synthesize the audio signal as described above.
, fout/2 need only be twice the frequency to be handled according to the sampling theorem.

This device takes fout/
2 is 20KHz.

The fin must also be controlled according to the input signal frequency so that the highest frequency of the input signal can be sufficiently sampled.

However, in this device, while the font is constant, the write clock frequency fin is changed according to the running speed of the tape, and fin-Pfout follows the increase or decrease in the frequency of the input signal. Since the relationship is maintained, the sampling theorem is satisfied for fin as well as for fout.

Note that although the above description has been made regarding the conversion of the audio signal time axis, it goes without saying that the same principle can be applied to video and other signals other than audio signals.

In the present invention, two charge transfer elements are used for writing (A) and reading (B), respectively. First, analog signals are stored in A with an appropriate sampling clock, and then the stored contents are stored in A. It is transferred at high speed to Party B, and at the same time as Party A reads it again, Party B outputs it with an appropriate lock. Furthermore, the ratio of Party B's clock out frequency to Party A's sampling clock frequency is determined based on the rated tape running speed. By making the ratio the same, it can be restored regardless of the tape running speed.

The signal frequency is made equal to that of the original sound, and these techniques make it possible to convert the time axis of an audio signal over a wide band using a relatively small-capacity charge transfer element, providing an extremely effective technique.

For example, a plainly recorded tape. Even if you double the running speed (halve the playback time), the frequency returns to its original level, so the clarity remains unchanged, allowing you to listen to lecture tapes, narrative tapes, various information tapes, etc. at high speed, and it is much easier to listen to than before. You can understand the content in half the time.

Furthermore, even if the tape running speed is halved (double the playback time), the clarity remains the same, making it possible to take short notes while listening slowly to transcriptions of meeting minutes, dictations, interviews, etc. , it is also extremely useful for practicing English conversation, etc.

As described above, the present invention connects the write delay device 1 and the read delay device 2 in series, and has the following effects.

In other words, (a) In a conventional device in which two storage devices are connected in parallel and switching is controlled between the two storage devices using an analog switch, if there are variations in the characteristics of these two storage devices, the variation causes the first storage device to A difference occurs between the signal passing through and the signal passing through the second storage device, resulting in a difference in the magnitude of the output signal each time the first and second storage devices are alternately switched.

On the other hand, in the present invention, since the write delay device 1 and the read delay device 2 are connected in series, all the signals pass through the delay devices 1 and 2. Even if there is variation in characteristics, the output signal is not affected by this variation number.

In a conventional circuit that connects two storage devices in parallel, an analog switch for signal switching must be connected to the input side and output side of the storage device due to the circuit configuration. has two memory devices connected in series, and the analog switch (gate) on the output side can be omitted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a signal time axis conversion device of the present invention, and FIG. 2 is a circuit diagram showing an example of a two-phase lock pulse generation circuit used in the device. 1.2...delay device, 6...magnetic tape, 10...first clock pulse generation circuit, 2
3...Second clock pulse generation circuit, 29...
...Third clock pulse generation circuit.

Claims (1)

[Claims] 1. A first clock pulse generation circuit that generates a clock pulse whose frequency changes according to the signal transmission speed of the analog signal transmission device, and an analog input signal using the clock pulse or a clock pulse formed in response to the clock pulse. a write delay device for sampling and storing and transferring the data; a read delay device connected in series with the delay device; and a second clock pulse for generating a transfer clock pulse having a higher frequency than the first clock pulse. a third clock pulse generating circuit that generates a clock pulse to be applied to the delay device in order to read the memory contents of the read delay device; and an output clock pulse of the first clock pulse generating circuit or the A counter circuit that counts the output clock pulses of the second clock pulse generation circuit and an input control gate connected to the input side of the write delay device are provided, and a predetermined amount of signals are stored in the write delay device. At the same time, the input control gate is cut off by the output of the counter circuit, and the transfer clock pulse or a clock pulse formed in response to the transfer clock pulse is applied to the write delay device and the read delay device. Transferring the memory contents of the write delay device to the read delay device at high speed, and then turning on the input control gate by the inverted output of the counter circuit, and responding to the output clock pulse of the third clock pulse generation circuit or the pulse. A signal time axis conversion device which reads out the stored contents of a readout delay device using a clock pulse formed by the clock pulse.