JPS5851571A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakdown of an FET which is produced by the breakdown of a boundary between an operating layer and a high resistance layer by doping doner impurity on part of the high resistance layer. CONSTITUTION:Doner impurity is doped in the vicinity 7 of the position corresponding to the gate electrode 2 of a buffer layer or a semi-insulating layer 6. Thereafter, an operating layer 5, a source electrode 1, a gate electrode 3 and a drain electrode 3 are formed. As a result, since the gradient of a depletion layer 4' becomes smooth, the electric field intensity becomes weak in the region A that the electric field is the highest in the operating layer as compared with the conventional device, while the length of the region A becomes long. Accordingly, since the ultrafine current which flows through the layer 6 flows through the region of the layer 6 in the wider range than the conventional device, the resistance in this region increases. Accordingly, the electric field in the boundary B can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for increasing the breakdown voltage of a semiconductor device such as a field effect transistor, and more specifically, to a method for increasing the breakdown voltage of a semiconductor device such as a field effect transistor. Concerning a method of manufacturing a semiconductor device in which the element is made to have a high withstand voltage as a 1fII mold. - Conventionally, for example, methods for increasing the withstand voltage of FIC technology, that is, increasing the drain-source voltage at which breakdown occurs, have been achieved by using a recess structure or drain There has been a method in which a Kn+ layer is provided below the base electrode. These methods are effective against breakdown caused by electric field concentration near the drain electrode, but they are effective against breakdown that occurs at the interface between the active layer and the high resistance layer at high gate voltages. Such breakdown, which is ineffective, may lead to dielectric breakdown of the high-resistance layer, which seriously affects the reliability of PET. ``In this sense, a new method for increasing the voltage resistance of PET is required.

Conventional shock) Kibari Yagut type FIT (Mmll
The structure of FIT)y#F1 is shown in Figure 1. Same figure lol
A, the buffer grown by vapor phase epitaxy, etc. is more difficult to process than the high-resistance layer (for example, Gllm), which is an insulating substrate.
An active layer 5 is formed on the active layer 5 (KCr-doped) 6, and a source electrode 1. Gate electrode 2. A drain electrode 3 is formed. A depletion layer 4 exists under the gate electrode 2 in the shape shown in the figure, and the wrinkled depletion layer 4 changes its shape depending on the voltage to control the source-drain current. When the gate voltage is high, the depletion layer 4 spreads to near the high-resistance layer 60, so that the source-drain current flows in a narrow region indicated by the arrow mark in the figure.

This region has the highest electric field in the active layer. At this time, a small amount of current flows through the path shown by the broken line in the figure, that is, from the active layer high-resistance layer interface B through the high-resistance layer region C to the active layer high-resistance layer interface. However, since the area C4 is very narrow, the high resistance layer area C4 where the minute current flows
Don't keep one book9. As a result, a high voltage is applied to the interface 1, and breakdown occurs in this region 1. This breakdown destroys the high resistance layer 6. As a result, current flows in the high resistance layer 6, making it difficult to control the source/drain current using the gate voltage.
function is lost. This fact leads to a decrease in the reliability of the semiconductor device.

The purpose of the present invention is to solve the above-mentioned problem of increasing the breakdown voltage of semiconductor devices such as FICT, and for this purpose,
The inventors of the present application provide a method of manufacturing a device with high breakdown voltage, which can prevent destruction of an FET caused by breakdown of the interface of the high resistance layer in the active layer by doping a portion of the high resistance layer with a donor impurity.

do.

FIG. 113 is a diagram for explaining the present invention in detail. This figure is a schematic equivalent circuit corresponding to the case where a constant voltage is applied between the source electrode 1 and the drain electrode 30 in the case 71 of FIG. Referring to the same figure, since each active layer high-resistance layer interface is considered to be one circuit component, it is fitted with a box in the figure. Also, since the high-resistance layer C is equivalently considered to be a resistor, the figure It is expressed in the symbol of resistance.

In the figure, E is a power supply for applying a constant voltage between the source and drain.

Using FIG. 3, the cause of the breakdown occurring at the interface B of the active layer high resistance layer can be explained as being that the voltage applied to the box BK is too large. Therefore, preventing breakdown [
tX, increase the value of resistance C.

It is necessary to reduce the voltage drop in box BK.

Based on the above-mentioned considerations, the inventor of the present invention increased the width of the active layer region formed by the depletion layer 4 and the high i resistance layer 6 shown in the MI diagram (and We have developed a method that can reduce the voltage applied to the active layer high-resistance layer interface by increasing the length of the flowing high-resistance layer region C along the interface V-.

FIG. 2 shows an embodiment of the invention. In this figure, the same parts as in Figure 1 have the same symbols! It is shown.

Referring to FIG. 2, donor impurity ## (silicon or sulfur) is added at a concentration of 5 x 10'' to the vicinity of the position 7 corresponding to the gate electrode 2 of the breadlayer or semi-insulating layer 6 grown by vapor phase growth or the like. Doping with I x 1G'' (c(・ ) by ion implantation method etc. After that,
Operation layer 5 using conventional techniques. Source electrode 19 Gate electrode 2. A drain electrode 3 is formed. In such a device,
Since the depletion layer has an impurity region buried by the donor impurity injected into the antilayer 6, the depletion layer has a shape as shown by A in the figure. ), the slope of the shape is gentler and the width of the area is wider.

As mentioned above, in the device of the present invention, the slope of the depletion layer is gentler, so compared to the conventional device, the electric field strength is higher in the region where the electrolysis is highest in the active layer (the region indicated by the square in Figure 1). While it becomes weaker, the length of region A becomes longer. Therefore, the minute current flowing through the high-resistance layer also flows through a wider range of the high-resistance layer region than in the conventional device, so the resistance in this region (corresponding to C in FIG. 3) increases. As a result of the above, the value of the resistance C in FIG. 3 can be increased, and therefore the electric field at the interface can be reduced.

As explained above, by implanting donor impurities into a part of the high-resistance layer, the slope of the depletion layer is made gentler, the voltage applied to the S layer high-resistance layer interface is reduced, and breakdown occurring at the interface is prevented. As a result, the reliability of the high voltage semiconductor device can be improved.

By the way, in the present invention, as shown in FIG. 4, by changing the donor impurity implantation region, the shape of the depletion layer can be changed and a sufficiently high breakdown voltage in FEYK can be realized. The method of the invention can be applied to manufacturing FETs other than those of this embodiment, and greatly contributes to improving the reliability of semiconductor devices.

[Brief explanation of the drawing]

Fig. 1 is a schematic cross-sectional view showing the structure of a FET in the prior art, Fig. 2 is a schematic cross-sectional view showing the structure of a 1rNT in the present invention, and Fig. 3 is an equivalent circuit between the source and drain electrodes in FIG. 4 is a schematic cross-sectional view of an FET in another embodiment of the present invention. 1... Source electrode, 2... Goo F electrode, 3... Ton-in electrode, 4. A, 4'・τ・depletion layer, 5・active layer, 6・−high resistance layer. 7. τ - Donor impurity implantation region Patent applicant Fujitsu Ltd. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] In a method of manufacturing a semiconductor device such as a field effect transistor, a region having a donor impurity concentration of the same degree as that of the active layer is formed on a part of the surface of a high resistance layer under the active layer of the device. 1. A method of manufacturing a semiconductor device, characterized in that the device has a high breakdown voltage.