JPS5850857A - Information reading and recording device - Google Patents

Abstract

PURPOSE:To reduce power consumption by providing plural recording parts and a storage device. CONSTITUTION:A self-scanning type photodetector CS consists of a great number of photodetectors which transduce light inputs into electric signals, and processes those signals in time series. For copy recording, a carriage CA while moving in a direction Q makes a raster scan on information on a platen in a direction P. At this time, recording paper at a recording part moves at a speed equal to the moving speed of the carriage CA in the direction Q to perform recording. Picture information obtained by a read part is sent through a buffer memory to the recording part to perform the recording in parallel to the reading, but the information read once may be recorded after being field in the memory. Plates are connected to the substrate with a heating body of the recording part and they are connected to ink injection pipes respectively. Plates in an odd and an even group shift in position from each other.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for reading and recording manuscript information, and the present invention is a nine-device device with improved reading and recording sections! Ill do it.

FIG. 1 is an example of a heating element drive circuit that can be used in the present invention.
FIG. 2 is a waveform diagram for explaining the operation.

A group is formed by heating elements 1ift~IH32, and a total of 1792 heating elements IRI~56 in 56 groups.
H32 is used, one end of each heating element is a control element, for example, an S6 group with diodes ldl~1d32 as l group, a total of 1792 diodes ldl~56432
It is connected to the. Each diode is connected to pixel information input terminals P1 to P32. Heating elements 181-12
The other end of 132 is connected to group selection signal input terminal D1. Heating elements 281~2H32,...56H1~
56f13j! are similarly connected to the group selection signal input terminals D2 to D56, respectively. As shown in Figure 2, each group is time-divisionally driven by the data unit 1156 to drive each heating element to generate heat. Kii as shown in Figure 2
When the element information p1 and the like are sparsely generated at Dl, it does not require much power to drive them simultaneously, but when 32 heating elements are driven at the same time at D2, a considerable amount of power is consumed.

Figure fg3 is an example of a circuit that solves this problem. In the figure, P
TG is an image information generator, DP (i is a group selection signal generator, RGC is a signal generator consisting of a ring counter or ROM, etc., and the heating element to be driven at the same time is, for example, Elf.
, 119, R17, R25, and at the next timing, add 4 more, for example, [2, I(10, Hlg, 112
This is a circuit for driving 6. That is, Antogame Fm1
- 32 are provided, and only four out of eight heating elements are driven at the same time. With this configuration, the power required to simultaneously drive 32 heating elements is 1/8 compared to the example shown in Figure 2.
becomes. That is, as shown in Fig. 4, 4 out of 8 of the 32 heating elements are driven to first print 4 dots, then print 4 dots of 1 dot 111 ID, and repeat this 8 times. When this is done, line-shaped printing of 3'2 dots is completed. FIG. 5 is a #l perspective view of an example in which 611 drops are formed by the above-mentioned heating element drive circuit.

This embodiment is an example of i^4 version full multi 8 dot/IEm. 56 substrates each having 32 heating elements are bonded to two areas of approximately equal area on the top and bottom of a metal plate H8 which also serves as a heat sink, and 32 grooves are formed on each of the substrates with heating elements 5tt1 to 5s56. Chopped plates JB1~J! 15(
5 are joined. Ink introduction pipes op1 to 0P56 are connected to each plate, and each ink introduction pipe is connected through ink supply pipes op and gp connected to an ink tank I'rK. DAI~DM5
Reference numeral 6 denotes a control element array, for example a diode chip, which is connected to each 9-wire on the substrate with a heating element.As shown in Figure 6, the control element chips are divided into two groups, an odd number group and an even number group, and the first chip It is preferable to place the third chip next to the second chip and the 40th chip (hereinafter referred to as uniform) next to the chip No. 2, since it is possible to uniformly secure the dot spacing Q of 8 dots/home as shown in Figure 6. .

Figure 7.8 is a schematic diagram of a copying machine or facsimile device to which the above-mentioned full multi-recording head and time-division drive circuit are applied. It has a reading section RD. A document table PG made of glass or the like is formed above the reading sRD, and a document is placed on the document table PG.

At the top of the document platen PG is a document platen cover PK that fixes the original.
is provided.

At the bottom of the document table PG, there is a light source BL that illuminates the document, a reflector RM that is provided so that the light emitted from the light source BL effectively illuminates the document table PG, and a self-contained light source that has a large number of light receiving elements arranged in a straight line. An optical unit LB including a scanning light receiver CS and an optical lens for forming an image of a document on the light receiver CS is provided integrally with the light receiver CS. This optical unit) L8
The light receiver cs11 is fixed to the carriage C. The carriage CA moves forward in the Q direction or backward in the warp direction by a screw G rotated by the drive of the motor MO on the guide rails R1, R2-H. It is also assumed that the main scanning direction of the self-scanning light receiver cm is sequential scanning in the P direction in the direction of the original. Therefore, by moving the carriage CA (in the scanning direction Q), the information of the original placed on the document platen PC is sequentially imaged onto the light receiver CB, and if the light receiving elements are sequentially read out (main scanning), From this, it is possible to obtain sequential signals obtained by raster scanning the original.

In this embodiment, the document table PC is fixed and the carriage CA
Although the carriage C is movable, a structure in which the carriage C is fixed and the document table PG is movable may be used. When performing copy recording, the carriage C raster scans the information on the document table in the P direction while moving in the Q direction. At this time, the recording paper in the recording section is recorded in the R direction while moving in, for example, the 6 directions in FIG. 5 at a speed equal to the speed at which the carriage C moves in the Q direction. The information obtained by the reading section is sent to the recording section P in Fig. 5 via the buffer memory, and recording is performed in parallel with the reading.For example, page information once read is filed in the memory. You may record again later.

The self-scanning photodetector cm consists of a large number of photodetectors that convert optical input into signals all at once, and can process these 4tii signals in time series. For example, C
There are OD image sensors, M08 type image sensors, etc. In Jin's copying machine, the width of the original platen in the P direction is 216 mm.
1EII (A4, lateral direction and #1 are equal), and consider a case where a 1728-bit COD linear image sensor is used as a light receiver. The output recording section PH is 1792 dots due to signal processing.) If a 224 m wide full-line multi-head is used, the image sensor and head are 8 dots/W.

You will be able to gain the power of enlightenment. Now, the 28 block arrays above the heat sink plate are the odd number group, and the 28 block arrays below are the even number group, and the gear lancers C8 in the vertical direction of the odd and even groups are 1728 as described above.
Each scan twin is blown by a bit twin senna and outputs nine voltage levels depending on the image information. This voltage level is determined by the digitizing circuit D shown in FIG.
When it is a level, it is converted into a binary value, and when gradation (half tone) is required, it is converted into a multivalued signal using an analog or digital converter. Considering binarization for simplicity, the digitizing circuit D compares the output voltage of the CCD sensor CB and the reference voltage (slice level) t! It consists of a comparator color and outputs a high level or four-level binary signal depending on the input voltage. This digitized nine data is 3
It is serially input to a 2-bit 77 register, converted into parallel data, and output, and thereafter processed in units of 32 bits. The data output in parallel by the shift register, RIAB, is once held in the 32-bit latch circuit L1, and then
Transferred to memory section. The memory section consists of a memory Ml and a memory M2, where the memory M1 is an odd-numbered prick group J1.
．． J13.・- data is stored in memory M2 in even block -J112. Store the data of JB4°-. The data held in the latch circuit L1 is stored in memory every 32 bits M.
1 and are alternately placed in memory M2. Memory M l.

M2 is, for example, RAM (random access memory) C
These are OD memories, magnetic memories, etc., and their storage capacities are 32 bits for memory M1 and 56 bits for memory M2. Memories Ml and M2 consist of 1 word with 32 bits, so the memory Mltil word and memory M2 consist of 1 word.
It consists of 792 words. In addition, memories Ml, M2
The output of enable signal 1/1lL4. When L5 is at the 1 level, it is assumed that the state is in a high impedance state, a so-called three-state state.

Selectively from memory Ml and M2! ! The extracted nine data are held in the 32-bit latch circuit L2. At this time, the states of the memory M1 and the memory M2 are such that when one is in the L write state, the other is in the read state, and the latch circuit L
When one of L and L2 holds data in memory M1, the other holds data in memory M2.

Therefore, the data in the memory M1 and the data in the memory M2 are alternately held in the latch circuit L2.

The nine data held in the latch circuit L2 are 32 NAND
Goo) is output to NGI ~ NG32, but NanoDog -)
NO2-)! G32 selectively operates the transistors 〒Pi to 〒P32 when the timing PG of the print command signal line LIO is outputted from the control circuit CC. The collector terminals of the transistors TPI to P32 are connected to data input terminals P1 to P32 of the recording section P). When adopting the power-saving drive system as shown in Figs.
-Mu32 may be substituted. The 56 selection signal input terminals D1 to 056 of the recording sP section are the two states D1 to TE D.
56 and is connected to the collector of transistor TI)
1~? 056 is sequentially scan-controlled by the output of the decoding circuit DC. The decoding circuit DC is 6 lines route 5
It is a 6-line depuder and is controlled by 6 signal lines 1.11 from the control circuit CC. The control circuit CC is a circuit that generates rounding signals to control the above elements.The reference clock is made of a crystal oscillator.

Each control signal will be explained using the tie charts in Figure 8 and Figures 9 and 10. -ccHc#i On the signal line L1 as a plow pulse, for example, a start pulse φ at the beginning of line scanning, a set clock φ of output amplifier 09, and a two-phase shift clock 1, φ for the shift register in the CCD.
2 (not shown) can be seen. The pulse interval of the start pulse φ buying in FIG.
Output from 8mcc. Reset F evening φ1 is CC
It is assumed that image information is outputted from the CCD when the V set, V, and φ blades are at the 11 level with the 9 signals corresponding to D and K.

Therefore, as shown in FIG. 9(3), the signal line L2 from the control circuit CC to the shift register 8 is connected to a transfer signal that rises when the reset clock φli-level is at the reset clock φli- level with the same period as the reset clock φ. SC ward is given.

In the control circuit iC, this transfer signal 8CIC is counted and 3
Latch circuit Ll & latch circuit L every 2 bits 21/
Ca-doc o tsu/ L CK 1 t L CK 2
signal 11L3. L911C gets 4. The load clock LCK1 given to the latch circuit L1 is as shown in FIG.
4) Shift clock of 32 pulses as shown in K■CX
is uttered and then stands up.

On the other hand, the first memory enable signal that selects the memories M1 and M2 is applied to the four terminals of the latch circuit L1, as shown in FIG. 9 (5).
After the clock LCK1 rises, it goes to the negative level to enable the program to operate.While the lock enable signal 1)in is held at the 11th level, the latch circuit L2 The applied load clock L0 section 2 must rise.

The read/write signal R/W that controls the writing and reading of memories Ml and M2 is as shown in Figure 1i9 (8).
CD reset signal signal layer 32 This is a signal whose level changes every 2 pulses, and as shown in Figure 10, 2
The level changes 8 times. As mentioned above, the memory M1. M2
Since the filling and setting operations are reversed, when the signal R/W given to the memory M2 by the signal -Ll is as shown in the figure,
The memory Ml is inverted by the inverter 1 (No. 1 is provided at the signal layer "Lg").

) Signal PGFi given to NGI to NG32,
<1 determines the energization timing and energization time to the heating element, and as shown in FIG. 9 (7), it is applied on the signal line LlO after the load clock LCK2 of the latch circuit L2. The external signal PG is also generated every 32 pulses of the reset clock φR.

When using the 1 drive method as described above, within the CC (Z) I
This PG 4ti by J song counter or ROM
The issue is further time-divided into the above-mentioned Andogutom 1 to Mu3.
If you apply 2, there will be a storm. The binary signal input to the decoding circuit DC is a 56-decimal signal in -scanning line, and C
CD Reset Signal - This is the output of a 56-decimal kakunta that counts up by one every time the wing counts 32 pulses. Therefore, 569 transistors D1~! 056 is turned on one by one every 32 pulses of the reset signal layer 1L, and sequentially generates selective driving pulses D1 to D56 in FIG. 91 to generate heat in the heating element. Here, regarding the operation of the JIs diagram, see Section 9.1.
To explain in more detail according to Fig. 0, first, after the COD start pulse φ starts to be generated, at the p- level in the second half of the first cycle of the write signal R/W (when it is at a high level, the last two pulses of the previous scanning fin are In the first half of the 1g2t cycle of the 0th order, the rounded data of the heating element group of the odd block Dm1 is written from liR, Ll to the memory corresponding to 1g2t cycle. The data written in the memory M1 is read out to the latch L2, and the data for the second block Dm2 is written into the memory M2. Furthermore, in the second half of the 1f and 2 cycles, data for the M3 boot DA3 is written into the memory M1, and data from the second boot DA2 is read out to the 22nd boot L2.

Thereafter, the same operation is repeated, and the readout for the am block DA55C of the odd block group and the readout and reading for the block ROM 56 after kk of the even block group are performed as the CCD scans the next scanning line. I do it when I'm there.

Here, the memory M1 is a 1 word x 32 bit memory as described above, and the data that has been written and read out is read out in the next cycle, whereas the memory M2 is a 1 word x 32 bit memory.
Ft& data is read out in 64 scanning lines (
1792 read/write cycles). That is, the data given to the even numbered blocks is data 64 scan lines before the data currently being read by the COD.

This is rounding, as described above, where there is an interval corresponding to 64 lines (8 lines) between the odd number block group and the even number block group.・1 For this reason, address selection is necessary for memory M2.

Figure 11 shows the general address cost of the memory M2, and the address decoding circuit M2 is configured in the memory M2, and the block counter BC and line counter LC are configured in the control i41 circuit CC.

Memory M2 has a storage capacity of 56 bits and its contents are 32 bits.
One word (one boot stock) is made up of bits, and a unit of 28 words is called one line (896 pits), making up a total of 64 lines.

Block counter! The IC is assumed to be a 28-decimal counter, and the input clock operates at the falling edge of the read/write signal R/W. The state of counting by the block counter isc is shown in FIG.

The line counter LC is a 64-decimal counter, and the carry second output (carry) signal line J of the counter BC.
Count F2 as an input clock. Block counter Be output IIIj3, line counter LC output @1
4 is a signal corresponding to address selection 4i L @ in FIG. 8, and is decoded by address decoding circuit M2 to select a memory. In memory M2 C, - line, m
After writing to the address of the block, the output of the block counter BC increases by 1, and the address of the (tm+1) block is read. This completes one read/write cycle.) In the next read/write cycle, the output of the block counter BC increases by 1 and reads the address of the (tm+1) block.
@+1) Write to the block address. Thisζ
When Peng reaches 28, it returns to 0 and accesses the next line, and when Peng reaches 64, it returns to 0 line.

FIG. 12 is a diagram showing the state of the image information of the original GK and the state of data transition in each latch and each memory.

The 32-bit datum l loaded into the latch circuit LIK at the current time teIK is written into the memory M1 at the time te2. Also, at time 2, 32-bit data A2 following datum 1 is loaded with latch LIK. Time NT
3, the datum l of the memory Ml is transferred to the latch L1, the datum 2 of the latch Ll is stored in the memory M2, and the latch LIK is transferred to the latch L2 at time T4, when the next datum 3 is stored. Data x2 is programmed, datum 3 of latch L1 is written into memory 1, and datum 4 is loaded into latch LIK.

After that, repeat the same operation, and now the data is X2゜x4.
is the current CCD scan position M1. Mu2-yosho 64
This is information that was read before the line and stored in memory M2.

FIG. 13 is a flowchart for easily explaining the operation in the trench mentioned above.

! Figure s14 shows the reading section RD and recording gp according to another embodiment.
It is a figure which shows the example of arrangement|positioning of u. As mentioned above, the self-scanning photodetector consists of a large number of photodetecting elements that convert optical input into electrical signals, and can process these signals in time series. It consists of four sensors CCDI to CCD4, and the length L of the effective light receiving part of one sensor is 12-8 inches (25 μ x 5 true 2 bits).

With this CCD sensor, the width of the document table in Figure 7 in the P direction is 20 mm.
5B, and to cover this, a lens optical system with a reduction magnification of 4 times may be used. In this case, the resolution of the heka sensor is 10 dots/s since the sensor receives light with a total of 2048 bits.

Therefore, the recording part PH is also 10 dots) 7m, that is, III
Each unit consists of 10 heating elements.

As mentioned above, the recording section PH is provided alternately above and below the heat sink plate H8, and these upper and lower blocks form a full-line multi-recording head, for example, 2048 inkjet nozzles are arranged in 4 blocks TJB1. ~
Each block consists of 512 heating elements. As shown in the figure, the heat sink plate H
The block installed under 8, (1st Pro YP Ding J B
IX 3rd block JB3) and the block installed above (
It is assumed that the gap interval between the oriices in the vertical direction of the second block TJB2 and the fourth block TJI14 is 28 degrees, that is, 28 G lines.

If a copying apparatus is configured for such a recording head by arranging sensors horizontally in a line (or using a 2048-bit line sensor) as in the previous example, image information corresponding to the Oriice gag interval, i.e. As mentioned above, it is necessary to have a memory for 2801 bits, and in the example shown in FIG. 5, a second memory M2 for 56 bits is required.

However, in this embodiment, by adopting a sensor arrangement that corresponds to the head arrangement as shown in FIG. 14, memory loss can be avoided. ! ! This results in a dangerously simple system configuration. That is, when the reading section RD is arranged like the one shown in FIG. 14, the CCD sensor C is moved in the q direction in the figure.
8 and drive the recording section P)I with that information. Here, in FIG. 14, CCD sensors CCD2, CCD4 and C
The vertical spacing of CDs 1 and 3 is the 15th block of recording section P■.
The figure is a diagram showing a drive circuit of the recording section PR in FIG. 14. IHI-4H5t2tf heating element, ldl~44512
is a cross-talk prevention diode 0 heating element fi
There are a total of 2048 ef blocks, and these blocks are made up of 4 blocks (M14 diagram 1st block TJBI to blank 4 block TJ B4) consisting of 512 blocks. The 512 heating elements in each block constitute 1,32 time-division wiring with 1716 duties. Therefore, stripe 1 block TJ
Focusing on B1, 32 image data input terminals pH~
P! By temporarily dividing and driving 32 and 16 selection signal input terminals D1 to D16t, 512 heating elements 1111 are generated.
-1FF512 is time-divisionally driven. Therefore, the overall configuration is made up of four blocks that have exactly the same configuration as this turtle 1 block TJBL and are driven by the same method.

FIG. 16 is a diagram of the four components that drive this embodiment. In FIG. Regarding L block 4, it has exactly the same configuration and operation as block 4 in Fig. 14, so 1
Only the circuits corresponding to the blocks will be explained.

As mentioned above, the COD sensor CCDI is a 512-bit line sensor that scans 17.1/4 scanning lines and outputs a voltage level according to the rim information. This voltage level is binarized according to black and white by a binarization circuit DI.

The binarization circuit consists of a comparator that compares the output voltage of the CCD sensor with a reference voltage (slice level), and compares the input analog voltage with the slice level.
Outputs a binary signal. If the gradation (
If half tone) is required, it is multi-valued using an analog-to-digital converter or the like.

The data digitized by the binarization circuit D1 is input to a 32-bit shift register 8R1, subjected to serial-to-parallel conversion, and then parallel output processed in units of 32 bits. The output data of shift register 8 and 1 is held in a 32-bit double circuit LAI. Latch circuit LA
The data held in I is passed through 32 NAND gates Nll
~N! After timing with the print command signal PG at 32, the transistor! ! 1 to 〒I32 are selectively operated. Transistor! 1 to 132 companies, 32 Ns
-P-N) transistors, their respective flip terminals are connected to data input terminals 1''11-1132.

On the other hand, the 16 selection signal input terminals DI to f)16 are connected to the collectors of the 16 PNP transistors D1 to TD16. This transistor circuit〒D1～〒D
16 is sequentially scan-controlled by the output of the decoding circuit DC. The decoding circuit DC is a 4-line to 16-line depuder that sequentially receives signals from the control circuit CC from D1? Lines 1 to 16 of D16 are selected.

The control circuit CC is a circuit that generates a CCD drive clock, a shift clock for the shift register, a clock for the latch circuit, a timing clock for the gate circuit, a selection signal for the decoding circuit, etc. These semi-clocks are made of a crystal oscillator. Made.

Each control signal will be explained with reference to the timing charts of FIGS. 16 and 17. CCD1 to CCD4 are supplied with a signal 11L1 as a driving pulse, for example, a start pulse φX to start line scanning (Fig. 917 (t)), a reset F4 of the N output amplifier φ3 (Fig. 17 (2)), and a shift register section. The two-phase shift clock φ1. φ2 (not shown)
is given by the control circuit CC. The pulse interval of the start pulse φX corresponds to the scanning time of one scanning line, and during this period, the reset clock φ8 is generated from the 512 pulse CC. It is assumed that the reset clock /R is a signal corresponding to the bit of the COD, and when the reset clock φR is in a low level state, one-time information is output from the CCD.

Therefore, as shown in FIG. 17 (3), a transfer signal 80IC that rises at the same period as the reset clock φ8 and when the reset clock φ1 is at the 4-level is connected to the signal line L2 that controls the shift register 5ill from the control circuit CC. is given.

In the control circuit CC, this transfer signal ICK is counted and 32
A load clock is applied to the latch circuit LAI-L 4 through the signal line L3 for each bit. The load circuit (signal line L3) applied to the latch circuits M1 to L4 is shown in FIG.
4), the 32-pulse shift clock (first
It rises after 8CK) in Figure 7 (3) is issued.

One signal given to the gate circuits Nt1 to Nff32: A signal P that determines the energization timing and energization time to the heating element.
In C, as shown in FIG. 17 (5), the latch circuit LA1~
It is given on signal lines 1 and 11 after the load check of LA4 (LCK in FIG. 17(4)). This signal po is also generated every pulse of the reset clock -R32.

On the other hand, the inline signal input to the decoding circuit DC is
- It is hexadecimal during the scanning line, and is a hexadecimal kakunta O output that counts up by one every time the COD reset signal φ is counted up by 32 pulses. 16 transistors! D1~D16d Reset signal φR32
Each pulse turns on one by one. (Fig. 2 D1~
(See D16) In this embodiment, the memory can be significantly saved compared to the example of Hirosaki, which is extremely preferable.

In this case, if manufacturing accuracy allows, go to CCD1~CCD
4 and TJBI to JB4 are arranged in a straight line, the same effect as described above can be expected.

Moreover, in the event of a failure, CCD1 to CCD4, TJ
It is convenient because BI to TJB4 can be separated individually. In addition, it is more useful to improve the degree of area etc. if they are manufactured individually.

Figures 18 and 19 show another embodiment of the present invention, and in this case as well, the geometrical power distribution of the recorder PH and the CCD reader RD is the same as in the example above. In this example, the configuration is extremely simple by reducing the number of matrix wiring lines and by sharing the data processing circuit with four CODs. That is, the first
The data processing circuit in Figure 6 processes the information of four CODs in parallel, compared to 90, whereas the data processing circuit in factor 19 processes the information in a time-sharing manner.

First, the drive circuit configuration will be explained with reference to FIG. 3118. There are 1792 heating elements IHI to 448, and a diode for cross talk prevention is connected to each of them. The 1792 heating elements appear in 4 blocks, and each block has 14 scanning signal input terminals D1 to D14 connected to 4 blocks.
ing. The other end of the heating element is connected every 32 wires,
32 data input terminals? 1 to F32.

The outputs of 3119g04 CCDs, Cl1l to C114, are input to the 4-line to 1-line analog data 7-channel D8. Analog data selector D8 switches the inputs of ccD1 to ccD4 every 01/4 scanning line (205w5 length on original stage), and selects four CCDs.
′ are sequentially connected to form one scanning line. The manual selection of the four CCDs is based on the control signal from the control circuit CC.The subsequent processing is the same as in the previous example.
A. The 32 Nant gates NGI to NG32 are connected to the terminals p1 to P32 through the transistors TP1 to TP32. decoding circuit n
In this case, a 6-line to 56-line decoder is used for c.

In this embodiment, the circuit is simplified, but the recording time is four times longer than in the previous example, but this does not pose a problem considering the response frequency of the thermal inkjet.

FIG. 20 is a schematic partial cross-sectional view of another example of the recording head. Liquid chambers Wl and W2 are placed on the tapered metal plate HB.
are made on both sides of the metal plate FIB.

What is the ejection direction of the recording droplets ejected from the orifice o1 of one liquid chamber w1? 1, and the ejection direction of the recording liquid droplet ejected from the orifice o2 of the other liquid MW2 is 12, toward the same 1iiIDP of the recording member PP.

For example, even if Gl and G2 are arranged in a zigzag configuration as shown in FIG. 14, no vertical positional deviation will occur, and #!
A zigzag arrangement is not necessary for the Ryunsa CS shown in Fig. 14, and a commercially available one-line sensor can be used.

It is preferable that a simple circuit as shown in FIG. M19 be used as the data processing circuit.

Figure wVJ21 shows another example of the configuration of the heating element, which can be easily manufactured at low cost and also improves the packaging density. That is, on the top of the heating element resistance layer H, there is a selection electrode Pi- as shown in the figure.
1'9, etc., and heat generating parts IH2, 312, 314, 5
PI to select 0 for example 112 forming H4,5H6.

If a driving pulse is selectively applied to P2, it will work fine.

It is easy to configure a 0 selection circuit in which 584 generates heat by selecting P5 and P4.

According to this structure, etching of the H layer is unnecessary and the process is extremely simple. Of course, a predetermined portion may be etched if necessary.

[Brief explanation of drawings]

FIG. 1 is an example diagram of a heating element drive circuit that can be used in the present invention, FIG. 2 is a waveform diagram explaining its operation, FIG. 3 is a waveform diagram for explaining other circuit causes, and FIG. 4 is a waveform diagram for explaining its operation. The figure is a perspective view of a recording section of an example of the present invention, FIG. 6 is a front view thereof, j17E is a general view of a document reading section, and FIG. 8 is a block diagram of an example of the present invention.
Figure M9゜10 is a waveform diagram for explaining its operation, Figure 11 is a detailed diagram of a part of the memory, Figure 12 is a red diagram showing how the memory contents are driven during reading, and Figure 13 is for explaining the overall operation. )p-
Chart diagram, Figure 14 shows other configuration causes of the reading unit and recording unit, Figure 15 shows the driving circuit and causes thereof, Figure 16 shows its overall block diagram, and Figure 17 shows waveform diagrams for explaining the operation. , 18th
The figure shows another drive circuit configuration, Figure 419 is its overall block diagram, Figure 20 shows other contingencies in the recording section, and Figure 21 shows recording SO*
There are other contingencies.

Claims (1)

[Claims] A linear information reading section, a plurality of recording sections arranged offset from each other in the recording paper feeding direction, and the reading section