JPS5850844A - Multidirectional synchronization system - Google Patents

Multidirectional synchronization system

Info

Publication number
JPS5850844A
JPS5850844A JP14783881A JP14783881A JPS5850844A JP S5850844 A JPS5850844 A JP S5850844A JP 14783881 A JP14783881 A JP 14783881A JP 14783881 A JP14783881 A JP 14783881A JP S5850844 A JPS5850844 A JP S5850844A
Authority
JP
Japan
Prior art keywords
station
circuit
signal
master station
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14783881A
Other languages
Japanese (ja)
Inventor
Kazuo Yagi
八木 和夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP14783881A priority Critical patent/JPS5850844A/en
Publication of JPS5850844A publication Critical patent/JPS5850844A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0638Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0647Synchronisation among TDM nodes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/062Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers

Abstract

PURPOSE:To transmit a dial pulse signal from a subordinate station to a master station by transmitting a PCM signal, which is as much as six frames or its integral multiple, in such a way that it is arranged in a transmitted burst to be transmitted at a time when the transmitted burst of the subordinate station is constituted. CONSTITUTION:A PCM codes are received by a receiving terminal 1, and a frame synchronizing signal receiving circuit 2 detects multiframe synchronism to find a frame containing a dial signal in the 8-bit code, thereby transmitting it to a memory control circuit 7. On the other hand, a synchronizing signal in a signal from a master station is transmitted from a terminal 3, and transmitting timing counters 5-1-5-3 count timing to input the results to the circuit 7. The circuit 7 controls the counters so that one of memories 6-1-6-3 is used for reading-in operation, another memory is used for reading-out operation, and the remaining one is used as a stand-by memory. Signals read out of the memory are transmitted to the master station through an OR circuit 8, a transmitter 9, and an antenna 10.

Description

【発明の詳細な説明】 本発明は、 PCM(Pulse Code Modu
lation)方式を用いた時分割多方向多重無線方式
の同期方式に関するものである。
[Detailed Description of the Invention] The present invention provides PCM (Pulse Code Module)
This invention relates to a synchronization method for a time division multiplex radio system using a time division multiplexing radio system.

無線周波数を使用して1行なう通信方式に於いて、中心
となる特定の局(以後親局と称する)と複数個の相対す
る局(以後子局と称する)の間での通信を1対の無線周
波数で行なう事は、電波の有効利用の上から好ましい事
であり、従来2周波数分割多重単一リ帯波変調を用いた
方式が実用化されていた。しかし2通信のディジタル化
の方向を考えて、音声の変調方式としてPCM変調方式
を用いたディジタル無線変調方式による時分割多方向多
重方式が考案され実用化されようとしている。
In a communication system that uses radio frequencies, communication between a specific central station (hereinafter referred to as the master station) and multiple opposing stations (hereinafter referred to as slave stations) is carried out in a pair. Using radio frequencies is preferable from the standpoint of effective use of radio waves, and conventionally a method using two-frequency division multiplexing and single band modulation has been put into practical use. However, considering the direction of digitalization of 2 communications, a time division multidirectional multiplexing system using a digital radio modulation system using a PCM modulation system as an audio modulation system has been devised and is about to be put into practical use.

この場合1対の電波で無線伝送を行なうため、親局から
子局方向へは連続波にて伝送するので、特に問題となる
事は無いが、子局から親局方向へは。
In this case, since wireless transmission is performed using a pair of radio waves, continuous waves are used for transmission from the master station to the slave station, so there is no particular problem, but from the slave station to the master station.

各子局が間歇的(バースト的)に伝送するだめ伝送する
方法に種々考慮しなければならないことがある。
Since each slave station transmits intermittently (burst-like), various considerations must be made regarding the transmission method.

第1図は9時分割多方向多重無線方式の1例の親局及び
各子局の送信するタイミングを示したものである。親局
から子局方向の伝送は連続波とし。
FIG. 1 shows the timing of transmission by a master station and each slave station in an example of a 9-time division multidirectional multiplex radio system. Transmission from the master station to the slave stations is a continuous wave.

一定周期で、フレーム同期ビットFが挿入しである。各
子局は1.このフレーム同期ビットを検出し。
A frame synchronization bit F is inserted at regular intervals. Each slave station has 1. Detect this frame sync bit.

これを・もとに自局の送信するタイミングを親局の受信
タイミングに合わすべくカウントし送信すれば、各子局
が間歇的に送信する信号(以後送信バーストと称する)
の中には、親局で、同期を検出するための符号を伝送す
る事が不要となり送信バーストの符号ピット数を減らし
、これにより、電波の有効利用をはかる事ができる。
Based on this, if you count and transmit the timing of your own station's transmission to match the reception timing of the master station, each slave station will transmit a signal intermittently (hereinafter referred to as a transmission burst).
In some cases, it becomes unnecessary for the master station to transmit codes for detecting synchronization, reducing the number of code pits in the transmission burst, thereby making it possible to use radio waves more effectively.

本発明は、かかる送信方式を使用する時分割多方向多重
通信方式に於ける。各子局の符号構成の方法に関するも
のである。第2図は、公知の冴通話路方式のPCM伝送
のフレーム構成であり、これは9国際電信電話諮問委員
会(CCITT)でも勧告されたものである。このフレ
ーム構成において。
The present invention relates to a time division multiplex communication system using such a transmission system. This relates to a code configuration method for each slave station. FIG. 2 shows the frame structure of PCM transmission using the well-known communication channel system, which was also recommended by the Consultative Committee on International Telegraph and Telephone (CCITT). In this frame configuration.

1つのパルス振幅−調波(以後PAM波と称す)を8ビ
ツトでコード化するとき、6フレームのうち5フレーム
は、8ビット全部でPAM波をコード化して表わし、6
フレームのうち1フレーム。
When one pulse amplitude harmonic (hereinafter referred to as a PAM wave) is encoded with 8 bits, 5 out of 6 frames represent the PAM wave encoded with all 8 bits, and 6
One of the frames.

8ビツトのうち1ピツトは、ダイヤル信号を伝送するの
に用いる。このため、この信号を表わすフレームが親局
において検出できる様に各子局は、符号を構成する必要
がある。
One pit of the 8 bits is used to transmit a dial signal. Therefore, it is necessary for each slave station to construct a code so that the frame representing this signal can be detected at the master station.

本発明は、親局においてのダイヤル信号が検出できるた
めの、多方向多重通信方式の符号構成を提供するもので
ある。
The present invention provides a code structure for a multi-directional multiplex communication system that allows detection of a dial signal at a master station.

24通話路P −CM伝送方式の符号は前述した通りダ
イヤル信号の伝送は、6フレームに1フレームであるの
で各子局の送信バーストは、6フレームまたは、その整
数倍の符号をまとめて構成し、8ビツトでコード化され
た符号の第8ピツトがダイヤル信号を表わしているフレ
ームが、6フレームのうちのどの部分(例えば、最後の
フレーム)に含まれているかをあらかじめ決めておけば
、親局で各子局からの送信バーストを受信し、それらを
標準PCM符号列に並べかえる時に各子局から受信した
PCM符号のうちダイヤル信号が含まれている部分を見
分けることが出来る。
As mentioned above, the transmission of the dial signal is one frame in every six frames, so the transmission burst of each slave station consists of codes of six frames or an integral multiple thereof. If you decide in advance which part of the six frames (for example, the last frame) contains the frame in which the 8th pit of the 8-bit encoded code represents the dial signal, the parent When the station receives the transmission bursts from each slave station and rearranges them into a standard PCM code string, it is possible to identify the portion of the PCM code received from each slave station that includes a dial signal.

第3図は1本発明の子局送信バーストの符号構成の1例
である。本実施例は、子局の送信バーストは、6フレ一
ム分のPCM符号から成っており。
FIG. 3 shows an example of the code structure of a slave station transmission burst according to the present invention. In this embodiment, the transmission burst of the slave station consists of PCM codes for 6 frames.

該当子局には6通話路(通話路を以後CHと略す)が割
当てられたものを示す。図中へ〜f、は、8ビツトのP
CM符号60H分即ち48ビツトから構成されており、
f1〜f、は8ビツトのPCM符号を。
This figure shows that six communication paths (the communication paths are hereinafter abbreviated as CH) are assigned to the corresponding slave station. ~f in the figure is an 8-bit P
It consists of 60H of CM code, that is, 48 bits,
f1 to f are 8-bit PCM codes.

全てPAM l波をコード化した符号としf6は、8ビ
ツトのうち8番目の1ビツトは、ダイヤル信号の伝送に
使用されているものとする。各子局ともCH数は異なっ
ても、八〜f6のならべる順序を同一にしておけば、親
局に於いて、各子局からの送信バーストを受信し、これ
を第2図に示した標準PCM符号構成に並べかえる事が
できる。
It is assumed that f6 is a code in which all PAM l waves are encoded, and the eighth bit out of eight bits is used for transmitting a dial signal. Even if the number of channels is different for each slave station, if the order of arranging 8 to f6 is the same, the master station can receive the transmission burst from each slave station and transmit it according to the standard shown in Figure 2. It can be rearranged to PCM code structure.

SlおよびS2は、送信バーストの前後のガードビット
差動同期のための同期ビット、監視のためのビット等で
数ビットずつで構成されている。
Sl and S2 each consist of several bits, including guard bits before and after the transmission burst, synchronization bits for differential synchronization, monitoring bits, and the like.

第4図は1本発明の子局送信バーストを構成するだめの
回路系統図の例であり、1は、PCM端局からの信号の
受信端子、2はPCM符号例の中からフレーム同期信号
およびマルチフレーム同期信号の検出回路3は、子局の
受信機にて受信した親局からのフレーム同期信号第1図
のFに相当)の受信端子、4は、親局からのフレーム同
期信号をもとにあらかじめ定められている自局の送信タ
イミングをカウントするカウンター°回路、5−1〜5
−3は、PCM端局からの符号を一時記憶するメモリー
回路、6−1〜6−3は、該メモリーの読込、読出のた
めのカウンター回路、7は、メモリーの読込、続出を制
御するメモリー制御回路、8は、メモリーの読出した内
容を集める論理和回路。
FIG. 4 is an example of a circuit system diagram configuring the slave station transmission burst of the present invention, in which 1 is a receiving terminal for a signal from a PCM terminal station, 2 is a frame synchronization signal and a signal from among PCM code examples. A multi-frame synchronization signal detection circuit 3 receives a frame synchronization signal from the master station (corresponding to F in FIG. 1) received by the receiver of the slave station; Counter circuit for counting the transmission timing of the own station predetermined in 5-1 to 5
-3 is a memory circuit that temporarily stores the code from the PCM terminal; 6-1 to 6-3 are counter circuits for reading and reading out the memory; and 7 is a memory that controls reading and subsequent reading of the memory. The control circuit 8 is an OR circuit that collects the contents read from the memory.

9は、無線送信機、 10は、送信用空中線である。9 is a radio transmitter, and 10 is a transmitting antenna.

次にこの動作は、PCM符号をPCM信号受信端子から
受信し、フレーム同期信号受信回路にてマルチフレーム
同期を検出し、8ビツトのPCM符号〔の中に・ダイヤ
ル信号が含まれているフレームを見わけ、メモリ制御回
路7へ情報を伝達する。
Next, this operation receives the PCM code from the PCM signal receiving terminal, detects multi-frame synchronization in the frame synchronization signal receiving circuit, and detects the frame containing the dial signal in the 8-bit PCM code. The information is transmitted to the memory control circuit 7.

一方親局からの受信信号に含まれるフレーム同期信号を
端子3より受信し、送信タイミングカウンタにて自局の
送信タイミングをカウントし、その情報をメモリ制御回
路7へ伝達する。メモリ制御図では、上記情報をもとに
順次3個所有するメモリのうち1個をPCM符号の読込
に使用し、他の1個を続出に使用し、残りの1個を時期
用に使用すべく、メモリカウンタ制御する。メモリカウ
ンタにより制御され読出されたPCM信号は、論理和回
路8.無線送信機9.送信用空中線10を通じて親局へ
送信される。
On the other hand, the frame synchronization signal included in the received signal from the master station is received from the terminal 3, the transmission timing of the own station is counted by the transmission timing counter, and the information is transmitted to the memory control circuit 7. In the memory control diagram, based on the above information, one of the three memories is used for reading the PCM code, the other one is used for reading the PCM code, and the remaining one is used for the timing. The memory counter is controlled accordingly. The PCM signal controlled and read by the memory counter is sent to the OR circuit 8. Wireless transmitter9. The signal is transmitted to the master station via the transmitting antenna 10.

第5図は、上記子局から送信されて来た信号を受信する
親局受信回路の例であり、1は受信空中線、2は無線受
信機、3は親局送信部からのフレーム同期情報受信端子
4は、上記フレーム同期情報をもとに受信タイミングを
カウントするカウンター、5−1.5−2は、受信した
符号を並べかえるために記憶するメモリー回路、6−1
.6−2は、メモリーの読込、読出のためのカウンタ、
7はメモリを制御するメモリ制御回路、8は、PCM端
局に対するフレーム同期の発生回路、9は、メモリ読出
出力を合成する論理和回路、10は、PCM端局への出
力端子である。
FIG. 5 is an example of a master station receiving circuit that receives signals transmitted from the slave station, where 1 is a reception antenna, 2 is a radio receiver, and 3 is a frame synchronization information reception circuit from the master station transmitter. Terminal 4 is a counter that counts reception timing based on the frame synchronization information, 5-1.5-2 is a memory circuit that stores received codes in order to rearrange them, and 6-1
.. 6-2 is a counter for reading and reading memory;
7 is a memory control circuit for controlling the memory; 8 is a frame synchronization generation circuit for the PCM terminal; 9 is an OR circuit for synthesizing memory read outputs; and 10 is an output terminal for the PCM terminal.

次にこの動作は、各子局から?送信バーストを空中線、
無線受信機で受信し、復調された符号を標準PCM端局
用符号列に並べかえるために、メモリ6−1.6−2に
一時記憶する。メモリの記憶する部署は、送信部からの
フレームビットをもとに、受信タイミングカウンタ4に
て作られた受信タイミングをもとに、メモリ制御回路8
にて制゛御されたメモリカウンタ6−1.6−2により
指定されるメモリの中で符号が並べ換えられ、メモリカ
ウンタに指定されて読出されている。読出された符号は
、論理和回路でフレーム同期発生回路8で発生されたP
CM端局用フレーム同期信号と合成され、端子10より
PCM端局へ伝達される。
Next, is this behavior from each slave station? Aerial transmitting bursts,
The codes received by the radio receiver and demodulated are temporarily stored in the memory 6-1.6-2 in order to be rearranged into a standard PCM terminal station code string. The memory is stored in a memory control circuit 8 based on the reception timing created by the reception timing counter 4 based on the frame bits from the transmitter.
The codes are rearranged in the memory specified by the memory counter 6-1, 6-2 controlled by the memory counter 6-1, 6-2, and read out by being specified by the memory counter. The read code is the P generated by the frame synchronization generation circuit 8 in the OR circuit.
It is combined with the frame synchronization signal for the CM terminal station and transmitted from the terminal 10 to the PCM terminal station.

以上説明したごとく9本発明によれば、子局の送信バー
ストを構成する際に6フレ一ム分またはその整数倍のP
CM符号を、1回の送信バースト内に並べて伝送するこ
とにより、親局でダイヤル信号の含まれたクレームラ見
わける事が出来、従って子局→親局方向にもダイヤルパ
ルス信号の伝送全可能にす志。
As explained above, according to the present invention, when configuring a transmission burst of a slave station, P of 6 frames or an integral multiple thereof is
By transmitting the CM codes side by side in one transmission burst, the master station can distinguish the complaints containing the dial signal, and therefore it is possible to transmit the dial pulse signal from the slave station to the master station. Will.

本発明の詳細な説明には、送信バーストの構成には6フ
レ一ム分のPCM符号で行なったが。
In the detailed description of the present invention, the transmission burst was constructed using PCM codes for 6 frames.

その整数倍のフレームで構成してもよい事はもちろんで
ある。 。
Of course, the frame may be composed of frames that are an integral multiple of that number. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は9時分割多方同条重無線方式の送信信号のタイ
ムチャートを示す図、第2図は、  PCM端局のフレ
、−ム構成を示す図、第3図は9本発明の子局送信バー
ストの符号構成を示す図、第4図は、第3図の符号構成
を実現する子局の回路系統図、第5図は、第3図の符号
構成する親局の回路系統図である。 5−1.5−2:メモリー回路、6−1.6−2:カウ
ンタ。 代理人弁理士 薄 1)利 幸 第1図 卑見1局送、イ盲  二二 摩11局受信   二二二二二=[二二二二二二[==
===コ===:、二°ニニ            
         ニニニ第3図
Fig. 1 is a diagram showing a time chart of a transmission signal of a 9-time division multidirectional simultaneous radio system, Fig. 2 is a diagram showing a frame configuration of a PCM terminal station, and Fig. 3 is a diagram showing a frame configuration of a PCM terminal station. FIG. 4 is a diagram showing the code structure of the station transmission burst. FIG. 4 is a circuit diagram of a slave station that implements the code structure of FIG. 3. FIG. 5 is a circuit diagram of a master station that implements the code structure of FIG. 3. be. 5-1.5-2: Memory circuit, 6-1.6-2: Counter. Agent Patent Attorney Susuki 1) Toshiyuki Figure 1 Hemi sent 1 station, Iblind 22 Ma received 11 stations 22222=[222222[==
===ko===:, 2°nini
Ninini Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1個の親局と複数個の子局の間の無線伝送をディジタル
変調方式を用いた1対の電波により行ない、親局から子
局方向へは連続波を、子局から親局方向へは2時分割で
、各子局は間歇的に送信する無線通信方式に於いて、2
4通話路PCM符号を伝送する場合、各子局は、自局に
割当てられた通話路(7) p CM符号の6フレ一ム
分またはその整数倍フレームの信号をひとまとめにして
親局へ伝送することにより、ダイヤル信号を伝送するこ
とを特徴とする多方向多重方式の符号構成方式。
Wireless transmission between one master station and multiple slave stations is performed using a pair of radio waves using a digital modulation method, with continuous waves transmitted from the master station to the slave stations, and continuous waves from the slave stations to the master station. In a wireless communication method in which each slave station transmits intermittently in two time divisions,
When transmitting a 4-channel PCM code, each slave station transmits the signals of 6 frames of the p CM code or an integral multiple thereof to the master station on the channel assigned to it (7). A multidirectional multiplex code configuration system characterized by transmitting dial signals by
JP14783881A 1981-09-21 1981-09-21 Multidirectional synchronization system Pending JPS5850844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14783881A JPS5850844A (en) 1981-09-21 1981-09-21 Multidirectional synchronization system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14783881A JPS5850844A (en) 1981-09-21 1981-09-21 Multidirectional synchronization system

Publications (1)

Publication Number Publication Date
JPS5850844A true JPS5850844A (en) 1983-03-25

Family

ID=15439388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14783881A Pending JPS5850844A (en) 1981-09-21 1981-09-21 Multidirectional synchronization system

Country Status (1)

Country Link
JP (1) JPS5850844A (en)

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