JPS58500821A - Dual element single oscillator ratio digital converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Dual Element Single Oscillator Ratio Digital Converter The present invention provides pressure, liquid level and physical It relates to devices and circuits for measuring quantities such as The device is effective in combination with common signal generators such as variable frequency oscillators. It relates to electronic circuits that make it possible to operate.

Background technology Using a converter with variable electrical components forming part of the oscillator's tank circuit It is well known to produce a signal representative of the quantity to be measured by This structure structure, the output frequency of the oscillator changes with the change in the quantity being measured, causing the oscillation If the circuit has the required stability, the frequency will also dictate the quantity being measured. It is possible to interpret it as

Also, in order to compensate for error sources such as changes in the values of electrical components due to temperature, Using two sensors, one generates a data signal and the other only follows the temperature. Methods of generating varying reference signals are also well known. Therefore, the data signal It is made pure by subtracting the quasi-signal value from it.

As mentioned above, the use of a dual sensor system in a variable frequency signal generator is It may induce another source of error. That is, the oscillation to which each sensor is connected This is a potential mismatch between the circuits. −Even if there is consistency under the group conditions, The two oscillator circuits have stray fluctuations independent of changes in temperature, pressure, humidity, etc. be.

Disclosure of invention The present invention provides a dual sensor measurement device that eliminates the potential error effects of mismatched oscillators. Ru. This means that the data that is controlled according to the change in one of the two types of generated signal frequencies is To time the two sensors and a common oscillator or similar signal generator using a This is achieved by operating in combination in a division multiplex format.

Brief description of the drawing FIG. 1 is a detailed circuit diagram of a device embodying the invention.

FIG. 2 is a diagram of signal waveforms generated in the circuit of FIG. 1.

FIG. 3 is a detailed circuit diagram of a modified section of the device shown in FIG. 1.

Best mode for carrying out the invention FIG. 1 shows an embodiment of the invention having a matched pair of inductive sensing elements 10 and 12. This pixel element is present in each signal quantity converter, such as a linear position detector. do. The inductive sensing elements 10 and 12 operate in a complementary manner to signal transmission data G1 and and G2 to a common variable frequency oscillator 14, in which They alternately serve as frequency determining elements. That is, its attached r -1 is conducting, each of the sensing elements 10 and 12 is connected to the tank circuit of the oscillator 14. electrical impedance or actuator connected to and represented by that element. Determine the output frequency of the oscillator according to the value of the oscillator.

Furthermore, the above-described logic circuit 18 may be configured such that the sensing elements 10 and 12 have different output frequencies. In the configuration each is coupled to a separately corresponding oscillator having f1 and f2. It is easily possible to make it into a shape suitable for use.

For example, as shown in FIG. 3, sensing elements 10 and 12 are connected to separate oscillators; The outputs of both oscillators with different frequencies are applied to the inputs of dates G1 and G2 as signals f□ and It is possible to supply them directly as f2 and f2. f1 and f2 respectively The outputs of G1 and G2 (data with frequency) are alternately provided directly to the input of date 16. The remaining operation of logic circuit 18 is essentially the same as described above.

The sensing elements 1'0 and 12 are similar or matched to the ambient conditions such as temperature. selected and positioned to indicate the desired response. In other words, given the ambient temperature changes in the electrical properties of the same magnitude and direction in each pixel element occurs. However, sensing elements 10 and 12 have opposite It is set to react based on orientation. For example, a sensing element is used in a moving magnetic core type linear position detector. When using sensors 10 and 12, the magnetic core of each sensing element 10 and 12 is a common core. be mechanically interconnected or spliced together, and the positional changes of the equipment being monitored. For one of the magnetic cores, the magnetic flux is deep enough to penetrate into the guide ring combined with it. The other magnetic core should be moved away from the guide ring attached to it. as a result of which a change in the electrical signal value occurs in the opposite direction. this thing are given by way of example only and may be used for resistive or static as well as combinations of electrical components. It is easily understood that it is possible to achieve the same result using capacitance. It will be done.

The time division multiplexed output of oscillator 140 is connected to an inverter and a Nant gate or The logic circuit control device is 18. This device 18 is installed at Nantes Gate 20 in the following produces an output signal related to the ratio of the two input signal frequencies, referred to as f2 and f2. more times The circuit 18 operates according to the change in frequency f and also determines the time of G1 and G2. Configure the optimal settings.

rt table 58-500821 (3) The main elements of circuit 18 are a 1 MHz clock source 22, a clock in both up and down directions. A clock 22 is connected to a group of 4029 type counters 26 that perform counting. Logic circuit 24. As well as the conduction of the two transmission dates G1 and G2, the various circuits 18 A pair of type 4016 flip clocks 18 that control the components of the In order to prevent excessive counts from being supplied to output 21, the repetition rates f and f2 should be kept constant. It is composed of a synchronous circuit consisting of a 4016 type flip-flop 72 which takes a certain period of time.

Wherever possible, we will use industry standard numbers for integrated circuits available on the market. Please note that

To explain the circuit of FIG. 1 in more detail, the complementary output of the flip clock 30 The timing signals on lines 32 and 34 generated by Make conductive. Assuming a moment when line 32 is high and line 34 is low, then N is made conductive, and then sensor 10 is coupled to the input of oscillator 14. This result An oscillator output with wavenumber f1 is produced. The f0 frequency signal is a Nantes gate 16 and 36 to a counter 38. Counter 38 is a 4040 type counter operates as a frequency divider and outputs a time-division multiplexed output pulse of the input frequency. It has outputs Q9°Q10 and Qll that provide. For example, Q'10 output is 512 gives the division coefficient of A predetermined number of pulses of input frequency f0 are input by the counter 38. When this is received, the Q10 output goes high. The high pulse from Q10 output is line 4 0 to one input of the NAND date 42.

The second input of NAND r-z2 is connected to the output of 1 MHz clock 22.

Therefore, the high output pulse from output Q10 will cause the look lock signal to 1 megabyte. The clock input signal of the counter 26 passes through the gate 42 and the clock input of the counter Allows you to be sent to power. At this point, the Q11 output of the counter 38 The power is low and this low signal is inverted to a high signal by inverter 50 and this signal The signal is then input to buffer 16 as well as each up or down input of counter 26. It is also supplied to one person.

A high signal at the up or down input of counter 26 causes the latter to go up. As a result, the counter 26 is in the counting state, and the Q10 output of the counter 38 is high. Start counting pulses of the 1 MHz clock signal while Therefore, Count The total number of counts accumulated in the counter 26 is determined by the Q10 output pulse, which is inversely proportional to the input frequency f. It can be seen that this is determined by the width of the space. Here, the clock signal is the quantity being measured in that it has no association with any of the variable frequency signals corresponding to changes in It should be noted that it is a signal of an arbitrarily selected frequency. death However, it is desirable that the frequency of the clock signal is higher than frequencies f1 and f2. Delicious. In any case, when the Q10 output goes low, the Q11 output goes high at the same time. Ru. This low signal from the Q10 output is inverted to a high signal by inverter 48. , which is then fed to the clock input of flip 70 30. flip croquet The circuit 30 responds by changing the state of the signals on lines 32 and 34. i.e. , line 32 goes low and line 34 goes high. At this point, date G2 is sensing element 1 2 is connected to the input of oscillator 14, which then generates frequency f2. Q1 A low signal of 0 closes date 42 and clocks nando date 44 and counter 26. Remove the clock signal from the clock input.

The high signal from the Q11 output is turned to a low state by inverter 50, and this low signal At the same time that the number switches the counter 26 to the down-counting state, one of the buffers 16 Power is supplied. This disables the output of buffer 16 and /7'-13 The supply of pulses from the oscillator 14 via 5 to the counter 38 is cut off. Q1 The high signal from the 1 output is also supplied to the Nanto Gamer 6 via the Nanto Gamer 6B. be done. In contrast, the date 66 is connected to the r-) inverter 64 and the k''-) 62. 36 to send a 1 MHz clock signal to the input of counter 38. First, counter 38 processes the incoming 1M look-lock signal. Coun The time interval during which the controller 3B processes the 1 MHz clock signal is the output of the oscillator 14. provides a delay period during which the power frequency is switched from f to f2. This delay period is , the output of the oscillator 14 stabilizes at the frequency f2 immediately after switching between gates G1 and G2. make it possible to

Counter 38 processes the 1 MHz clock signal until the Q9 output goes high. . The high signal that occurs simultaneously on Q9 and Qll is caused by t""-i 6B and 66. It is processed as follows. These gates send a 1 meg looklock signal to counter 38. act to terminate the supply of issues.

Furthermore, the high output simultaneously generated on Q9 and Qll is caused by gate 68 and inverter 7. 0 to flip 70 to 72. This flip-flop is Set by f2 pulse. Flip clock 72 then goes to Nantes gate 54 high signal, this nand date outputs nand r''-) 44 from clock 22. provides a look-lock signal to 1 megabyte for the clock input of counter 26 through make it possible to Since the counter 26 is in a down counting state (Q1 1 output goes low), counter 26 receives the 1 MHz clock signal. Therefore, a down counting operation is performed.

As a result of flip-flop 72 being set, there are 7 rip clocks at the same time. A date signal is also supplied from Q3 output of 72 to one person of Nando Date 20. .

The other two connections to Nando Date 20 are via line 106 to line 34 and It is connected to the output of oscillator 14 via line 74. Therefore, flip-flop The date signal from the Q3 output of nando pad 72 causes nando date 20 to A frequency signal is supplied to the output terminal 21.

When the counter 26 counts down to zero, the carrier wire C○1 of the counter 26, The high output signals from CO2 and CO6 are fed to the input of the Nordate 56, which The latter generates a signal at its output. The output signal from gate 56 is Rip clock 58 clock (set) 1% flip flop 30 Reset. In response to the set signal, flip clock 58 is applied to line 60. Provides a signal to reset counter 38. Counter 38 reset state , the Q9, Ql0 and Q11 outputs go low and the low signal on Q11 is inverted. The counter 26 is inverted by the counter 50 and placed in a down counting operation state. Coun Simultaneously with the reset of the signal on line 61, the flip clock 58 We also supply R-144 for one-person labor. This signal is from Nando'7"-to44. Prohibit blocking of the 1 MHz clock signal to counter 26 . Therefore, after the counter 26 counts down to zero, the counter 26 then counts down to zero, and then Holds zero count until placed into up-count operation by a low signal. ke” -) By resetting the flip-flop 30 by the output of , lines 32 and 34 are returned to their initial state, ie, line 32 is high and line 34 is low. Set. The reset of flip-flop 30 also flips onto line 63 It also provides a reset signal to the reset input of flop 102. flip Due to the reset of clock 72, its Q3 output goes low and the output of gate 20 is prohibited. At this point, the circuit returns to its initial starting state and is ready for the next counting period. Ru.

The output fo of gate 20 (shown in FIG. The voltage of sensing elements 10 and 12 is proportional to the ratio of signal frequencies f and f2, and It maintains stability regardless of fluctuations in environmental quantities that change the air value in the same way. but However, since the signal frequency values f1 and f2 change in opposite directions, their ratio is as a powerful, easy-to-process electrical signal representation of the amount of change that occurs.

Industrial applicability Although the techniques and devices described above are applicable to a wide range of precision measurement applications, To facilitate the solution, the response to linear position measurements in an ambient environment with varying temperatures is required. It is best to refer to the

As mentioned above, an internally movable device mechanically connected to the device whose position is to be monitored. A dynamic magnetic core is applied to the inductive sensing element 10, thereby causing a movement in the right direction. The movement moves the magnetic core deeper into the inductive element 10, and the movement to the left moves it out of the element. Go away. Conversely, the inductive sensing element 12 is affected by movement of the device to the right. The magnetic core moves away from the element! 71 Move deeper into the element by moving to the left A movable internal magnetic core or magnetic core part mechanically connected to the equipment being monitored given. As a result, the two inductive elements 10 and 12 are resistant to temperature changes. react in the same direction, but in the opposite direction to the movement of the element whose position is to be measured. and react.

The operation of the circuit 18 in the above-described configuration is provided to the circuit 18 via the data 116. resulting in a sequence of time-division multiplexed signals f 1 and f 2 . The counter 38 is f 8, which operates to divide the f1 signal and has a width inversely proportional to the frequency of the f1 signal. - produces a pulse at its Q10 output. Q? During the period of 0 output date pulse , the pulses from the 1MHz clock 22 are input to the counter 26 by the up counting function. Stored. Since the frequency of the clock 22 is constant, the pulse of the counter 26 The count represents a period of time that can be regenerated by counting down to zero. Q1. (At the end of one 8-bit pulse, G1 and G2 switch each other, and the The path of car 20 produces a time f2 that is the same as the period set by f. The corresponding periods of fl and f2 are supplied to the force and therefore the corresponding periods of fl and f2 are The ratio remains constant.

At the same time, counters 26 are routed through gates 54 and 44 to count to zero. A clock pulse is supplied. When the zero count is reached, the output 20 will stop and the rotation will start. The path is brought back to rest for the next cycle of operation.

The processing of the signal from output port 20 may be varied to suit a particular user. However, the number of f2 pulses that occur during the gate pulse time dictates the ratio of f and f2. is intended to be counted and averaged. This signal is Due to its form, it is clear to those familiar with the prior art that the latest signals Easily adaptable to processing and data storage devices.

Reference has been made to the above detailed description of the present invention, and is not limited to the prior art. It should be understood that various changes and additions may be obvious to those who read the manual.

Furthermore, the present invention can be adapted to applications other than linear position measurements. It should also be understood that

Examples include measurements of pressure, humidity, water level, light intensity, and acoustic conditions. Similarly, the circuit It is also possible to make the sensor insensitive to ambient conditions other than temperature, such as humidity and atmospheric pressure. be. Other aspects, objects and advantages of the invention may be found in the accompanying drawings, disclosure and appended claims. This can be obtained by considering the range.

international investigation failure

Claims (1)

[Claims] 1. A single signal generator (1) connected to the first and second sensing elements (10, 12) 4), wherein the signal generator (14) is connected to the first and second sensing elements (10°), respectively. 12) in response to one of the first and second signals (fi. f2), the sensing elements (10, 12) sensing at least one changing condition at corresponding first and second locations; In the measuring device that supplies the signal corresponding to the device (14) each connected between a corresponding sensing element (10, 12) and a generator (14), each a first and a first one adapted to control the supply of a corresponding sensing element signal to the generator; 2 date (G1,02), and Receives the signal (fx; f2) from the generator (14) and generates the signal (fl + f2) ) to sequentially operate the gates (G1, G2) corresponding to one period of A measuring device consisting of a control device (18). 2. The measuring device according to claim 1, wherein the signal generator is an oscillator (14). - said gate (G1.G2) connects said sensing element (10, 12) to said oscillator; (14) Measuring device connected to. 3. The measuring device according to claim 2, wherein the I control device (18) A part (fl) of the first frequency output that changes according to the signal from the intelligent element (10) is received from the oscillator (14), and the width is opposite according to the frequency of a part (fl) of this output. a logic device (24, 28) for generating a gate pulse that changes to a portion of the second frequency output (f2) that varies in response to the signal from the sensing element (12) of ) is received from the oscillator (14) and also receives a delayed date pulse as an activation signal. receiving a re-occurrence signal, and changing a second value only upon receipt of said delayed re-occurrence signal; an output gate device (20) for passing a part of the frequency output (f2); Fixed device. 4. The measuring device according to claim 6, wherein the logic device (24, 28) During the first varying frequency output section (f), the width of said gate pulse a first clock device (22) operative to generate a count proportional to the count; a first counter device (26) for receiving and accumulating numbers; Signal device (40, 46) for simultaneously reversing the counting order and starting the date pulse ),as well as The inverted count and date pulse are terminated in response to the count being reduced to the initial value. and a first switch device (58). 5. The device according to claim 4, wherein the logical device (24, 28) is A second switch device (for controlling conduction of the gate (, () 1.02)) 30). 6. The measuring device according to claim 4, wherein the logic device (24, 28) is divide the frequency of the first signal (fl) to generate the gate pulse. A measuring device with a second counter device (38) for. 7. The measuring device according to claim 4, wherein the switch device (58) A measuring device that is a flop. 8. The measuring device according to claim 1, wherein the control device (18) is a signal generator. One of the signals (f2) and (f2) in (14), and the other of the signals (fl) and (f2) A digital circuit (38, 2) that generates an output according to the ratio of the output signal values divided by 4,26,28,30°20.72).