JPS5850059B2 - Reception signal control circuit - Google Patents

Reception signal control circuit

Info

Publication number
JPS5850059B2
JPS5850059B2 JP52011967A JP1196777A JPS5850059B2 JP S5850059 B2 JPS5850059 B2 JP S5850059B2 JP 52011967 A JP52011967 A JP 52011967A JP 1196777 A JP1196777 A JP 1196777A JP S5850059 B2 JPS5850059 B2 JP S5850059B2
Authority
JP
Japan
Prior art keywords
circuit
switching
control circuit
control
signal control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52011967A
Other languages
Japanese (ja)
Other versions
JPS5396716A (en
Inventor
修 山本
肇 赤羽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP52011967A priority Critical patent/JPS5850059B2/en
Publication of JPS5396716A publication Critical patent/JPS5396716A/en
Publication of JPS5850059B2 publication Critical patent/JPS5850059B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B7/00Radio transmission systems, i.e. using radiation field
    • H04B7/02Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/08Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
    • H04B7/0802Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using antenna selection
    • H04B7/0817Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using antenna selection with multiple receivers and antenna path selection
    • H04B7/082Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using antenna selection with multiple receivers and antenna path selection selecting best antenna path
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G7/00Volume compression or expansion in amplifiers
    • H03G7/001Volume compression or expansion in amplifiers without controlling loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Circuits Of Receivers In General (AREA)
  • Radio Transmission System (AREA)

Description

【発明の詳細な説明】 本発明は受信信号制御回路に関するものである。[Detailed description of the invention] The present invention relates to a received signal control circuit.

従来、受信信号レベルの変動に対して複数の受信機を切
替えて使用するスペースダイパーシティ方式が用いられ
ている。
Conventionally, a space diversity method has been used in which a plurality of receivers are switched and used in response to fluctuations in the received signal level.

この受信信号制御回路の代表例としては、第1図あるい
は第2図のブロック図の回路が使用されている。
As a typical example of this received signal control circuit, the circuit shown in the block diagram of FIG. 1 or 2 is used.

第1図において、入力端子114,115に加えられた
AI 、A2の受信信号は分岐増巾器101゜102を
通った後、切替回路103でいずれか1方が選択された
後出力端子116から送出される。
In FIG. 1, the received signals of AI and A2 applied to input terminals 114 and 115 pass through branch amplifiers 101 and 102, and after one of them is selected by a switching circuit 103, they are output from an output terminal 116. Sent out.

他方、分岐増巾器101,102にて分岐された信号は
制御信号発生回路104で比較された後、切替回路10
3へ制御信号を送出する。
On the other hand, the signals branched by the branch amplifiers 101 and 102 are compared by the control signal generation circuit 104, and then sent to the switching circuit 10.
Sends a control signal to 3.

制御信号発生回路104の構成は、第1図に示すとおり
である。
The configuration of control signal generation circuit 104 is as shown in FIG.

105,106はバッファ増巾器、107は切替器、1
08は増巾器、109はAGC回路、110,111は
同期検波回路、112は論理回路、113はスイッチン
グ発振器である。
105 and 106 are buffer amplifiers, 107 is a switch, 1
08 is an amplifier, 109 is an AGC circuit, 110 and 111 are synchronous detection circuits, 112 is a logic circuit, and 113 is a switching oscillator.

切替回路107はスイッチング発振器113からのスイ
ッチング信号に応答して、増巾器105及び106から
の各受信信号を交互に切替えて出力する。
In response to the switching signal from the switching oscillator 113, the switching circuit 107 alternately switches and outputs each received signal from the amplifiers 105 and 106.

この切替回路107からの出力は、AGC回路付の増巾
器108を通過後、同期検波器110及び111に供給
される。
The output from this switching circuit 107 is supplied to synchronous detectors 110 and 111 after passing through an amplifier 108 with an AGC circuit.

同期検波器110及び111は、発振器11′3からの
スイッチング信号によって、切替回路107と連動する
ように構成されているので、これらの出力にはそれぞれ
AI及びA2に対応した受信信号が得られる。
Since the synchronous detectors 110 and 111 are configured to operate in conjunction with the switching circuit 107 by the switching signal from the oscillator 11'3, received signals corresponding to AI and A2 are obtained at their outputs, respectively.

論理回路112は、こうして得られる検波出力のレベル
を比較し、レベルの高い側の受信信号を選択するよう切
替回路103を制御する。
The logic circuit 112 compares the levels of the detected outputs thus obtained and controls the switching circuit 103 to select the received signal with the higher level.

つまり、この第1図の回路は2つの受信信号の変動に対
して、常に高い入力レベルをもつ側の受信信号を選択出
力する。
In other words, the circuit shown in FIG. 1 always selects and outputs the received signal having a higher input level in response to fluctuations in the two received signals.

本制御信号発生回路104は制御精変の点において優れ
ているが構成が複雑なため高価である。
Although the present control signal generation circuit 104 is excellent in terms of control refinement, it is expensive due to its complicated configuration.

また、従来の回路として第2図に示す例について訣明す
る。
Furthermore, an example of a conventional circuit shown in FIG. 2 will be explained.

121,122は増巾器であり、その利得はAGC回路
123,124により制御されている。
121 and 122 are amplifiers, the gains of which are controlled by AGC circuits 123 and 124.

入力端子114,115の信号レベルに従い、AGC回
路123,124の出力レベル125.126は変化し
、これら2つの信号を比較回路127にて比較し、切替
器103を制御する。
The output levels 125 and 126 of the AGC circuits 123 and 124 change according to the signal levels of the input terminals 114 and 115, and these two signals are compared in a comparison circuit 127 to control the switch 103.

この方式は第1図の方式に比較し、構成は簡単になるが
入力端子114,115対AGC回路出力端子125,
126の直線性があまり良くないため制御誤差を生じや
すい欠点がある。
This method has a simpler configuration than the method shown in FIG.
Since the linearity of 126 is not very good, there is a drawback that control errors are likely to occur.

本発明の目的は、従来のこれらの欠点を除去するために
考えられたもので、非常に簡単な構成で誤差の非常に少
ない制御を行うことができる受信信号制御回路を提供す
ることにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a received signal control circuit that has a very simple configuration and can perform control with very little error, which has been devised to eliminate these conventional drawbacks.

次に本発明を実施例により説明する。Next, the present invention will be explained by examples.

第3図は本発明の実施例の受信信号レベル検出回路を示
し、第4図は第3図の回路を使用した場合の切替器制御
の実施例の回路図を示す。
FIG. 3 shows a received signal level detection circuit according to an embodiment of the present invention, and FIG. 4 shows a circuit diagram of an embodiment of switch control when the circuit of FIG. 3 is used.

入力端子14に加えられた受信信号はリミッタ作用のあ
るn段より構成される飽和形増巾器11により増巾され
た後、一定のレベルとなり端子15より送出される。
The received signal applied to the input terminal 14 is amplified by a saturation type amplifier 11 composed of n stages having a limiter function, and then becomes a constant level and is sent out from the terminal 15.

端子14に加えられた信号レベルが低レベルの状態から
増加した場合には増巾器11は最終段の増巾器nから順
次前段に向い(n−1)、(n−2)・・・・・・2,
1と飽和するようになっている。
When the signal level applied to the terminal 14 increases from a low level state, the amplifiers 11 are sequentially directed from amplifier n at the final stage to previous stages (n-1), (n-2), etc. ...2,
It becomes saturated at 1.

これらのレベルを各段の出力に接続された検出器12(
1,2・・・n)で検出し、それ等の検波出力信号を加
算器13で加算し、端子16より制御信号として送出す
る。
These levels are detected by a detector 12 (
1, 2, .

第5図は検波回路5段の場合の第3図における端子14
人カレベル対各検波器12および加算器13出力端子1
6の出力レベル特性図であり、端子16からは非常に直
線性の良い信号が得られる。
Figure 5 shows the terminal 14 in Figure 3 in the case of a five-stage detection circuit.
Person level vs. each detector 12 and adder 13 output terminal 1
6, a signal with very good linearity can be obtained from terminal 16.

第4図は第3図の回路を使用し切替器を制御する場合の
1例であり、端子25.26に加えられたAI 、A2
の受信信号は第3図のレベル検出回路21.22にそれ
ぞれ加えられた増巾された後、切゛替器23にて選択さ
れ、出力端子27より送出される。
Figure 4 is an example of controlling a switch using the circuit shown in Figure 3, with AI and A2 applied to terminals 25 and 26.
The received signals are respectively amplified by the level detection circuits 21 and 22 in FIG. 3, selected by the switch 23, and sent out from the output terminal 27.

検出回路21.22よりの直線性のよい信号28.29
は比較回路24で比較され、両信号レベルの間にある規
定以上の差が生じた場合は切替器に信号を送り伝送品質
の良い方の信号を優先的に選択する。
Signals with good linearity from detection circuits 21 and 22 28 and 29
are compared in a comparison circuit 24, and if a difference greater than a certain standard occurs between the two signal levels, a signal is sent to a switch to preferentially select the signal with better transmission quality.

第4図の例はRF又はIP信号での切替した場合である
が、レベル検出回路21.22の後に復調器を用いるこ
とによりベースバンド信号での切替も同様な方法ででき
る。
The example shown in FIG. 4 is a case of switching using RF or IP signals, but switching using baseband signals can also be performed in a similar manner by using a demodulator after the level detection circuits 21 and 22.

又信号23の回路は切替器でなく合成画であってもよい
Further, the circuit for the signal 23 may be a composite image instead of a switch.

以上説明したように非常に簡単な構成で制御誤差の少い
制御回路が可能であり、これを使用することにより動作
安定で安価な切替装置および合成装置を構成することが
できる。
As explained above, a control circuit with a very simple configuration and little control error is possible, and by using this, a switching device and a combining device with stable operation and low cost can be constructed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は従来の受信制御回路のブロック図
、第3図は本発明の実施例のレベル検出回路のブロック
図、第4図は本発明の実施例のブロック図、第5図は第
3図の特性図である。 図において、IL 108,121.122・・・・・
・増巾器、12・・・・・・検波器、13・・・・・・
加算器、14゜25.26,114,115・・・・・
・受信入力端子、15.27,116・・・・・・出力
端子、16・・・・・・制御出力端子、23,103,
107・・・・・・切替器、24゜127・・・・・・
比較回路、28,29・・・・・・加算出力端子、10
1,102・・・・・・分岐増巾器、104・・・・・
・制御信号発生回路、105,106・・・・・・バッ
ファ増巾器、109,123,124・・・・・・AG
C回路、110.111・・・・・・同期検波回路、1
12・・・・・・論理回路、113・・・・・・スイッ
チング発振器、125゜126・・・・・・AGC出力
端子である。
1 and 2 are block diagrams of a conventional reception control circuit, FIG. 3 is a block diagram of a level detection circuit according to an embodiment of the present invention, FIG. 4 is a block diagram of an embodiment of the present invention, and FIG. 5 is the characteristic diagram of FIG. In the figure, IL 108, 121.122...
・Amplifier, 12...Detector, 13...
Adder, 14°25.26, 114, 115...
・Reception input terminal, 15.27, 116... Output terminal, 16... Control output terminal, 23, 103,
107...Switcher, 24°127...
Comparison circuit, 28, 29... Addition output terminal, 10
1,102...branch amplifier, 104...
・Control signal generation circuit, 105, 106...Buffer amplifier, 109, 123, 124...AG
C circuit, 110.111... Synchronous detection circuit, 1
12...Logic circuit, 113...Switching oscillator, 125°126...AGC output terminal.

Claims (1)

【特許請求の範囲】[Claims] 1 飽和形多段増幅器の各段毎に接続された検波回路と
、この検波出力を加算する加算回路とからなる入力受信
レベル検出回路を複数の受信系の各々に備え、かつこれ
ら受信系の検出回路の出力を比較し、その比較結果に応
答して前記複数の受信系の出力を合成又は切替え制御す
る回路を有する受信信号制御回路。
1 Each of a plurality of receiving systems is provided with an input reception level detection circuit consisting of a detection circuit connected to each stage of a saturation multistage amplifier and an adder circuit that adds the detected outputs, and the detection circuit of these receiving systems. A received signal control circuit comprising a circuit that compares the outputs of the plurality of receiving systems and controls the synthesis or switching of the outputs of the plurality of receiving systems in response to the comparison result.
JP52011967A 1977-02-04 1977-02-04 Reception signal control circuit Expired JPS5850059B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52011967A JPS5850059B2 (en) 1977-02-04 1977-02-04 Reception signal control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52011967A JPS5850059B2 (en) 1977-02-04 1977-02-04 Reception signal control circuit

Publications (2)

Publication Number Publication Date
JPS5396716A JPS5396716A (en) 1978-08-24
JPS5850059B2 true JPS5850059B2 (en) 1983-11-08

Family

ID=11792375

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52011967A Expired JPS5850059B2 (en) 1977-02-04 1977-02-04 Reception signal control circuit

Country Status (1)

Country Link
JP (1) JPS5850059B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0266364U (en) * 1988-11-11 1990-05-18
JPH0356442Y2 (en) * 1984-03-30 1991-12-18
WO2019008620A1 (en) 2017-07-03 2019-01-10 株式会社島津製作所 X-ray ct device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0356442Y2 (en) * 1984-03-30 1991-12-18
JPH0266364U (en) * 1988-11-11 1990-05-18
WO2019008620A1 (en) 2017-07-03 2019-01-10 株式会社島津製作所 X-ray ct device
US11002690B2 (en) 2017-07-03 2021-05-11 Shimadzu Corporation X-ray CT device

Also Published As

Publication number Publication date
JPS5396716A (en) 1978-08-24

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