JPS584947A - Manufacture for buried wiring layer - Google Patents

Abstract

PURPOSE:To obtain a flat surfaced multilayer wiring free of disconnections by a method wherein masking layers are formed having wiring patterns on conductive layers buried in an insulting layer and electroless chemical treatment is performed for the masks and conductors. CONSTITUTION:An Al layer C1 is piled on an SiO2 layer B1 on an Si substrate 1. A resist mask M1 is applied for the formation of an insulating layer I1 in an electroless chemical process. The mask M1 is dismantled and a window H12 provided Si3N4 film B12 and an Al layer C12 are successively laid down and a resist mask M12 is selectively provided above the window H12. Electroless chemical process follows for the formation of an insulating layer I12, and a connecting wiring layer W12 is formed. The mask M12 is removed and, again, a window 12 provided Si3N4 film B2 and an Al layer C2 are successively formed to be subjected to electroless chemical treatment for the formation of an insulating layer I2. Then mask M2 is removed. Thus, a flat surfaced multilayer wiring free of burial caused wiring disconnections is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a buried wiring layer suitable for use in forming multilayer wiring layers of a semiconductor integrated circuit device.

Various methods for forming buried wiring layers have been proposed in the past, but all of them require complicated processes, and even if it is possible to flatten the resulting buried wiring layer, it is difficult to flatten the resulting buried wiring layer. Therefore, even if we try to obtain a multilayer buried wiring layer, there is a certain limit to increasing the number of layers, and even if we try to make the resulting buried wiring layer even finer, There is a certain limit to the miniaturization, and for this reason, if the buried wiring layer can be made finer, the substrate on which the buried wiring layer is formed can be made smaller, but it is not possible to do so. It had drawbacks.

Therefore, the present invention proposes a novel method for forming a buried wiring layer that does not have the above-mentioned drawbacks, and this will become clear from the eight points detailed below.

FIG. 1 shows an example of a method for forming a buried wiring layer according to the present invention, which is applicable when obtaining a multilayer wiring layer of a semiconductor integrated circuit device. Prepare in advance a substrate 2 having a structure in which an insulating layer B1 made of, for example, aluminum oxide is formed on the surface of the substrate 1.
Then, a conductive layer C1 made of, for example, A is formed on the main surface of the substrate 2, that is, above the surface of the insulating layer B1 (FIG. 1B).

Next, on the surface of the conductive layer C1, a masking layer M1 made of, for example, photoresist and having a desired wiring pattern is formed by a method known per se (FIG. 1C).

Next, by electroless chemical conversion treatment on the conductive layer 01 using the mask layer M1 as a mask, the area of the conductive layer C1 other than under the mask layer M1 is Insulating layer 11 made of insulation
is formed to have approximately the same thickness as the conductive layer C1 (the first
#Al)). In this case, the electroless chemical conversion treatment is performed on the conductive layer C.
When 1 is Aj, electroless chemical conversion treatment is performed using an alkaline water bath liquid having a composition corresponding to the thickness of 1.
For example, when the conductive layer C1 has a thickness of about 1 μm, a bath solution prepared by mixing α11 aqueous ammonia and 50 g of ammonium persulfate in 1 μm of water is used as the alkaline aqueous solution. l of 60-80℃
Electrical layer C1 that can be heated to 1ltL for 10 to 30 minutes
The insulating layer 11 is made of conductive material made of AJ, @@C
The process is such that an oxide layer having a thickness of approximately the same as that of 1 is obtained.

1E) % Thus, a first buried wiring layer U1 having a structure in which the interconnection layer W1 is buried with the insulation 71I1 on the insulation layer B1 is obtained.

Next, on the surface of the first buried wiring layer U1, that is, on the wiring layer W1 and the insulating layer 11, a wiring layer W1 having resistance to electroless chemical conversion treatment similar to the above-mentioned electroless chemical treatment is applied. An insulating layer B12 made of silicon nitride, for example, having a window H12 facing the outside is formed (FIG. 1F).

Next, an insulating layer is formed on the surface of the insulating layer B12, as shown in FIG. On B12, it is connected to the wiring layer W1 through a window H12. A conductive layer C12 similar to the conductive layer C1 described above in FIG. 1B is formed in the same process as described above in FIG. 1B, and then! !
As shown in FIG. 1H, on the conductive layer C12.

At a position corresponding to the window H12, a mask layer M12 similar to the mask layer M1 described above in FIG. 1C is formed by a process similar to that described above in FIG. As shown in Figure I, by taking the same steps as described above in the first diagram,
Comply with l.

Insulating layer 1 described above in the first drawing to form a wiring layer connection layer W12 corresponding to the wiring layer W1 described above in the first drawing
1, and then a mask layer M
12), on the wiring layer W1, the wiring layer connection layer W12 is connected to the insulating layers B12 and 112.
A first buried wiring layer connection layer Q12 having a structure formed by trenching is obtained.

Next, on the surface of the 111111th embedded wiring j connection layer Q12, that is, on the wiring layer connection 4W12 and the insulating layer 112, a layer fj similar to the insulating layer B12 described above in FIG.
An insulating layer B2 having a window H2 that exposes the I-layer connection layer W12 to the outside is an insulating layer B2 on the substrate 1 described above in FIG.
1 is formed by the same process as described above in FIG. 1 (K in FIG. 1).

Next, on the surface of the insulating layer B2, a first layer of the insulating layer B2 is applied.
As shown in the first diagram, the insulating layer B1 on the substrate 1 described above is connected to the wiring layer connecting layer W12 on the insulating layer B2 through the window H2* #I
A conductive layer C2 similar to the conductive layer C1 described above in t'mA B is formed by a process similar to that described above in FIG. 1B, and then, as shown in FIG. Add the required wiring pattern to the top. However, the wiring layer connection layer W
A mask layer M2 similar to the mask layer M1 described above in FIG.
It is formed in the same process as described above in Figure 1Nk.
As shown in <% wt1, the same steps as described above are taken to connect to the wiring layer connection layer W12. In order to form a wiring layer W2 similar to the wiring layer W1 described above in the first drawing, an insulating layer 11 and an insulating layer I2 similar to P1 are formed in the first drawing, and then the mask layer M2 is removed. 1 O), thus, on the insulating layer B2, a second buried wiring layer U2 having a structure in which the wiring layer W2 to be connected to the wiring layer connection layer W12 is buried in the insulating layer 12 is formed. obtain.

Thereafter, the same process as described above is repeated, and the second, fifth, etc. buried wiring layer connection layers Q25, C54, etc. are formed on the second buried wiring layer U2. The buried wiring layers υ5, 04--... are obtained through the 3rd and 4th layers in sequence.The above is semiconductor integration. - This is an example of a method for forming a buried wiring layer according to the present invention which is applied when obtaining a multilayer wiring layer of a circuit device.
A wiring layer W2 is formed on the buried wiring layer U1 and connected to the wiring layer W1 via a wiring layer connection layer W12. Insulating layer I
2, the second embedded wiring layer U2.
. U2. −−−=−・ are each formed into a mask layer (Ml, M2−−−−−−) having a wiring pattern on the conductive layer (CI, C2−−−−)
A conductive layer (CI, C2-...-
) can be easily obtained as a flattened product through a simple process of electroless chemical conversion treatment, and therefore, even if a multilayer wiring layer of a semiconductor integrated circuit device is obtained as a large number of layers, the multilayer arrangement can be easily obtained. It can be easily formed as it does not have the habit of breaking the layer, and the buried wiring layer U
1, U2-...-m-- wiring layers W1, W2---
-------, conductive layer (C1゜C2...
) formed on the mask layer (Ml, M2...)
・-) patterns can be easily formed in a fine, self-aligned manner, thus eliminating the need to make the board unnecessarily bulky due to the embedded wiring layer. It has the following characteristics.

In this case, the improvement serial number is the conductive layer (CI, C2---...
... ;.

, C12, C23---1...) are Muj, but the conductive layer is AI.

Or, for example, an alloy containing AI, such as a 1-Bi alloy, is acceptable, but if it is an easily oxidized material that undergoes chemical oxidation and becomes an oxide through electroless chemical conversion treatment, it is not acceptable! (However, it is clear that various modifications and changes can be made without departing from the spirit of invention.

[Brief explanation of the drawing]

Figures A1 to A0 are line cross-sectional views in sequential steps showing an example of the method of forming a buried wiring layer according to the present invention. In the figure, 2 is the substrate, 01. C2 and C12 are conductive layers, Ml
, M2 and Ml2 are mask layers %W1 and W2 are wiring layers,
W12 is a wiring layer connection layer, 11% I2 and 112 are insulating layers, 81. B12 and B2 represent insulating layers, and H12 and H2 represent windows, respectively. Applicant Nippon Telegraph and Telephone Company - Seal < 1 Q Loco 1 〇

Claims (1)

[Claims] A process of forming a conductive layer on the substrate, a process of forming a mask layer having a wiring pattern on the conductive layer, and an electroless chemical conversion treatment for the conductive layer using the cough mask wide as a mask make m cough conductive. forming an insulating layer in which areas of the conductive layer other than under the mask layer are insulated to form a wiring layer in the area under the mask layer of the conductive layer. How to form wiring layers.