JPS5848585A - Digital receiver - Google Patents

Abstract

PURPOSE:To prevent the generation of noise at switching on a received screen, by switching the correcting characteristics of a correcting circuit which has a preset time interval to a vertical synchronizing signal and corrects a group delay characteristic, based on a vertical synchronizing signal and a detection signal. CONSTITUTION:A logical circuit 47 is connected between a logical circuit 42 and relay drive circuits 43 and 44. A vertical synchronizing signal is given to a logical circuit 47 from a vertical deflection circuit 18. When the relay drive circuits 43, 44 respectively switch relays 45, 46 based on detected pulses (a) and (b) outputted from a Fleming code comparator 41, the logical circuit 47 switches the relays 45, 46 with a preset time interval to the vertical synchronizing signal and provides a switching control signal just before or after the vertical blanking period to the relay drive circuits 43 and 44.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal receiver, and in particular, improves group delay characteristics in TV text multiplex reception where an O-track run-in signal and a framing code signal are sent sequentially before data. The present invention relates to a digital signal receiver.

τTeletext multilayer broadcasting is known as a digital transmission system for television broadcasting.

As is well known, this teletext broadcasting system consists of teletext broadcasting,
A digital signal representing data such as characters, 1m shape, etc. is input and transmitted within H (H-horizontal scanning period ■).

*iam is a diagram showing an example of a television text multiplex signal. FIG. 1 shows the 1H of the 20th H in the vertical blanking period in which character signals (data) are inserted in a television character multiplexing system. In other words, these two
In the 08th period, after a certain period of time from the color burst signal (CO> located on the back porch of the horizontal synchronization signal (Ha), the CRI signal consisting of the merging of the brass, rIJ, and rOJ is transmitted. ) and - An 8-pit framing code signal (FRC) following this CRI signal, and a data signal (OA) continuing from the pit of this FRC code signal to the end of 1H are inserted.

The 0RII@ is "1" as described above.

It is configured as a 16 or 18 pit signal consisting of a series of "0"s, and is the standard for 1IllJI when creating a sampling pulse for sampling the data 1ie (DA) in a television receiver. be. The FRC signal is an 8-pit code signal selected to provide 1-pit error protection, and is used as a time reference when the sampled data signal is converted in parallel by 8 pits. This is the result. There are many possible code configurations for this FRC signal, so it is only necessary to adopt an appropriate one among them. For example, NHK's 055 code is 11ioo1o.
i was adopted, and in the UK teletext system 1ii
oo1oo is adopted, and 11100111 is adopted in the French ante-aube system.

FIG. 2 is a schematic block diagram of the main parts of a conventional character multiplex signal receiver. In the figure, a text multiplex transmitter 10 transmits radio waves containing the TV text multiplex signal shown in FIG. This radio wave is received by receiver 11120 via an antenna. That is, the tuner or the video detector l1s21 included in the receiver 2o reproduces the video-confucian@ and TV text multiplex signals. Movie
The signal is applied to the video circuit 28, and the television character TAOROUSU@ is applied to the gate @s22. This gate 8Wi22 is a gate passage for extracting a character signal from 1H to 118 minutes into which a character multiplex signal is inserted from the detection output of the video detection circuit. The character signal extracted by this gate 111122 is slicer! 11123, which is sliced at 172 levels of amplitude and converted into a rectangular wave.

・Slicer 11s23. The character signal converted into a rectangular wave by
1611m! 26. The sampling clock reproduction 811124 is the first! CRI signal from among the characters shown in l.

This is used to create and use the sampling clock.

This sampling clock is the Fleming code detection point 1.
125. The fleming hood detection circuit 25 detects the FRC signal from the output signal of the slicer circuit 23, creates timing pulses for every 8 pits of the data signal based on the sampling clock, and sends them to the digital processing circuit 27.

The serial/parallel converter 1 path 26 samples and extracts a data signal from the output signal of the slicer circuit 23 using a sampling pulse, and converts the sequentially extracted data signal into a parallel signal by τ8 bits using a timing pulse. , the converted signal is sent to the digital processing circuit 2
Give to 7. Digital processing! The @ circuit 27 digitally processes the signals of each 8 pits so that they are displayed at appropriate positions on the television screen. The output signal of this digital processing circuit 27 is given to the video circuit 28. The video circuit 28 superimposes the character signal given from the digital processing circuit 27 on the television digital signal received from the video detection circuit 21 and supplies it to the receiver 1129.The conventional receiver is configured as described above. However, what should be noted here is that the modulator (II
(not shown) from the tuner or video detector in -20
This is the overall group delay characteristic up to output point A of 11121.

That is, in general, in a television receiver, the group delay characteristic of the tuner or video detection circuit s21 is selected so as to be canceled out by the group delay characteristic of the transmitter 10.

However, this is true only for the high frequency part (3 to 4 MH2 band) of the video signal band, and for the low frequency part (0 to 2 MH2 band) of the video signal band.
τ is not necessarily considered in this way. Therefore, the group delay characteristic at the 211th point A, that is, the transmitting device 1
The low-frequency part of the overall group delay characteristic including the 0 side and the receiver 20 side (hereinafter referred to as the low-frequency group delay characteristic) is flat in some cases a, and in other cases sloped, as shown in Figure 3. vinegar,.

This is determined by the group delay characteristics of the transmitter 10 and the tuner or video detector 121 in the receiver 20.

By the way, the pit rate of the above-mentioned multi-character signal is selected to be 5.73 Mb/s in the NHK 055 system, for example. For this reason, the clock run-in (
In the case of a signal in which rIJ and rOJ are repeated for each pit, such as the CRI) signal, the repetition frequency corresponds to 1/2 of the pit rate, or approximately 2.86 MH2. This means that CR11 is hardly affected by the low frequency part (0 to 2 MH2 band) of the group delay characteristic shown in FIG. 3 above.

On the other hand, the Fleming code in the character multiplex signal (FRC)
The signal (Dt'y rate is also 2, which is 5.73 Mb/3. However, as mentioned earlier, this FRC signal is not a periodic repeating signal for each bit,
This is relatively low for FRC signals (i.e. 2
This means that the FRC signal contains frequency components (below MH2), and therefore the FRC signal is affected by the low frequency group delay characteristic shown in FIG.

In addition, as a method for quantitatively determining the value of waveform distortion, there is a method of determining the eye-hide rate using an eye pattern, which responds to the increase in transmission distortion and the decrease in the eye-hide ratio.

FIG. 4 is a block diagram showing an example of improved τ group delay characteristics in conventional teletext reception. This Figure 4 is the same as Figure τ2 except for the following points.

That is, the tuner 211 and the video-intermediate frequency detection circuit 21
2, a group delay characteristic correction circuit 30 for correcting the group delay characteristic is provided. This group delay characteristic correction circuit 30 uses, for example, a surface acoustic wave filter, and has two correction characteristics.

In other words, as shown in FIG. 3(b) above, if the amount of delay in the low frequency region of the group delay characteristic is large, the delay amount is made small so that the group delay characteristic becomes as shown in FIG. 5(a). Correct it so that it is flat. Further, as shown in FIG. 3(0), when the delay amount in the low frequency region of the group delay characteristic is small, the delay amount is increased to make it flat. A Fleming code comparator 41 is provided to switch the correction characteristics of this group delay WLII correction path 3o. The Fleming code comparator 41 is supplied with the Fleming code signal received from the slicer circuit 23, and is also supplied with a sampling clock signal from the sampling clock copying circuit 24. Then, the Fleming code comparator 41 outputs pulses a and b for error detection due to the influence of the Fleming code d low frequency group delay characteristic, and outputs pulses a and b to the Ichimori circuit 42.
The logic circuit 42 controls the relay drive circuits 43 and 44 in response to the error detection pulses a and b.゛Then, when the low-frequency group delay characteristic is as shown in the 31st%lI('b), the relay drive circuit 4'4 turns on the contact of the relay 46 and corrects the group delay characteristic so that it becomes ``flat.'' .

In addition, when error detection/-"rus b is output, the relay dry pro path 43 turns on the contact of the relay 45 and the group delay characteristic becomes uniform as shown in FIG. 3(a). By correcting the group delay characteristic using the τ-delay characteristic compensation circuit 30 in this way, the influence of the group delay characteristic can be prevented.

However, the fourth of ε! As shown in II, a group delay characteristic correction circuit 30 is provided between the tuner 211 and the narrow-to-center frequency detection 1212,
By switching the correction characteristics of τ synchronization aim
may cause malfunction.

This means that, for example, the timing of a switching operation triggered by an error detection pulse is
5. This appears when passing through 46 and coincides with (2), and will seriously damage the received product. Furthermore, even when timing signal 1 is performed when the switching operation does not affect the vertical synchronization pulse, instantaneous noise appears on the reception screen, which also deteriorates the reception quality. Although this is instantaneous,
This is because the video intermediate frequency detection am is temporarily interrupted by the switching operation.

Therefore, the main object of the present invention is to provide a digital signal receiver that can eliminate the adverse effects caused by the above-mentioned switching operation and ensure a stable and good reception surface.

To summarize this invention, when detecting signal distortion caused by the group delay characteristics of the transmission system and switching the correction characteristics of the correction circuit based on the detected output, a certain preset value for the vertical synchronization signal is used. The control is performed so that the switching is performed with time intervals.

The above objects and other objects and features of the invention will become apparent from the detailed description given below with reference to WWJ.

"No. 5 is a diagram showing the electrode configuration of a surface acoustic wave filter as an example of the group delay characteristic correction circuit 30 included in an embodiment of the present invention, and No. 6 is a diagram showing its characteristics.

In recent years, surface acoustic wave filters have become widely used as bandpass filters for frequency amplification in the video of television receivers. Part 1 of this surface acoustic wave filter
filter amplitude by changing the electrode structure for surface wave excitation and detection.

For surface wave excitation, the phase characteristics (group delay characteristics) can be designed independently of each other.
The transducer is a so-called cross-oriented transducer (interdigital transducer, I
As shown in FIG. 6, a so-called regular type IDT 32 with a constant electrode crossing width and pitch is arranged on one side, and a so-called regular type IDT 32 with a constant electrode crossing width and pitch is arranged on the other side, and a desired amplitude 9 phase characteristics! 1,000 uni, electrode-intersection width.

pitch. l! It is common to have a configuration in which weighted IDTs are arranged to write data. In such a configuration, the elasticity table [1w1. The frequency characteristics of the filter are.

It is given as the product of the frequency characteristics of each IDT. Positive m type I
The characteristics of DT, 32 are determined by the electrode pit t and the number of electrodes,
7 The fluency characteristics are symmetrical to the center frequency,
The phase characteristic is linear and the group delay characteristic is constant.On the other hand, various methods have been used for the electrode film of weighted EDT, but the most common method is to use a surface acoustic wave filter. Determined from the specifications of the joint characteristics and the characteristics of the regular type ■ Find the time axis response by inverting the hospitality that 0T31 should have to 7-9, and calculate this so-called impulse response waveform. This is a method to determine the shape of the peak to be realized. This utilizes the impulse response of an elastic A-wave filter.

By the way, as shown in FIG. 6, the shape of the IDT designed by the above-mentioned method has asymmetrical amplitude characteristics and properties a.
Phase characteristics are not uniform (group delay characteristics are not constant)
According to the specifications, the electrode crossing width and pitch of the weighted IDT 31 are not constant and are asymmetrical.

Figure 7 is an example of a case where the weighted 1-poles of the surface acoustic wave filter are symmetrical! The 8th am is the same.
An example of a control case is shown in FIG.

911 and 10 are illustrative views of the propagation layer of the surface acoustic wave filter, and FIG.
．． FIG. 4 is a diagram for explaining the difference in characteristics depending on the propagation direction in the case of zero cause.

In FIG. 9, generally, one-plane waves radiated from the IDT 31 travel in opposite directions relative to the IDT 31 on the same propagation path. Usually the first one is on the propagation path of one of the bows.
As shown in FIG. 0, another regular type IDT 32 is arranged to form a filter. Now, as shown in FIG. 10, regular m-type IDTs 32 and 33 are placed on both sides of one weighted IDT 31, each having equidistant rods, and
Combination A of swollen IDT31 and regular IDT33
J5. k (Fll Mi attached e I DT31 Tosho 11!!
If we consider the filter characteristics for each of the adjustment B with IDT32, the amplitude characteristics a are the same as shown in Figures 11(a) and (b), but the group delay characteristics are reversed. I understand that. That is, it can be seen that the propagation function representing the characteristics to the combination and the combination B are in a conjugate relationship with each other. Therefore, Fig. 11 ('Jl
) and (b), the group delay characteristic can be made constant within the band of the filter.

FIG. 12 is a diagram showing the characteristics of a surface acoustic wave filter included in an embodiment of the present invention, and 13I!1 is a diagram showing lNl
FIG. 2 is a diagram showing the characteristics shown in FIG. 2 in terms of baseband.

As shown in FIG. 10 above, positive III! EDT32.3
For example, the frequency characteristic of combination A is set as 12111 (a), and the frequency characteristic of combination B is
The frequency characteristic of is set as shown in FIG. 12(c). and,
By adding both characteristics, the characteristics shown in FIG. 12(b) can be realized. When converted into baseband characteristics, these correspond to the characteristics shown in Nos. 1311(a) to 1311(C), and are found to be suitable as characteristics for correcting group delay distortion in a transmission path.

FIG. 14 is a schematic block diagram of an embodiment of the present invention.

This FIG. 14 is the same as FIG. 4 except for the following points.

In other words, it's a no-brainer! Circuit 42 and relay drive circuit 43
．． A logic circuit 47 is connected between the picture tube 44 and a vertical deflection circuit 18 for vertically deflecting the picture tube 29. A vertical synchronizing signal (V-8YNC) is applied to the logic 1 path 47. Based on the error detection pulses a and b output from the logic circuit 47&t Fleming code comparator 41, the relay drive circuits 43 and 44
゜46 respectively, the preset 〒9. Relay 4 with a fixed time jump interval
This is for switching between 5.46 and 5.46. In other words, theory M
＠Route 47 outputs a switching control signal to relay drive l1II43. immediately after or immediately before the vertical return period. ．． Give to 44. In this way, by switching the switching control signal to the relays 45 and 46 immediately or immediately before the vertical synchronization signal instead of using the vertical synchronization signal, the noise at the upper or lower end of -1 can be suppressed.
This reduces the impression that viewers have of an extremely poor reception-to-image relationship. Furthermore, if a speed switch 45 or 46 with a very fast response speed is used, it is expected that the generation of noise will be further reduced.

' Figure 15 is the theory I shown in Figure 14! This is a specific proof of circuits 42 and 47. In the configuration,
Logic path 42 includes inverters 421, 424, 426, and 429, AND gates 422, 425, 427, and 430, and OR gate 42313. a1147 is an O-type flip-flop 471.472 and a monostable multivibrator 47
3, the error detection pulses a, b and Dt given from the Fleming code quantulator 41 are
Based on the Q output signals of the J flip-flops 471, 4, and 72, switching control signals are applied to the O input ends of the D-type flip-flops 471, 472, respectively.

Type 0 flip-flop 4.71.472 is logic circuit 4.
This is for applying the switching control signal given from 2 to the relay drive circuits 43 and 44 in synchronization with the vertical synchronization signal. For this purpose, the vertical synchronizing signal output from the vertical deflection circuit 18 shown in FIG. 14 is applied to the monostable multivibrator 473. The monostable multivibrator 473 generates a D-type flip-flop '7471.4 by sending a timing signal immediately or just before the vertical return period.
Give to 72.

FIG. 16 is a rounding diagram illustrating the concrete operation of one embodiment of this invention.

Next, the specific operation of one embodiment of the present invention will be explained with reference to FIGS. 14 to 16. First, both SW4!1146 are turned OFF and τ group delay characteristic correction is performed. It is assumed that the correction characteristic of @'1130 is flat.At this time, the condition of the transmission path is such that the low frequency group delay characteristic is decreasing as shown in FIG. 16(1), and the Fleming code comparator 41 Assume that error detection pulse 1 is at H level and b is at L level.Then,
Referring to No. 158, the H level error detection pulse a is inverted by the inverter 421 and the AND gate 422
Close. This H level error detection pulse a is also applied to one input of the AND gate 427. AN
The L level output signal from the D-type flip-flop Otube 471 is inverted by an inverter 426 and applied to the other input terminal of the D gate 427 . Therefore, AND gate 427 is opened and an H level signal is applied to D-type flip-flop 472 via OR gate 428. and,
The vertical synchronization signal is given to the monostable multivibrator 473, and from this monostable multivibrator 473, the timing signal is OW! applied to flip-flop 472. Thereby, D.I.
! Flip-flop 472 is set and an H level signal is given to relay drive circuit 43.

On the other hand, since the error detection pulse b is at the L level,
AND gate 425 is wIUed. No, as mentioned above, the AND gate 422 is also closed, so the D-type flip-flop 471 is not set.
No switching control signal is given to the relay drive circuit 44. The relay 45 is turned on by a switching signal from the relay drive circuit 43, and the correction characteristic of the group delay characteristic correction circuit 1130 increases in the low frequency range. Therefore, since the low frequency group delay characteristic of the transmission path is decreasing and the correction characteristic is increasing, the group delay characteristic can be made substantially flat.

Moreover, as shown in FIG. 16 (2), when the low frequency group delay characteristic is 1 and the error detection pulse a is at the L level and becomes the bSH level, contrary to the above explanation, Dg! Flip-flop 471 is set and it is D type! /Flop 472 is reset. Therefore, the contacts of relay 46 are turned on and the contacts of relay 45 are turned off. Then, since the correction characteristic of the group delay characteristic correction@path 30 decreases, it becomes possible to make the entire characteristic cost line qrtn. e
Uni, either relay 4-5 or 46 - power is ON
1661(3) or 6)
When it becomes as shown in Fig. 3, one of the relays 45 and 46 is turned on, or both of them are turned off to make the overall characteristic almost flat.

As described above, according to the present invention, the signal distortion caused by the group delay characteristic of the transmission system is detected, and the detected signal and W
Based on the IJW1 signal, the correction characteristics of the correction 1 and the group delay characteristics are switched based on the IJW1 signal and the correction characteristics of the group delay characteristics are changed using a preset period of time relative to the synchronous signal. Noise will no longer occur when switching over. Therefore, it is possible to eliminate the harmful effects caused by switching operation.
Stable and good reception can be ensured.

[Brief explanation of the drawing]

FIG. 15 is an illustrative diagram showing an example of a television text multiplex signal. FIG. 2 is a schematic block diagram of the main parts of a conventional character multi-word signal reception book. FIG. 3 is a diagram showing group delay characteristics. 4I11 is a schematic block diagram showing an example of a conventional receiver with improved group delay characteristics. FIG. 5 is a diagram showing an electrode configuration of a surface acoustic wave filter as an example of a group delay characteristic correction (c) path included in an embodiment of the present invention. , 6th
The figure also shows the characteristics of a surface acoustic wave filter. FIG. 7 is a diagram showing an example of weighting of the elastic surface to be filtered when the electrodes are symmetrical. FIG. 8 is a diagram showing an example of a similarly asymmetrical case. Figures 9 and 10 are illustrative diagrams for explaining the propagation state of the surface acoustic wave filter, and Figure 11 is a diagram for explaining the difference in characteristics depending on the propagation direction in Figure 10. be. FIG. 12 is a diagram showing the characteristics of a surface acoustic wave filter included in an embodiment of the present invention. -131% II is a diagram showing the characteristics shown in FIG. 12 in terms of baseband. FIG. 14 is a schematic block diagram of an embodiment of the present invention. Figure 15 is the 14th
It is a detailed block diagram of the 11th logic shown in the figure. 16th
FIG. 1 is a diagram for explaining the specific operation of an embodiment of the present invention. In the figure, 30 is If! Discuss the extension characteristic correction circuit, 41 is the Fleming code comparator, 42.47 &! 1 circuit, 421, 424, 426.429 are inverters, 42
2,425,427.430 is an AND gate, 423.
428 is the OR gate, 471.472 is Og! Flip-flop, 473, monostable multivibrator, 43.
44 is a relay drive circuit, and 45 and 46 are relays. Patent Applicant Sanyo Electric Co., Ltd. Figure 1 Figure 3 False Figure 6 Figure 9 810 - Figure 11 (a) 2. Name of the invention Digital receiver 3. Relationship with the case of the person making the amendment Patent applicant address 2-18 Keihan Hondori, Moriguchi City, Osaka Prefecture Name
(18B) Sanyo Electric Co., Ltd. Representative Iue
Kaoru 4, Agent Address 41!2-3-9 Tenjin, Kita-ku, Osaka Yachiyo Daiichi Pill Spontaneous Amendment Claims H of the specification to be amended and Detailed Description of the Invention HAO Column 7 of the amendment Contents (1) S tsuba of the patent claim is attached. (2) Specification 1g, page 9, line 11, line 11〇[
jI for pigeon lofts with a large amount of flyover in the low range! "Reduce the amount of extension" is corrected to "If the low-range g is slow, make it negative, that is, lead the phase." (3) Specification omission 9j [jlxa line to line 1114 “
If the amount of delay in the low frequency range is small, oj! ``Increase the amount of flies'' should be corrected to ``If the low frequency region -fi is out of phase, make it positive or slow.'' (4) Change rIDTJ on the 3rd line of the 13th member of the specification to “IDT3
Correct to 1J. (5) "Fourier inverse transform" in line 14 of al13 Sada of the specification
Correct it to ``Fourier inverse transform.''
Correct. (7) In the 20th member, line 11 of the specification - LJ112 line [descending], the correction characteristic is rising i, so d is ``phase leading, and the correction characteristic is slow phase -, so, ” is corrected. (8) “Rising” on page 20, line M15 of the specification
〇 (9) On page 1N, page 21, jl, line 1 of the specification, ``because it falls,'' is corrected to ``because it is a slow phase,'' to ``because it is an advanced phase.'' 0 Above 2, Claims ゛ (1) Digital signal reception in which a clock run-in signal that determines the data sampling timing and a lemming code signal that determines the parallel conversion timing of the sampled data are transmitted prior to the data.
Detecting means for detecting signal distortion that the Fleming code signal or the group delay characteristic detection code signal undergoes due to the group delay characteristic of the transmission system from the transmitting side to the digital signal receiver; A correction circuit that is provided in a video intermediate frequency amplification circuit included in the aircraft and includes a correction circuit that corrects the group delay characteristic, and a switching means that switches the correction characteristic of the correction circuit in accordance with a detection signal of the detection means, Further, switching control means receives the detection signal and the vertical synchronization signal, and controls the switching means so as to switch the correction characteristic with a predetermined constant correlation with respect to the vertical synchronization signal. A digital signal receiver with special features. (2) The digital signal receiver according to claim 1, wherein the switching control means includes means for prohibiting the switching means from switching during a vertical retrace period. (3) The digital signal receiver according to claim 1 or 2, wherein the switching IIJID means includes means for switching the switching means immediately before or after a pre-vertical blanking period. 4771

Claims (3)

[Claims] (1) A clock run-in signal that determines the data sampling timing, a clock run-in signal that determines the parallel conversion timing of sampled data, and a framing code signal that determines the parallel conversion timing of sampled data precede the data. A digital signal receiver that detects signal distortion that the Fleming code signal or group delay characteristic detection code signal receives due to group 1III characteristics of a transmission system from the transmitting side to the digital signal amount am. detection means; a correction circuit provided in a video intermediate frequency amplification circuit included in the digital signal receiver and correcting the group delay characteristic; and switching the correction characteristic of the correction circuit in accordance with a detection signal of the detection means. and a switching means, further configured to receive the detection signal and the vertical synchronization signal and switch the correction characteristic at a predetermined time interval with respect to the vertical synchronization signal. 1. A digital signal receiver comprising switching control means for controlling Ilw. (2) Digital signal reception-1 according to claim 1, wherein the switching control means includes means for prohibiting the switching means from switching within the vertical retrace period. (3) The digital signal receiver according to claim 1 or 2, wherein the switching control means includes means for switching the switching means immediately before or during the vertical retrace period.