JPS5848527A - Timer circuit - Google Patents

Abstract

PURPOSE:To accurately and easily set time, by assembling two stages of inverters having a suitable ratio between the 1st capacitor and the inverter input terminal and increasing the voltage of the 1st capacitor. CONSTITUTION:A potential change of a capaitor CL is received at an offset circuit 20 consisting of two stages of inverters comprising transistors Q8-Q11. Then, taking around 1V of the threshold voltage of an output inverter and a linear region of discharge characteristic of a charge pump up to about 2V into consideration, the timer set time accuracy can be increased by using this region only. Thus, the inverting amplification of the inverter is applied, the offset amplifier consisting of the two stages of the inverters is constituted without losing the logic and the ratio of the inverters is set to a suitable value, allowing to easily correct the deviation from the threshold value of the output inverter.

Description

[Detailed description of the invention] This summary relates to timer circuits.

In the MU8 dynamic random access memory, in order to prevent the memory and accumulated charge from disappearing over time, it is necessary to perform the 7-receipt operation within a certain period of time.Normally, an external clock and an external clock are used to perform this operation. By supplying address No. 11, it is necessary to access a predetermined shared address, and in a memory device using this, a timer circuit that counts the waiting time and a timer circuit that generates a predetermined address are required. Therefore, in order to simplify these peripheral circuits, it is necessary to install an address counter in the vicinity of the address counter, which results in double-tracking of the peripheral control circuit. Therefore, in order to simplify these peripheral circuits, the above-mentioned timer circuit and address counter are mounted on the same chip. With the advent of the M08F Dynamic AM with a refresh function, this function can be achieved with just 7 refresher control bins, which has a significant effect on simplifying peripheral control circuits and improving packaging density. You can expect.

In order to realize the auto-refresh function, the introduction of the tie 7 circuit is essential.

The cycle value is 2ms/1, which has become very common.
If 28 cycles are adopted, it will be necessary to refresh once within approximately 15j18 for l memory 7 l. ◎ Tie 1 circuit will be 1 - memory 7 k"k h 1
The circuit that controls the maximum time allowed for D7 resetting (1) is usually counted by a binary counter, and the charging/discharging time for the capacitor C, so-called 03
Application of time constant, capacitor C using charge pump circuit
A circuit that utilizes a fixed amount of discharge of the charged charge can be considered.

As shown in FIG. 1, a conventional charge pump timer circuit includes a capacitor Cx, a transistor Q1 that charges it to a predetermined potential, a charge pump capacitor Op, a transistor Q6 that controls it, and transistors Q2 to Q2.
It consists of a constant charge discharge control circuit consisting of Q5, a high impedance load 11 for generating an internal refresher control signal in response to potential changes at one node A, and an inverter 10 consisting of a transistor Q7. Then, the external controller input is activated and a refresh cycle begins, refreshing the series of memories associated with the word line with the given address.

A clock lp is generated during the active operation period for refreshing, and the transistor Q1, which receives this clock at its gate, becomes O
F+11. , charges the capacitor CL.

When the refresh tool operation is completed, a control is activated to automatically shift to the precharge state, and lp is reset at the same time. Clock already supplied from the internal oscillator circuit! , and door, charge pump circuit and discharge charge control circuit - capacitor C
L starts discharging a certain amount every cycle of clock y51-1m. A series of circuit operations are as follows.

``First of all, Clockda, ahead of Akame, rises.

Turn on the transistor Q6, keep the sardine point B at the ground potential, and then increase the voltage.
When the 0 clock that charges the voltage drops.

The voltage at node B of the capacitor CPK drops sharply in the negative direction from the ground potential. When the potential difference between node B and the ground potential exceeds the threshold of transistors Q'4 and Q5, transistors Q4. Q5 turns on, and in response to this, the potential at each node and point C also drops, and transistors Q2' and Q3 also turn on□
do. )'Fnjistar Q2. When Q3 turns on, discharge from the sensor CL via these transistor resistors starts. At this time, transistors Q2 and Q5' are simultaneously turned on and receive charge from the power supply It operates to suppress the potential drop at nodes B and C.
. The amount of charge discharged per cycle from the capacitor CL, the cloff, and the charge from the capacitor CL is determined by the transistor Q2.
Compared to the case where Q5O does not exist, it can be reduced,
This can be adjusted arbitrarily depending on the size of the transistor capacity. As a result, the amount of charge discharged per cycle from the capacitor CL can be set arbitrarily.

As shown in FIG. 2, the potential at node A shows a constant potential drop every cycle, and has the advantage that the time until it reaches the threshold of the output inverter, that is, the timer time, can be easily calculated. However, if we take the discharge characteristics of a conventional timer circuit and take the precharge potential of node A on the horizontal axis and the amount of potential drop of the random capacitor Ct per cycle on the vertical axis, the third
As shown in the figure, it is found that d is linear, and N in the figure is trunks Q2. Q5 transistor Q3. Q
Mizuko's ability ratio to 4. According to this, in any case of N, the amount of potential drop depends on the potential of node A, and decreases at an approximately constant rate, and the voltage drops from 1.5 to 2. , it can be seen that it decreases rapidly near OV. Furthermore, if the MO8) resistor constituting the circuit is of the N-channel type, a value around 1V is usually adopted in consideration of ease of manufacture, so the output inverter has a potential of node A of l. ■The timer time setting line in a timer circuit using an inverter with a value near the threshold lv, which starts operation and generates a start signal In for internal 7 resetting, only when the voltage drops to around the threshold lv. , since the non-linear region of region (1) must also be used, this has the disadvantage of extremely deteriorating the 1-hour setting N[(0). Considering the yield, it is not common.

The present invention seeks to remedy one or more disadvantages.

It is made completely.

A detailed explanation will be given below with reference to an embodiment.〇Figure 4 shows an embodiment of the invention. ,
Although an offset circuit 20 is inserted between two stages of inverters made up of transistors Q8 to Qll, the operation of the charge pump circuit made up of transistors Ql to Q6 is basically no different from the conventional example shown in FIG.

A first load transistor whose drain and gate are generally connected to a power supply and whose source is connected to an output terminal.

) An inverter consisting of a second driving transistor whose drain is connected to the output terminal, whose source is grounded, and whose gate is applied with an input signal exhibits an input/output transfer characteristic as shown in FIG. According to this, from the point where the input voltage exceeds the threshold of the second transistor, the second transistor becomes ONI, and the output voltage gradually decreases, and decreases almost linearly within the input voltage range of 1 to 3V. This produces a 1-inversion amplification effect. This inversion amplification effect is well known, and it is clear that the gain can be controlled arbitrarily by varying the ratio of the transistors that make up the inverter.@The threshold value of the output inverter is around 1V. Considering that the discharge characteristic of the charge pump circuit shown in FIG. 3 is in a linear region at about 2vt, it is possible to improve the accuracy of timer time setting by using only the radial region. For this reason, an offset amplifier consisting of two stages of inverters is constructed to take advantage of the inverting amplification effect of the inverter and to avoid compromising the logic.

By setting the inverter ratio to the appropriate
For example, the transistor QB in FIG. 5 can easily correct the difference between the output inverter and the threshold value.

The ratio of the ml inverter consisting of Q9 is 2. By setting the value of the second inverter consisting of the transistors QlO and Ql1 to 4, the offset of the capacitor CL can be set to 4 (0) where the potential drop of the capacitor CL changes linearly. potential is 2V
When K is reached, the 0 output inverter which obtains the offset of the offset amplifier alV and generates the output of IV receives this and operates to generate an internal reset signal 6.

The potential change in the offset amplifier will be explained using FIG. 5. As the potential of the capacitor CL (potential of node I) passes through the charge pump circuit and receives a certain amount of charge discharge, it gradually decreases and reaches around 2V.
The first inverter output node y transitions from point 1' to l in the figure and obtains a potential of about 2V. In response to this, the second inverter.

The output node ``transitions from point 1 to 2'' in the figure.

The 0 output inverter that obtains the output voltage IV receives the potential change at the node ", and generates the signal y5m.

In this way, in a timer circuit consisting of a charge pump circuit and an inverter having a threshold value of about 1 energization IV, the @ line region of the discharge characteristic of the charge pump circuit is used, and the 1 inversion amplification effect is skillfully utilized to improve the timer time accuracy. The effect of introducing the offset circuit is enormous.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional circuit. Figure 2 is a diagram showing its operation. ◇ Figure 3 is based on the charge pump circuit used in Figure 1; Figure 4 is a diagram showing the discharge characteristics of the capacitor. Figure 4 shows an embodiment of the present invention. It is a diagram. Fifth
The figure shows a general input/output transfer percentage of an inverter. Symbols in the figure %Ql-Qll...--MOS transistor, CP, CL-----Capacitor 0 (A isolation, voltage) Plexus 3 Figure z 4 Figure

Claims (1)

[Scope of Claims] Means for charging a capacitor jIl controlled by an external signal fal, a second capacitor driven by a second external signal, and a drain connected to the other end of the second capacitor. a charge pump means comprising a transistor having a gate driven by a third external signal and a source grounded; and the sources are both #I1 node Km! A pair of connected transistors and a gate are connected to one end, and one drain is connected to the power supply K. Another drain is connected to the first node Km, and the sources are both connected to the other end of the g2 capacitor and have a high impedance negative *t- discharge means for the first capacitor consisting of another pair of transistors. an inverter, and two stages of inverters having an appropriate ratio are installed between the first capacitor and the inverter input terminal to increase the inverter lift of the high impedance load. A timer circuit 0 characterized in that time setting becomes accurate and easy by increasing the potential of a capacitor.