JPS5846866A - Control type dc-dc converter - Google Patents

Control type dc-dc converter

Info

Publication number
JPS5846866A
JPS5846866A JP56143331A JP14333181A JPS5846866A JP S5846866 A JPS5846866 A JP S5846866A JP 56143331 A JP56143331 A JP 56143331A JP 14333181 A JP14333181 A JP 14333181A JP S5846866 A JPS5846866 A JP S5846866A
Authority
JP
Japan
Prior art keywords
output
switching
center
taps
tap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56143331A
Other languages
Japanese (ja)
Other versions
JPS6259549B2 (en
Inventor
Yuji Fukushima
福島 裕司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56143331A priority Critical patent/JPS5846866A/en
Publication of JPS5846866A publication Critical patent/JPS5846866A/en
Publication of JPS6259549B2 publication Critical patent/JPS6259549B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE:To reduce the current effective value component and the ripple component for the titled converter by a method wherein two center taps for an output transformer are provided, and an output waveform is formed into a stepped pulse waveform by switching these taps. CONSTITUTION:The two center taps are provided on the input side wiring of the output transformer 5, and switching transistors 14 and 14' are operated alternately at the phase difference of 180 deg. by the driving pulse sent from a two-phase pulse generator 15. The transistors 14 and 14' are synchronized with the operation of the main switching transistors 4 and 4', maintaining certain phase difference phi, and as a result, the switching waveform is formed into a stepped pulse waveform (b). The high and low time ratio of the switching waveform Vs on the output side is change with varied phase difference ranging 0-180 deg., and the output voltage V0 is controlled. Accordingly, the current Ip on the input side is turned to a stepped waveform, and this enables to reduce the effective value and the ripple component of the titled converter when compared with that of the converter heretofore in use.

Description

【発明の詳細な説明】 本発明は、′直流電源を入力とし所要直流電圧の出力を
得るDO−noコンバーターに関するもので、特にスイ
ッチング方式O出力電圧安定化機能を備えた制御形DO
−DOコンバーターに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DO-no converter that receives a DC power source as an input and outputs a required DC voltage, and particularly relates to a DO-no converter that uses a DC power source as an input and outputs a required DC voltage.
- This relates to a DO converter.

一般にDO−Doシコンーターは出方電圧が高安定で変
換効率が高くかつ小型、軽量のものが望まれている。こ
のニーズに応えるものとしてスイッチング、レギュレー
ターが広く用−られるよう(なった。このスイッンダレ
ギュレーターは直流入力電源をトランジス倉等のスイッ
チング素子で断続し、これを短形波パルスに変換しトラ
ンス等で変圧し、整流、平滑回路を経て直流出方を得て
いるが、同時にスイッチングパルス巾を制御し出方の安
定化を図っている。第1図はこの従来例の基本回路を示
す構成図である。第1図に於てlは直流入力電源、4.
4′はスイッチングトランジスタでプッシュプル構成の
ものである。5#i出カドランス、6.6′は整流ダイ
オード、7はチョークコイル、8はコンデンサ、10t
j出力側負荷を示し、更に111fi駆動パルスの2相
パルス発生器、12はパルス巾変調回路、13は出力電
圧の誤差電圧を検出する誤差電圧検出器を各々示すが、
通常は・上記の11%12.13等F11個のLgI化
されたものを使用する。本回路は一般にセンタータップ
方式のプッシュプルDo−DCコンバーターと呼称され
る1ので、その動作について祉周知であるので簡単に説
明する。入力直流電源IFiスイッチングトランジスタ
4.4′によって1800の位相角で交互にスイッチン
グされ、出方トランス5の出力側K11i短形波交流パ
ルスが発生する。ごの出力パルスはダイオード6.6′
によるセンタータップ ′方式の全波整流回路で整流さ
れ、チョークコイル7及びコンデン−f8によ抄平滑、
直流化されて負荷10C供給される・出力側IIcは誤
差電圧検出器が接続されており、出力電圧が設定値よ抄
ずれた場合そ、の誤差分を検出増巾するようKなってお
り、その検出、信号をパルス巾変調回路12に加え駆動
パルスの巾(デユーティ−比)を変えて出力電圧を設定
値に保持するようになっている。本回路方式のスイッチ
ング電圧及び電流波形は第3図(a)に示すように設定
値からDポテンシャルまでスイングした所■短形波パル
スであ抄、リップル電圧、電流分が多いと言える。一般
にこのリップル電圧、電流分が大きいとその実効値が一
大、するので種々の弊害が発生する。例えば第3図(a
)K於ける入力側電流IPにつ−て見れば、このリップ
ル分は入力コンデンサ3に流れるので、入力コンデンサ
3II′iこれに耐える為に大形コンデンサが必要とな
るし、その他回路各部のオーミッタを損失も大きくな9
、変換効率を下げる結果にもなる。又、出力側電流IL
K″:)−ても同様でチョークコイル7のインダクタン
スが大自〈なり形が大きくなる。以上のように従来方式
に於ては構成部品が大形となり炊事も低下すると言った
問題があった。
Generally, DO-Do converters are desired to have highly stable output voltage, high conversion efficiency, small size, and light weight. Switching regulators have become widely used to meet this need.The switcher regulator uses a switching element such as a transistor to interrupt the DC input power, converts it into a rectangular wave pulse, and converts it into a rectangular wave pulse. The DC output is obtained through voltage transformation, rectification, and smoothing circuits, and at the same time, the switching pulse width is controlled to stabilize the output.Figure 1 is a configuration diagram showing the basic circuit of this conventional example. In Fig. 1, l is a DC input power supply, and 4.
4' is a switching transistor of push-pull configuration. 5#i output transformer, 6.6' is rectifier diode, 7 is choke coil, 8 is capacitor, 10t
j indicates the output side load, and further indicates a two-phase pulse generator with 111fi drive pulses, 12 a pulse width modulation circuit, and 13 an error voltage detector for detecting the error voltage of the output voltage.
Usually, the above-mentioned 11% 12.13 etc. F11 LgI is used. This circuit is generally called a center-tap push-pull Do-DC converter, and since its operation is well known, it will be briefly explained. The input DC power source IFi is alternately switched at a phase angle of 1800 by the switching transistor 4.4', and a rectangular wave AC pulse is generated at the output side K11i of the output transformer 5. The output pulse of each is diode 6.6'
It is rectified by a full-wave rectifier circuit with center tap ' method, and smoothed by choke coil 7 and condenser f8.
The output side IIc is converted into DC and supplied with a load of 10C. An error voltage detector is connected to the output side IIc, and it is designed to detect and amplify the error when the output voltage deviates from the set value. The detected signal is applied to the pulse width modulation circuit 12, and the width (duty ratio) of the drive pulse is changed to maintain the output voltage at a set value. As shown in FIG. 3(a), the switching voltage and current waveforms of this circuit system can be said to be rectangular wave pulses with large ripple voltages and currents when they swing from the set value to the D potential. Generally, when the ripple voltage and current are large, their effective value becomes large, which causes various problems. For example, in Figure 3 (a
) Regarding the input side current IP at K, this ripple flows to the input capacitor 3, so a large capacitor is required to withstand this, and the ohmitter of other parts of the circuit is also required. The loss is also large9
, it also results in lowering the conversion efficiency. Also, the output side current IL
Similarly, the inductance of the choke coil 7 becomes larger in the case of K'':)-, and the shape becomes larger.As mentioned above, in the conventional method, there was a problem in that the component parts were large and the cooking efficiency was reduced. .

本発明はかかる問題点を改善しようとするもので、スイ
ッチング波形を階段状とし各部のリップル電圧、電流分
を減じ構成部品゛の小型化及び回路損失の軽減化を図り
小型軽量で高効率かつ価格も安い制御WIDO−DCコ
ンバーターを提供することを目的とする。
The present invention aims to improve such problems by making the switching waveform step-like, reducing the ripple voltage and current at each part, downsizing the component parts, and reducing circuit loss. Another object of the present invention is to provide a low-cost controlled WIDO-DC converter.

本発明による回路構成は、直流入端子とこれに接続され
、た2個の主スイツチングトランジスタと出力)ランス
と前記主スイツチングトランジスタを駆動する第1の2
相パルス発生器等から構成されるセンタータップ方式の
プツシ五プルインバーター回路とこのインバーター回路
の出力部KIII続されたセン;−タップ方式の余波整
流回路とこれに縦続するチ冒−タインプット形LOフィ
ルター回路と出力端子とから構成されたDo−DOコン
バータ(於て、特に前記インバーター回路の、前記出カ
ドランスに於て1次側巻線のセンタータップを巻線中央
から対称に位置する2箇所に設けて該センタータップ各
々に2個のセンタータップ切換用スイッチジグトランジ
スタを直列に接続し、更に該タップ切換用スイッチング
トランジスタを駆動する位相制御用入力端子及び周波数
同期用入力端子を備えた第2の2相パルス発生器及び前
記出力端子に接続され出力電圧の誤差分を検出する誤差
検出器とを附加し前記第1の2相パルス発生器の同期信
号を前記第2の2相パルス発生器の周波数同期用入力端
子に接続し、前記誤差電圧検出器の検出信号を前記第2
の2相パルス発生器の位相制御用入力端子に接続し、構
成したものである。
The circuit configuration according to the present invention includes a DC inflow terminal, two main switching transistors connected thereto, an output lance, and a first two main switching transistors that drive the main switching transistors.
A center-tap type push-pull inverter circuit consisting of a phase pulse generator, etc., an output section of this inverter circuit connected to a sensor-tap type rectifier circuit, and a transistor input type LO connected in series to this. In a Do-DO converter consisting of a filter circuit and an output terminal (in particular, in the output transformer of the inverter circuit, the center tap of the primary winding is located at two locations symmetrically from the center of the winding). a second center tap switching transistor provided with two center tap switching switching transistors connected in series to each of the center taps, and further provided with a phase control input terminal and a frequency synchronization input terminal for driving the tap switching switching transistors; A two-phase pulse generator and an error detector connected to the output terminal to detect an error in the output voltage are added, and the synchronizing signal of the first two-phase pulse generator is applied to the second two-phase pulse generator. is connected to the frequency synchronization input terminal, and the detection signal of the error voltage detector is connected to the second frequency synchronization input terminal.
This configuration is connected to the phase control input terminal of a two-phase pulse generator.

即ち本発明は、インバーター回路の出方トランスのセン
タータップを2偏設けこれを切換えることにより出力波
形を階段状のパルス波形とし、この実効値分及びリップ
ル分を滅することにょ抄その目的を達するものである。
That is, the present invention achieves its purpose by providing two center taps on the output transformer of the inverter circuit, and by switching between them, the output waveform becomes a stepped pulse waveform, and the effective value and ripple components are eliminated. It is.

第3図はこの波形の相違を説明する為のスイッチング波
形図である。第3図(1)に従来方式の入力側電流IP
を例としたスイッチング電流波形を・示し、・第3 [
(b)に本発明による同図(3)と相応するスイッチン
グ電流波形を示す。同図(a)の平均m ′I!011 電流t!I、   /、、であるが、与、!は基準化し
であるのでTonとなる。第3図(b)の平均電流Fi
IP@T’on + Ip (IIIN)・T’off
となるが、Ip(WIN)=Ton(WIN)が初期条
件として投入すると結局とれは、 〒’on + Ton (MIN ) e T’Off
となる。よって、 Ton =−T’on + Ton (M I N )
 −’I”off ”−= (1)を得る。
FIG. 3 is a switching waveform diagram for explaining the difference in waveforms. Figure 3 (1) shows the input side current IP of the conventional method.
The switching current waveform is shown as an example, and the third [
(b) shows a switching current waveform corresponding to (3) in the same figure according to the present invention. The average m ′I! in (a) of the same figure. 011 Current t! I, /,, but give,! Since it is standardized, it becomes Ton. Average current Fi in Figure 3(b)
IP@T'on + Ip (IIIIN)・T'off
However, if Ip (WIN) = Ton (WIN) is input as the initial condition, the result is 〒'on + Ton (MIN) e T'Off
becomes. Therefore, Ton = −T'on + Ton (M I N )
-'I"off"-= (1) is obtained.

又、第3図(11)、(b)各々の平均電力に対する実
効分は次式によって示される。
Further, the effective component for each average power in FIG. 3 (11) and (b) is shown by the following equation.

第311(a)’の実効分= 1 / Ton  −”
−==””凹曲[21第3図(暑)と(b)の実効分比
即ち第3図(b)実効分/第3図(a)実効分は(1)
、(2)、(3)式よりとなる。但し、?’off =
 1− ’F’国 である。
Effective portion of Section 311(a)' = 1/Ton −”
−==”” Concave curve [21 The effective component ratio of Figure 3 (hot) and (b), that is, Figure 3 (b) effective component / Figure 3 (a) effective component is (1)
, (2) and (3). however,? 'off =
1- It is 'F' country.

?’on (或−は!軸)の変化に対しこの実効公比が
どのよ′うに変化するかを示したのが113 Wi(C
)のグラフである・Ton (MIN)をパラメータと
し、こ0 Ton(WIN)は必要とする制御限界値に
ょ゛り決められるが、通常o、5〜0.7である。第3
 [(C)のダラ7から、本発明による回路方式である
第3図(b) CJ方が電流の実効分は低いことがわか
る。更に第311 (11)、(b)に於て平行斜線で
示した部分がリップル分となるが、第3図(a)の方が
そのビ′−タ値が大1〈な抄リップル実勢電流は大きく
なることがわかる。
? 113 Wi (C
) is a graph with Ton (MIN) as a parameter, and Ton (WIN) is determined depending on the required control limit value, but is usually o, 5 to 0.7. Third
[From Dala 7 in (C), it can be seen that the effective component of the current is lower in the circuit system according to the present invention, that is, the CJ circuit shown in FIG. 3(b). Furthermore, the portion indicated by parallel diagonal lines in Fig. 311 (11) and (b) is the ripple component, but in Fig. 3 (a), the beater value is larger than 1, and the actual ripple current is It can be seen that it becomes larger.

第4図に本発明による第1の実施例の回路構成を示す。FIG. 4 shows a circuit configuration of a first embodiment according to the present invention.

第4図に於いて、第1図に示した従来例の回路構成と同
一記号を付した構成要素は、全くこれと同一機能のもの
でその動作も同様である〇即ち基本的にはセンタータッ
プのプッシュプル方式のDO−DOコンバーターである
。以下相違点のみを説明する。。出カドランス50入力
側巻線IK:2個のセンタータップが設けられており、
これは巻線中央に対称の位置に設けられている。トラ、
ンジスタ14.14’はこの2個のタップを交互に切換
える為のスイッチングトランジスタで、このスイツチン
グトランジスタ14.14’は第2の2相パルス発生器
15からのドライブパルスによって180゜の位相差で
交互に動作する。この2相パルス発生器15は第1の2
相パルス発生l5llからの同期信号によりこれと同期
しかつ誤差検出器15の出力信号により位相制御を受け
る。即ちタップ切換用のFランジメタ14.14’は主
スイツチングトランジスタ4.4′の動作と同期しかつ
これと成る位相差φで動作・している。したがつそその
スイッチング波形は階段状のパルス波形となる。この模
様は第t @ (b)に示した各部のスイッチング波形
を見れば明らかとなる。即ち同図にお―でトランジスタ
4.4′のスイッチング波形とトランジスター4.14
′のスイッチング波形は周期が同期し位相差φ(この場
合トランジスタ4と14’、)ランジスタ4′と14と
の位相差をいう)を有しているーこの位相差φをO〜1
80@変化させることにより出力側スイッチング波形v
8の高低時間比率が変化し出\ 力電圧マ、が制御されることが分る゛。この波形v8の
高低差Ili出カドランスの2個のセンタータップの位
置により決定されるがその値は出力電圧V、の所要制御
中によって決定される。この制御中は最大出力電圧V、
030〜50%程度に通常設定される@もし出力電圧V
、が鳥一方にずれた場合は誤差電圧検出器の出力信号に
よ秒位相差φは小の方に制御され、これによってV、は
下がる方向となり、よってV、は−電値に安定化される
。入力側の電流IPはは図示の如自MR状の波形である
ので前述した様に従来例に比べその実効値およびリップ
ル分は小さくなる。尚出力側に於てもその電流■、もリ
ップル分カ小さくなる。これは工、のリップル分Δ工し
ハ本実施例の場合、ΔIL= 譬、、6で表わさ2れ、
この式中のφは従来例に比べ小さくなるのでΔILI/
′i小さくなる。尚、スイッチングトランジスタ14.
14’の士vc、が高くなる場合はこ、れに耐える双方
向性トランジスタを使用する必要がある。
In Fig. 4, the components with the same symbols as the circuit configuration of the conventional example shown in Fig. 1 have exactly the same function and operation as this, i.e., basically the center tap. This is a push-pull DO-DO converter. Only the differences will be explained below. . Output transformer 50 input side winding IK: Two center taps are provided,
This is located symmetrically to the center of the winding. Tiger,
The transistor 14.14' is a switching transistor for alternately switching these two taps, and this switching transistor 14.14' is driven by a drive pulse from the second two-phase pulse generator 15 with a phase difference of 180°. Works alternately. This two-phase pulse generator 15 is a first two-phase pulse generator.
It is synchronized with the synchronizing signal from the phase pulse generator 15ll and receives phase control by the output signal of the error detector 15. That is, the tap switching F range metal 14.14' operates in synchronization with the operation of the main switching transistor 4.4' and with a phase difference φ corresponding thereto. Therefore, the switching waveform becomes a step-like pulse waveform. This pattern becomes clear when looking at the switching waveforms of each part shown in t@(b). In other words, in the same figure, the switching waveform of transistor 4.4' and the switching waveform of transistor 4.14 are shown.
The switching waveforms ' have synchronized periods and have a phase difference φ (in this case, the phase difference between transistors 4 and 14') - this phase difference φ is O~1
80@By changing the output side switching waveform v
It can be seen that the output voltage is controlled by changing the high/low time ratio of 8. The height difference Ili of this waveform v8 is determined by the positions of the two center taps of the output voltage, and its value is determined by the required control of the output voltage V. During this control, the maximum output voltage V,
@ Output voltage V which is usually set to about 030-50%
When , shifts to one side, the second phase difference φ is controlled to be small by the output signal of the error voltage detector, and as a result, V, decreases, and therefore, V, is stabilized at a negative value. Ru. Since the current IP on the input side has a waveform similar to the MR shape shown in the figure, its effective value and ripple are smaller than in the conventional example, as described above. Furthermore, on the output side, the current (2) is also reduced by the amount of ripple. This is the ripple of ΔIL, which is expressed as ΔIL=,6 in the case of this embodiment.
Since φ in this formula is smaller than the conventional example, ΔILI/
'i becomes smaller. Note that the switching transistor 14.
When the value of 14', vc, becomes high, it is necessary to use a bidirectional transistor that can withstand this.

第5図は第2の実施例の回路構成図を示す。本実施例社
第1の実施例に比べてタップ切換に、よる出力電圧の制
御安定化回路を入力側から出力側に移した場合の1ので
ある。即ち出カドランスの出力側巻線に2個のセンター
タップを設けてこれをタップ切換用のスイッチングトラ
ンジスタ14.14’を接続構成したもので、その動作
は第1の実施例と同様であるので省略する。この第2の
実施例では出力電圧の安定化は出力側で行なっているの
で多出力構成の場合、各出力に本安定化回路を投砂れば
各出力を容易に安定化させることが出来る。
FIG. 5 shows a circuit diagram of the second embodiment. This embodiment is compared to the first embodiment in which the output voltage control stabilization circuit based on tap switching is moved from the input side to the output side. That is, two center taps are provided on the output side winding of the output transformer, and switching transistors 14 and 14' for tap switching are connected to these center taps, and the operation thereof is the same as that of the first embodiment, so the description thereof will be omitted. do. In this second embodiment, the output voltage is stabilized on the output side, so in the case of a multi-output configuration, each output can be easily stabilized by applying this stabilizing circuit to each output.

以上の説明から分る様に本発明によれば、各部の電流実
効値が小さく又リップル分も小さくなるので回路損失の
減少、入力コンデンサの小型化、又出力側チ■−タコイ
ルの小型化等が可能であり全体として高効率で小型の制
御形Do−Doコンバーターが実現出来る。又特に多出
力形の場合は各出力の・安定化が簡単な回路で行えるの
で低価格な多出力制御形DO−Doコンバーターが実現
出来る。
As can be seen from the above explanation, according to the present invention, the effective value of the current in each part is small and the ripple component is also small, so circuit loss is reduced, the input capacitor is made smaller, and the output side converter coil is made smaller. This makes it possible to realize a highly efficient and compact controlled Do-Do converter as a whole. In particular, in the case of a multi-output type, each output can be stabilized with a simple circuit, so a low-cost multi-output control type DO-Do converter can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第111IIi従来例を示す回路構成図、第2図は従来
例と本発明に係る第10実施例の各部動作波形を示した
図、第311!従来例と本発明に係る実施。 例との特徴を説明する波形比較図、第4図は本発明に係
る第1の実施例の回路構成図、第5vliは本発明に係
る第2の実施例の回路構成図である。 1・・・入力直流電源、  2.2′・・・入力端子、
3・・・入力コンデンサ、 4.4′・・・主スイッチングFテンジスタ、5−i1
$カシランス、6.6’・・・ダイオード、7・・・チ
曹−タコイル、  8・・・コンデンサ、9.9′・・
・出力端子、  10・・・負荷、11・・・第102
相パルス発生器、 12・・・パルス巾変調器、 13・・・誤差電圧検出
器、14.14’・・・タップ切換用スイッチングトラ
ンジスタ、15・・・第2の2相パルス発生器。 代理人  弁理士 染 川 利 吉 第2図 (a)       (b) 第3図
No. 111 IIi A circuit configuration diagram showing a conventional example, FIG. 2 is a diagram showing operation waveforms of each part of the conventional example and a tenth embodiment according to the present invention, and No. 311! Conventional example and implementation according to the present invention. FIG. 4 is a circuit configuration diagram of the first embodiment according to the present invention, and No. 5vli is a circuit configuration diagram of the second embodiment according to the present invention. 1...Input DC power supply, 2.2'...Input terminal,
3... Input capacitor, 4.4'... Main switching F tensor, 5-i1
$Casillance, 6.6'...Diode, 7...Catacoil, 8...Capacitor, 9.9'...
・Output terminal, 10...Load, 11...102nd
Phase pulse generator, 12... Pulse width modulator, 13... Error voltage detector, 14.14'... Switching transistor for tap change, 15... Second two-phase pulse generator. Agent Patent Attorney Toshikichi Somekawa Figure 2 (a) (b) Figure 3

Claims (1)

【特許請求の範囲】[Claims] (1)  直流入力端子と、これに接続された2個の主
スイツチングトランジスタと、出力)ランスと、前記主
スイツチングトランジスタを駆動する為の一第1の2相
パルス発生器等から構成された方形波交流出力を取り出
すセンタータップ方式のプツシプにインド−ター回路と
↓該インバーター回路の出力側に縦続接続されたセンタ
ータップ方式の全波整流回路と、チョークインプット形
I0フィルター回路と、出力端子と、から構成されたD
O−DOコン−バーターに於て、特に前記インバーター
回路の前記最カドランスに於て、1次側巻線のセンター
タップを巻線中央から対称便蓋の2箇所に設°け、該セ
ンタータップ各々に2個のタップ切換用スイッチングト
ランジスタを直列接続し、更に該タップ切換用スイッチ
ングトランジスタを駆動する為の位相制御用入力端子及
び周波数同期用人。 力端子を備えた#2t)2相パルス発生器及び前記出力
端子に接続おれ出力電圧の誤差分を検出増巾する誤差電
圧検出器とを附加し、前記第1の2相パルス発生器から
の同期信号を前記第2の2相パルス発生器の周波数同期
用入力端子に接続し、前記誤差電圧検出器の出力信号を
前記第2の2相パルス発生器の位相制御用入力端子に接
続し、構成したことを特徴とする制御形DO−DOコシ
パーのセンタータップ及びこれに接続された前記タップ
切換用スイッチングトランジスタの構成部分を前記出カ
ドランスの出力側巻線センタータップ側に移酸し構成し
たことを特徴とする特許請求の範W第1111e載Lt
制御 HD O−D O=i ンA −fi
(1) Consists of a DC input terminal, two main switching transistors connected to this, an output lance, and a first two-phase pulse generator for driving the main switching transistor. An inverter circuit is connected to a center-tap pushbutton that takes out a square wave AC output. A center-tap full-wave rectifier circuit is connected in cascade to the output side of the inverter circuit, a choke input type I0 filter circuit, and an output terminal. D composed of and
In the O-DO converter, in particular, in the most quadrant of the inverter circuit, the center taps of the primary winding are provided at two locations on the toilet lid symmetrically from the center of the winding, and each of the center taps is Two switching transistors for switching taps are connected in series to the switching transistors for switching taps, and an input terminal for phase control and a frequency synchronization terminal for driving the switching transistors for switching taps are connected in series. #2t) A two-phase pulse generator equipped with a power terminal and an error voltage detector connected to the output terminal to detect and amplify the error in the output voltage, connecting a synchronization signal to a frequency synchronization input terminal of the second two-phase pulse generator; connecting an output signal of the error voltage detector to a phase control input terminal of the second two-phase pulse generator; The center tap of the controlled DO-DO cosiper characterized in that the center tap and the constituent parts of the tap switching switching transistor connected thereto are transferred to the output side winding center tap side of the output transformer. Claim W No. 1111e Lt characterized by
Control HD O-D O=i InA-fi
JP56143331A 1981-09-11 1981-09-11 Control type dc-dc converter Granted JPS5846866A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56143331A JPS5846866A (en) 1981-09-11 1981-09-11 Control type dc-dc converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56143331A JPS5846866A (en) 1981-09-11 1981-09-11 Control type dc-dc converter

Publications (2)

Publication Number Publication Date
JPS5846866A true JPS5846866A (en) 1983-03-18
JPS6259549B2 JPS6259549B2 (en) 1987-12-11

Family

ID=15336291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56143331A Granted JPS5846866A (en) 1981-09-11 1981-09-11 Control type dc-dc converter

Country Status (1)

Country Link
JP (1) JPS5846866A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02276477A (en) * 1989-02-06 1990-11-13 Lincoln Electric Co Improved output regulating circuit for inverter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02276477A (en) * 1989-02-06 1990-11-13 Lincoln Electric Co Improved output regulating circuit for inverter

Also Published As

Publication number Publication date
JPS6259549B2 (en) 1987-12-11

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