JPS5846459U - semiconductor element - Google Patents

semiconductor element

Info

Publication number
JPS5846459U
JPS5846459U JP14038681U JP14038681U JPS5846459U JP S5846459 U JPS5846459 U JP S5846459U JP 14038681 U JP14038681 U JP 14038681U JP 14038681 U JP14038681 U JP 14038681U JP S5846459 U JPS5846459 U JP S5846459U
Authority
JP
Japan
Prior art keywords
lead terminals
semiconductor element
package
displaying
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14038681U
Other languages
Japanese (ja)
Inventor
西元 幸一
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP14038681U priority Critical patent/JPS5846459U/en
Publication of JPS5846459U publication Critical patent/JPS5846459U/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すicの斜視図、第2図
は第1図のn−n矢視断面図、第3図は本考案を適用し
た一実施例の回路図である。 1・・・パッケージ、2・・・電源用リード端子、3・
・・グランド用リード端子、4・・・入力信号、出力信
号、その他用者リード端子、5・・・表示口、6・・・
ICチップ、7・・・ワイヤ、8・・・発光ダイオード
、9・・・抵LIO−・・アノ−ド、11・・・カソー
ド。
Fig. 1 is a perspective view of an IC showing an embodiment of the present invention, Fig. 2 is a sectional view taken along the line nn in Fig. 1, and Fig. 3 is a circuit diagram of an embodiment to which the present invention is applied. . 1...Package, 2...Power supply lead terminal, 3.
...Ground lead terminal, 4...Input signal, output signal, other user lead terminal, 5...Display port, 6...
IC chip, 7... Wire, 8... Light emitting diode, 9... Resistor LIO-... Anode, 11... Cathode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リード端子付きの半導体素子において、前記リード端子
の通電動作状態を表示する発光物質を、前記リード端子
のパッケージへの取付端部に設けたことを特徴とする半
導体素子。
1. A semiconductor device with lead terminals, characterized in that a light-emitting substance for displaying the energization operating state of the lead terminals is provided at an end portion of the lead terminals attached to the package.
JP14038681U 1981-09-24 1981-09-24 semiconductor element Pending JPS5846459U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14038681U JPS5846459U (en) 1981-09-24 1981-09-24 semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14038681U JPS5846459U (en) 1981-09-24 1981-09-24 semiconductor element

Publications (1)

Publication Number Publication Date
JPS5846459U true JPS5846459U (en) 1983-03-29

Family

ID=29933547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14038681U Pending JPS5846459U (en) 1981-09-24 1981-09-24 semiconductor element

Country Status (1)

Country Link
JP (1) JPS5846459U (en)

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