JPS5845628A - Address reading method for optical recorder - Google Patents

Abstract

PURPOSE:To surely access tracks, by using a different error correcting system of address information formatted as pit information in advance from that of data information to be additionally recorded. CONSTITUTION:Reproduced digital information 61 is separated into addresses and data with an address data separating circuit 62. The addresses and the data are respectively error-corrected at error correcting circuits 63, 65. Since the address information produced with pressing through formatting in advance has different error characteristics from that of data information recorded afterward, and since the error correcting system suitable for the respective errors is used, correct detection of the address information can be done and the high- speed accessing to tracks can surely be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) The present invention relates to a method for reading address information from a grooved disk that has been formatted in advance in an optical recording apparatus that records and reproduces information using a light beam.

Conventionally, this type of device accesses a target track or sector to perform additional recording and random access reproduction of information, so as shown in FIG. The address information 13 is engraved, and the new information is in the DC groove 14.
It has a structure that is written to. The address information has a structure as shown in FIG. 2, for example, in the format of analog recording of one rotation I TV frame.

FIG. 2 shows one rotation of the track, 21 is an index marker cage indicating the beginning of the track, 22 is a synchronization signal, 23 is a track number, 24 is the same track number as the duplicated track number 23, 25 is an FCC (error correction code), each of which is pre-engraved with a digital code. Reference numeral 26 denotes a data area, which is an area in which additional data is recorded as necessary. FIG. 3 shows an example of formatting when recording digital information, where 31 is an index marker, 32 is a synchronization signal,
33 is the track number. Following this < 34, 35
, 36, . . . , 37 represent sectors. This sector is formatted, for example, in the format shown in FIG. 41 is sector gap, 42 is synchronization signal, 43 is track number, 44 is sector number, 45 is FC
C. Groove information is inscribed in advance in these hatched areas using digital code. 46 is a data area to be additionally recorded, and 47 is an ECC of the data area to be additionally recorded.

Since the address information previously engraved by formatting is mass-produced using a press, there is a drawback that the probability of error occurrence is higher than that in the data section (DC groove) that is additionally recorded later.

On the other hand, in optical recording, the track spacing is extremely narrow, making it difficult to access with the mechanical precision of a magnetic disk. In order to bring the difference close to zero while making a judgment using the track logic circuit 55,
The method is to gradually approach the target truck. Therefore, if there is an error in the read address information, the light beam will not approach the target and will instead move away from the target, resulting in a disadvantage that high-speed access operations will not be possible.

In order to eliminate these drawbacks, the present invention, in part, makes the error correction function of the pre-engraved groove information (address information) stronger than the error correction function of the data section. Secondly, it provides an address information reading method that has an added function of recognizing the correct address number by calculating address information that is reproduced in duplicate, and will be explained in detail below with reference to the drawings.

FIG. 6 is a block diagram showing the configuration of an embodiment of the present invention, in which 61 is digital information reproduced by a light beam;
62 is an address and data separation circuit.

63 is an address section p correction circuit, and 64 is an address number.

65 is a data section error correction circuit, and 66 is data.

(4) In this embodiment, the error characteristics of the address section, which is inscribed in advance as groove information, are different from the error characteristics of the additionally recorded data section, as shown in FIG. 7, 71 and 72, respectively. Correct detection of address information is made possible by employing error correction methods suitable for each dropout length 2 occurrence frequency. Note that the address/data separation circuit 62 is realized by changing the modulation method for both the address and data, or by using the difference in reproduction signal level caused by the difference in the depth of the grooves between the two.

FIG. 8 shows another embodiment of the present invention. In this example, the sixth
The configuration is such that an address recognition circuit 81 is added after the address section υ correction circuit 63 shown in the figure.

The address recognition circuit 81 operates as shown in FIG.

That is, in the groove information formatted as shown in FIG. 2 or 3, the adjacent addresses Ai and Ai++ are read and set in the register 6 each time the disk rotates, and Ai and Ai+1 are compared to find a match. If so, it will be output as a correct address, and if it does not match, the addresses Ai++ and Ai+2 will be read in the next rotation.
Perform the same operation below. The number of repetitions is set depending on the error characteristics of the groove information. If there are two pre-engraved addresses as in the example shown in FIG. 2, and they do not match, the track is moved to an adjacent track and the same operation is performed.

FIG. 1O shows an example of a match determination circuit for addresses Ai and Ai++ in which the address is composed of 16 bits.

101 is the AI address read into register 1.

102 is the Ai+1 address read into register 2.

103, 104, 105, and 106 are half adder circuits.

The output (Xn, Xl, X2, -X1s) - indicates that AI and Ai++ match.

Note that the half adder circuit can be constructed as shown in FIG.

111 is negation, 112 is negation, and 113 is exclusive OR.

As explained above, for address information with a high error rate, one is that we have added a more powerful error correction function compared to data information, and the other is that we have added an address recognition function using multiple address information. By doing this, correct address information can be reused, which prevents access operations from diverging in random access operations on optical disks, and allows asymptotically approaching the target track, even when using disk media with a high error rate. This has the advantage of speeding up access operations as a result.

[Brief explanation of the drawing]

Figure 1 shows a formatted optical disc, Figure 2 shows an example of track formatting for analog recording, Figure 3 shows an example of track formatting for digital recording, and Figure 4 shows sector formatting. example,
FIG. 5 is an explanatory diagram of track access operation on an optical disc, FIG. 6 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is a diagram showing a false error occurrence situation, Figure 8 is another embodiment of the present invention, Figure 9 is a principle diagram of address recognition, Figure 10 is a circuit diagram for address matching determination, and Figure 11 is a half addition circuit diagram. be. 13... Address area carved in advance (signal groove), 14... Additional recording area (DC groove), 21...
Index marker, 22... Synchronization signal, 23.24
... Torano (7) 37... Sector, 41... Sector gap, 42...
...Synchronization signal, 43...Track number, 44...Sector number, 45...ECC%46...Data area,
47... ECC, 61... Optical reproduction digital information,
62...Address/data separation circuit, 63...Address part error correction circuit, 64...Address number, 65...
...Data section error correction circuit, 66...Data, 81.
・Address recognition circuit, 103, 104, 105, 10
6...Half adder circuit. Patent Applicant Nippon Telegraph and Telephone Public Corporation Patent Attorney Hisashi Tamamushi (3 others) (8)

Claims (1)

[Claims] 1. An error correction method for address information formatted in advance as groove information in an optical recording device that optically records and reproduces analog information such as video and audio, and digital information such as documents and data. A method for reading and searching for an address in an optical recording device, characterized in that the method is different from the method for correcting errors in data information to be additionally recorded. 2. The error correction method for the address information formatted in advance as groove information consists of reading a plurality of pieces of address information and recognizing the correct address number by comparing and determining whether the pieces of address information match. An address reading method in an optical recording device according to claim 1, characterized in that: