JPS5845114B2 - handmade takiokusouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a nonvolatile, electrically rewritable semiconductor device that includes an insulated gate field effect semiconductor memory device using a ferroelectric material as a gate insulator and has a pseudo-random access function. It is related to storage devices.

The idea of controlling electrical conduction on a semiconductor surface through spontaneous polarization of a ferroelectric material to create a nonvolatile semiconductor memory device has been around for a long time, but it has been difficult to form a ferroelectric thin film on a semiconductor substrate, so it has not been developed until now. The research carried out was limited to thin film transistors in which semiconductors were deposited on ferroelectric substrates, and because it was difficult to integrate them, they were not put into practical use.

Subsequently, a type of method was proposed and developed in which charge is injected into the gate insulating film from the semiconductor surface and the injected charge induces charge on the semiconductor surface, which is completely different in principle from the method that utilizes the spontaneous polarization of ferroelectric materials. It is being advanced.

However, the MN, which seems to be the most developed of this type,
OS (Metal-81licon N1tri
deSi 1icon -0xide -3em 1
Even when looking at memories using conductors, they have the disadvantage of high write/erase voltages.

Furthermore, by improving this type and adopting an avalanche injection method, it became possible to perform random access operation with a unipolar voltage without separating the substrate, but the avalanche injection method generally uses bipolar power supplies. requires a larger write/erase voltage than when using

In addition, in the case of this type, there is a restriction that voltage must be applied to the source and drain at the same time in order to achieve uniform writing across the entire channel (IEICE Semiconductor and Transistor Research Group Materials, 5SD74
-13).

Therefore, when forming a memory or an array, the gates of the switching MOS transistors added on both sides of the source and drain of the MNOS memory transistor constituting the memory or cell are commonly connected, and the two switching MOS transistors are connected in common.
The OS transistors are driven simultaneously.

Further, as a problem associated with these, there is a drawback that the peripheral circuits inevitably become complicated.

The invention of the present invention is based on the establishment of a technology to form a ferroelectric bismuth titanate thin film on a silicon substrate, and a ferroelectric insulated gate electric field that controls the electrical conductivity of the semiconductor surface by spontaneous polarization of the ferroelectric material. Developed an effect transistor.

The memory retention characteristics of the product that the present inventors can actually provide as a product were determined by actually measuring and extrapolating the change in channel conductance between the source and drain for up to 105 seconds. It is so excellent that it required 103° years.

Conventionally, memory elements using ferroelectric materials have often been considered in comparison with magnetic cores using ferromagnetic materials (
It was even said that the spontaneous polarization reversal electric field of ferroelectric materials is unstable and difficult to apply to memory elements.

In order to discuss the ease with which polarization reversal occurs and its stability, it is convenient to use the activation electric field α, which represents the applied electric field sufficient to cause polarization reversal. If it is too small, it may not be of practical use.

In 1970, Mr. Taylor (G, W, Taylor) published an article in the European journal Ferroelectrics J, Vol. 1, No. 7.
In the paper published on pages 9 to 86, we report that the reversal time t8 of spontaneous polarization shows the following relationship using the activation electric field α and the electric field strength E applied to the ferroelectric material, and also Bismuth oxide exhibits a specifically large activation electric field α, and in the high electric field region where the applied electric field E is 5 or more/c1rL or more, α is 25.
It was reported that the spontaneous polarization reversal time was 0.1 μsec or less when the applied electric field E was assumed to be infinite.

However, even with the activation electric field α in this report,
Moreover, it is too small to be used for application to ferroelectric insulated gate field effect transistors.

For example, when a ferroelectric insulated gate field effect transistor is constructed using this bismuth titanate thin film, a surface potential of about 1 V is inevitably generated on the semiconductor surface, and therefore an anti-electric field is generated within the ferroelectric thin film.

Due to this anti-electric field, the memory that you want to store will gradually volatilize, but if we use the above-mentioned activation electric field value and day value as the reversal time, we will assume that the thickness of the bismuth titanate film is 1 μm. Assuming that, using the above relational expression, the spontaneous polarization reversal torture t8 is approximately 151 tsec.

In other words, the stored content quickly evaporates even without applying any external voltage.

Based on such analysis results, the present inventors have made efforts and found that the activation electric field value α is 1.5×10' to 7×106v/
By perfecting a manufacturing method for a special bismuth titanate film exhibiting cIrL, they succeeded in making a ferroelectric insulated gate field effect transistor, which had been said to be impossible, a reality, as mentioned above.

The present invention uses this ferroelectric insulated gate field effect transistor as a memory cell of a semiconductor memory device.

Figure 1 is a diagram for explaining the write and erase characteristics of a ferroelectric insulated gate field effect transistor. Taking a P-channel type as an example, the drain voltage is kept at -1V and a sine wave of about IHz is applied to the gate. This figure shows a hysteresis curve between the gate voltage VG and the drain current D when .

At this time, as shown in Figure 1, where the source and substrate are grounded, a low voltage of about ±15V is sufficient for writing and erasing (
It will be seen that it is possible to perform rewriting).

Now, let's consider constructing a memory by combining a large number of ferroelectric insulated gate field effect transistors, which have now become a reality.

Let us now consider a memory in which ferroelectric insulated gate field effect transistors are arranged in a two-dimensional matrix X, Y.

When thinking about how to rewrite this memory, line
It is normal to try to rewrite only the elements at the intersection of XY by applying half of the voltage required for writing to the lines in column Y, and applying a voltage with the same absolute value and opposite polarity to the lines in column Y. be.

However, this magnetic core memory-like driving method is not very suitable for ferroelectric insulated gate field effect transistors.

This is because half of the electric field sufficient to reverse polarization is always applied to memory elements other than those at the intersection, working in the direction of volatilizing the memory contents (hereinafter referred to as being subject to half-selective disturbance).

Furthermore, this driving method requires a power source capable of supplying bipolar write and erase voltages, which is also a major drawback.

The purpose of the present invention is to simplify the peripheral circuitry, which has a low write/erase voltage, does not require substrate separation, operates with a unipolar power supply, and allows writing/reading with the gate insulating film receiving almost no half-selective disturbance. An object of the present invention is to provide a highly reliable ferroelectric insulated gate field effect transistor memory device.

Next, one embodiment of the present invention will be described with reference to the drawings.

What will be described here is an embodiment in which a p-channel ferroelectric insulated gate field effect transistor is used as the memory element.

FIG. 2 is a schematic diagram showing a cross section of an example of a ferroelectric insulated gate field effect transistor using a bismuth titanate thin film as a gate insulator.

A p-type source region 2 and a drain region 3 are provided on an n-type silicon substrate 1, a bismuth titanate film is formed on the silicon substrate between the source region 2 and the drain region 3 by high-frequency sputtering, and the shape is adjusted by etching. After that, a heat treatment is performed to crystallize the ferroelectric bismuth titanate film 4 which is a gate insulating film.

On top of this, for example, a multilayer metal layer of Ti-Pt-Au is applied.
The gate electrode 5 is closed.

The source electrode 6 and the substrate electrode 8 are grounded, and the drain electrode 7 is biased to -IV, and the sine wave of IH7 is applied to the gate electrode 5.
FIG. 1, which was explained earlier, shows an example of the hysteresis characteristics of the drain current ■D and the gate voltage vG when the voltage is applied to the gate voltage vG.

The direction of this hysteresis is opposite to that of a device such as MNOS that utilizes charge injected into a trap in an insulating film.

At this time, the P-E hysteresis with respect to the electric field E and spontaneous polarization P applied to bismuth titanate is I.

-Depending on vG hysteresis, move above the solid line in Figure 3 by 11 →
Moves in the order of 12 → 13 → 14 → 15 → 16 → 11 (.

When there is no external electric field, E is 0, so spontaneous polarization P is 1
2 or 15, and these two states are stable due to the nature of the ferroelectric material.

For example, when the memory transistor is at position 12, a channel is formed between the source and drain due to charges induced on the semiconductor surface between the source and drain due to its spontaneous polarization, and the memory transistor becomes on state at position 15. At this point, the channel disappears and the transistor is turned off.

This hysteresis can be created by grounding the gate electrode instead of applying a positive voltage to the gate electrode and applying a voltage between at least one of the source and drain and the substrate.

On the other hand, when integrating transistors, electrical isolation between peripheral circuits and memory parts becomes complicated, so it is desirable to apply a negative voltage only to at least one of the source and drain without applying voltage to the substrate.

When a negative voltage is applied to the gate with respect to at least one of the source and drain, the direction between the source or drain and the substrate becomes forward, so a voltage is applied to the bismuth titanate, even if the transistor is in the off state. , 15→16 in Figure 3
→At 19, a channel is created between the source and drain.

Furthermore, even if a channel is formed, a voltage is applied between the channel and the gate, and the reversal of spontaneous polarization progresses, eventually 19 → 11 →
12, the Qn state is completely established.

By the way, if you ground the gate to the substrate and apply a negative voltage to both the source and drain, if a channel is formed, the bismuth titanate ferroelectric material between the channel and the gate will be A voltage is applied to the film, and the transition changes from 12 to 13 to 17 in FIG. 3 (at this time, the source or drain and the substrate are biased in the opposite direction and no current flows.

) When the spontaneous polarization disappears and the channel disappears and the connection between the source and drain becomes OFF, the electric field is no longer applied to the ferroelectric material at the gate, and the spontaneous polarization can no longer be reversed, and the external electric field is cut off. At the same time, the hysteresis changes from 17 to 18.

In fact, as will be explained later, even in the 18 states where the spontaneous polarization value P is close to zero on average, although the value of spontaneous polarization is not completely zero at all locations, it is stable in the absence of external voltage. At this time, since the channel has disappeared, the memory transistor is in the OFF state.

In the end, even if you use a writing method that applies a voltage between at least one of the source and drain and the gate, the on-off
The value can be selected.

To discuss this in more detail, when performing off writing in this operation, a larger voltage is applied to the channel part on the source or drain side to which the write voltage is applied, so the channel part on the source or drain side turns off first.
It becomes f.

In other words, the amount of charge induced on the surface between the source and drain by spontaneous polarization, that is, the apparent gate threshold voltage, differs depending on the location.

- This seems to be a drawback (it seems that when reading, the gate of the memory transistor is not biased to ensure conductance in the Qn state, but good conductance in the Qn state is obtained with the gate grounded, but on the other hand o
In the ff state, the gate is grounded, and Tomoka < off
That's fine, so it's not a problem at all.

In this respect as well, the present invention is superior to semiconductor nonvolatile memories such as MNOS that utilize the injection phenomenon.

In a semiconductor memory device that utilizes an injection phenomenon such as MNOS, which has a small change in vT, voltage is lowered to the gate of a memory transistor during reading, so variations in vT depending on the location of the channel portion are a serious drawback.

For this reason, in this type of device, it is necessary to apply voltage simultaneously from the source and drain to cause avalanche, which causes problems such as the peripheral circuitry becoming complicated.

FIG. 4 is a diagram for explaining one embodiment of the present invention.

Insulated gate field effect memory transistor Mij (i is 1
(j is an integer from 1 to n) arranged in an m-by-n matrix.

An enhancement type insulated gate field effect transistor (hereinafter referred to as a first transistor) is connected to the drain of each memory transistor Mij.
(referred to as switching transistors) Jj (t is an integer from 1 to m, j is an integer from 1 to n), and the drains of the switching transistors Sij are commonly connected for each row and the gates are commonly connected for each column. , and let their output terminals be X. and Yj, respectively.

In addition, a separate enhancement type insulated gate field effect transistor (hereinafter referred to as a second switching transistor) Sij(i) is connected to the source of each memory transistor Mij.
is an integer from 1 to m, and j is an integer from 1 to n) are connected to each other, and the source and gate of this second switching transistor Sij are connected in common, and are used as Out and W/R terminals, respectively. .

Alternatively, the gates of the memory transistors Mij are commonly connected independently, or for each word, for each character, or for each page, and used as an Erase terminal.

The semiconductor memory device of the present invention having an example of the configuration described above has a pseudo-random access function capable of erasing memory contents for each information unit such as bits, words, characters, or pages, and writing bits for each bit. Moreover, writing and erasing can be performed using a unipolar voltage.

Next, the operation will be explained with reference to FIGS. 4 and 5.

First, to erase, all the first
switching transistor S? j is turned on and the drains of all memory transistors Mij are grounded,
A negative erase voltage vwi is applied to the commonly connected E rase terminal for each information unit.

At this time, the W/R terminal may be grounded or may be biased appropriately.

Next, writing is performed by grounding the W/R terminal, turning off all the second switching transistor groups Sij and separating the rows and columns of each memory cell, and applying a negative voltage to the Yl terminal to turn off the switching transistor group Sij. 5i1(
1=1.2, . . . , m) is set to Qn, and by further applying a negative write voltage Vw2 from the Xk terminal, a negative write voltage ■ is applied from the drain to only the memory transistor Mkl in the first row and column. This is done by adding w2.

Next, for reading, all the switching transistor groups Sij are set to Qn by applying a negative voltage to the W/R terminal, and an appropriate negative voltage is applied to the Xq Yr terminal of the address to be read. Q
Output voltage and current according to n state or off state
This is done by reading from the terminal.

At this time, the voltage vR applied from the Xq terminal is selected to be as large as necessary for reading and much smaller than the writing voltage VWZ, so as to minimize disturbances applied to the gate ferroelectric of the memory transistor.

Actually, the write and erase voltages VWZ and ■wn are -15V.
It is appropriate to select the read voltage to be approximately -3 to -5V.

Below, we will estimate the influence of half-selective disturbance in this case.

The activation electric field of the bismuth titanate thin film deposited on a silicon substrate that we have obtained is 1.5 to 7 x 106 ■/crr.
If bismuth titanate with a film thickness of about 1 μm is used, the applied voltage required for activation will be 150 to 700 V.

Therefore, the reversal time of spontaneous polarization due to a disturbance of -5V is -1
Since the reversal time at 5■ is normally 0.1 seconds, 3.4
It is believed to be over 105 years old.

In addition, in the case of a simple half-selection method, there is disturbance due to a half-selection voltage of about 7.5V, but the inversion time due to this voltage is 15V.
Looks like it's over a year old.

Therefore, although this bismuth titanate film is originally stable against half-selective disturbances, there remained some concerns, but with the present invention, the lifetime of the polarized state due to half-selective voltage is approximately 1
It has improved by 0' times and I no longer have that anxiety.

It must be said that the effects of the present invention are truly unprecedented.

In addition, according to the present invention, since it is possible to adopt a writing method from either one side of the drain or the source, there is a significant effect that the circuit configuration including the peripheral circuits is simplified.

Furthermore, in the unipolar embodiment according to the present invention,
Even when the peripheral circuits are manufactured on the same substrate, there is no need to separate the peripheral circuits and the memory portion, which simplifies the structure, facilitates manufacturing, and enables high-density integration.

Further, according to the present invention, completely random access is not possible, but since information often flows in units of words, characters, pages, etc., erasing is performed for each unit of information.
By providing the e terminal, it is possible to perform the same operation as random access as a normal storage device.

This is why I mentioned earlier that it has a pseudo-random access function.

In the embodiment, the switch transistor group Sij
Although +Sij is configured with an insulated gate field effect transistor, the present invention is not limited to an insulated gate field effect transistor, and can be replaced with other switching elements.

Furthermore, the gate insulator of the memory transistor Mij is not limited to the bismuth titanate ferroelectric material shown in the embodiment, but can be replaced with a ferroelectric material that still exhibits ferroelectricity even when made into a thin film.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating write and erase characteristics of a single memory transistor having a bismuth titanate ferroelectric material as a gate insulator used in an embodiment of the present invention.
This shows G hysteresis characteristics. FIG. 2 is a schematic diagram showing the structure of a single memory transistor, in which 1 is an n-type S substrate, 2 and 3 are p-type impurity regions of the source or drain, respectively, and 4 is a bismuth titanate ferroelectric insulating thin film. , 5 is a gate electrode, and 6 and 7 are source or drain electrodes, respectively. 8 is a substrate electrode. FIG. 3 is a diagram showing a hysteresis loop of polarization and electric field, which is used to explain the writing method of the memory transistor. FIG. 4 is a configuration diagram of a memory array showing one embodiment of the present invention, and FIG. 5 is an explanatory diagram showing how voltages are applied to operate the memory array.

Claims (1)

[Claims] 1 Insulated gate field effect nonvolatile memory transistors having ferroelectric material as a gate insulator are arranged in a matrix, and the source of each insulated gate field effect transistor is connected to the drain of each memory transistor to form the insulated gate field effect transistor. The drains of the insulated gate field effect transistors are commonly connected for each row, and the gates are commonly connected for each column, and the drains of other insulated gate field effect transistors are connected to the sources of each memory transistor, so that the sources and gates of the insulated gate field effect transistors are commonly connected. What is claimed is: 1. A semiconductor memory device characterized in that gate terminals of memory transistors are commonly connected independently or word by word, character by character, or page by page.