JPS584494B2 - Isoudou Kihatsushinkinyoru Bittuudou Kisouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving circuit for a data transmission device, and particularly to bit synchronization extraction using a phase synchronized oscillator.

In digital communication, bit synchronization information regarding bit frequency and phase is necessary for identifying received data or for reproducing and relaying data.

Since this bit synchronization information is generally not provided, it is extracted by appropriately processing the received data.

However, received data suffers from waveform distortion due to transmission interference due to noise and intersymbol interference, and the bit synchronization information extracted from this data contains jitter, resulting in reduced margins during identification and accumulation of jitter during regenerative relay. A problem has arisen.

To solve this problem, conventionally, a tank circuit and a phase-locked oscillator are used to suppress jitter and extract bit-synchronized information.

There are many code formats in digital communication, as shown in FIG. 1, but it is necessary that bit synchronization information can be easily extracted.

NRZ (Non Return to Z) shown in Figure 1A
erol), RZ (Return to Ze) shown in B
The code ro) has a drawback in that it is impossible to extract bit synchronization information containing consecutive "0"s.

On the other hand, the two-phase modulation codes shown in C to E all include bit synchronization information, and the only difference is that the phases are shifted.

Here, C is a two-phase modulation level code, D is a two-phase modulation mark code, and E is a two-phase modulation space code.

The present invention is directed to these two-phase modulation code C to E formats, and here, the case of two-phase modulation mark code D will be specifically explained as an example.

As shown in Figure 1D, the two-phase modulation mark code has a changing point at the break of the bit period, and if there is a changing point half a bit width after this changing point, it will be "0", otherwise it will be "1". It is something to do.

FIG. 2 shows a bit synchronization information extraction circuit using a conventional phase synchronization oscillator, and FIG. 3 shows its operating waveforms a to g.

The phase synchronized oscillator 60 includes the phase comparator 20 and the filter circuit 3
0, a voltage controlled oscillator 40 and a falling change point detection circuit 50 connected to a path that feeds back its output frequency to the phase comparator 20.

In general, a phase comparator can be constructed from an exclusive OR gate, a flip-flop, etc., but here we will refer to the oscillation frequency of the phase synchronized oscillator 60 when there is no input (usually this state is called free-running oscillation, and the oscillation frequency at that time is called free-running frequency). A J-K flip-flop is used to ensure that the frequency (called 1/2) is approximately equal to the frequency of the input, and the comparison input is 1/4 as shown in Figure 3.
Bit period (The bit period is T.

) has a phase difference of In the connection of the J-K flip-flop shown in Figure 2, the J and K inputs are set to "1", and when a pulse is input to the trigger input terminal T, the states of the outputs Q and Q change relative to the state at the previous time. Invert.

Furthermore, when a pulse is input to the set input terminal S, Q becomes "1" regardless of the input state.

The inputs to the input terminals S and T of the phase comparator 20 have a phase difference of 1/4 bit period width, and are phase-locked to a frequency of 2/(bit period) as shown in FIG.

When the phase synchronized oscillator 60 is in free-running oscillation, the only input to the phase comparator 20 is a trigger input, and the output Q is (
It is inverted every bit period)/2.

Therefore, the average value of the filter circuit 30 is Vp/2 (V
A voltage of p: pulse peak value) is applied.

The filter circuit 30 includes a phase comparator 20 and a voltage controlled oscillator 4.
0, the input impedance is sufficiently large and the output impedance is sufficiently small, and is composed of, for example, an amplifier, a lag filter, or a lead-lag filter.

The filter constant and amplifier gain are determined based on the stability of the phase synchronized oscillator 60, synchronization pull-in time, jitter suppression characteristics, etc.

The voltage controlled oscillator 40 has a characteristic that the output frequency changes linearly with respect to the input voltage.

The DC operating point when the input frequency and free-running frequency are equal is Kf・Vp, where the DC gain of the filter circuit is Kf.
With an input voltage of /2, the output frequency of the voltage controlled oscillator 40 is a free running frequency.

When the input frequency is higher than the free-running frequency, the duty ratio of the output pulse of the phase comparator is greater than 50%, its average value is greater than Vp/2, and the frequency of the voltage controlled oscillator 40 increases to become equal to the input frequency.

Therefore, strictly speaking, the phase difference between the input and output frequencies does not match, but since the loop gain is large, it can be considered that the phases are approximately synchronized.

50 is the voltage controlled oscillator output b which is 1/1/with respect to the input frequency.
This is a falling change point detection circuit for feedback with a 4-bit synchronous phase difference.

FIG. 3 shows operating waveforms of a circuit that extracts bit synchronization information from a two-phase modulation mark code, which is synchronized to a frequency of 2/(bit period).

The free-running frequency of the phase-locked oscillator is made to roughly match the bit frequency supplied from a high-precision crystal, for example, on the transmitter side, but the frequency stability of the phase-locked oscillator is considerably worse than that of a crystal, and generally It is about a few coefficients.

As is clear from FIG. 3, when the received data has a series of "0"s, the phase comparison operation is performed correctly, and both the frequency and phase of the phase synchronized oscillator 60 are synchronized with that of the received data.

However, when "1" occurs in the received data, the phase comparator output is determined only by the output b of the voltage controlled oscillator 40, and even though bit synchronization information exists in the received data, it is not used.

Therefore, when "1" appears in the received data, the phase synchronized oscillator 60 is controlled to return to the free running frequency.

Therefore, depending on the relationship between the number of consecutive "1" bits and the size of the time constant of the filter circuit, the frequency returns to the free-running frequency.

In addition, since the received data is generally random binary data, it is possible to predict the appearance of a considerable number of consecutive "1"s.
In order to maintain the bit frequency even if "" continues, the filter time constant must be made larger than necessary, which is undesirable because it takes a long time to acquire synchronization.

Also, as shown in Figure 3, when the value is "0", there is a change point at the center of the bit period, so this may be regarded as a bit break and synchronization may occur, and there is also a recovery function to return to the correct synchronization state. It was difficult to

SUMMARY OF THE INVENTION An object of the present invention is to provide a bit synchronization device that takes a short time to acquire synchronization and operates stably.

A feature of the present invention is that unnecessary phase comparison information present at the center of each bit period of a two-phase modulation code is masked by the phase-locked oscillator output.

In the present invention, the two-phase modulation code has correct phase comparison information for each bit period and unnecessary phase comparison information at the center of each bit period. It takes advantage of the fact that the frequencies match, and that the frequency of the received data and the free-running frequency generally match with an accuracy of a numerical coefficient or less even if they are not phase synchronized.

FIG. 4 shows the principle configuration of the present invention, which includes a changing point detection circuit 10 for converting changing points of received data into a pulse train, a phase comparator 20, a filter circuit 30, and a voltage controlled oscillator 40. A first frequency dividing circuit 80 divides the output b of the oscillator 40 and provides an output pulse f to one input of the phase comparator 20, and an output pulse C having a constant phase relationship with the output pulse f is obtained. Second frequency divider circuit 8
0', the output of the change point detection circuit 10, and the output pulse C, and a gate circuit 70 that ANDs the output of the change point detection circuit 10 and the output pulse C, and outputs the result to the other input of the phase comparator 20;
Determine whether or not the voltage controlled oscillator 40 is operating normally based on the output of the output and the output of the second frequency dividing circuit 80';
Synchronization determination control circuit 90 that controls second frequency dividing circuit 80'
It is composed of.

With such a configuration, unnecessary portions of the phase comparison input (output of the change point detection circuit 10) are connected to the frequency dividing circuit 80' and the gate having an appropriate phase relationship with respect to the output f of the frequency dividing circuit 80. When the phase synchronization oscillator is masked by the circuit 70 and the phase synchronization oscillator is not correctly phase synchronized, it is detected by the synchronization judgment control circuit 90, and by resetting the second frequency dividing circuit 80', the phase synchronization is correctly performed. controlled as follows.

FIG. 5 shows a circuit diagram of a specific embodiment of FIG. 4, and FIGS. 6 and 7 show its operating waveforms.

The phase synchronized oscillator 60 includes a phase comparator 20 using a JK flip-flop, an amplifier with sufficiently large input impedance and sufficiently small output impedance, for example.
A filter circuit 30 consisting of a lag or lead-lag circuit, a voltage controlled oscillator 40 with a linear relationship between input voltage and output frequency, and a voltage controlled oscillator whose frequency is halved.
Edge-triggered J-K flip-flop 80 that divides the frequency into
'An inverter 81 that delays the phase of this frequency-divided wave number by 1/2 bit cycle relative to the received data, an edge-trigger J-K flip-flop 80, a circuit 82 that detects the rising and changing points, and an unnecessary changing point of the received data that detects the phase. It consists of an AND circuit 70 for prohibiting input to the comparator 20 by the output of the voltage controlled oscillator.

The synchronization determination control circuit 90 extracts the pulse set by the pulse e applied to the phase comparator 20 and inhibited by the AND gate 70 using the AND gate 92 and the inverter 91 from the pulse train at the changing point of the received data. Set reset by pulse, reset flip-flop 93
, a circuit 95 that detects the falling change point of the frequency-divided output C of the voltage controlled oscillator 40, an AND gate 94 that controls passage of this changing point pulse, and an output h of the AND gate 94 that divides the output of the voltage controlled oscillator 40. and means for applying the reset R of the rotating flip-flop 80'.

The normal operation will be explained with reference to FIG.

The pulse train a of the received data is converted by the change point detection circuit 10 into a pulse train at the change point.

This changing point pulse train is processed by an AND gate 70, and by the Q output C of a flip-flop 80' which divides a frequency synchronized with that of the received data in terms of both frequency and phase, unnecessary pulses other than those used to separate bit periods are prohibited.

The output frequency b of the voltage controlled oscillator 40 is divided by a flip-flop 80', and this Q output and the voltage controlled oscillator output b inverted by the inverter 81 are applied to the flip-flop 80 to produce a frequency-divided output with a 3/4 bit cycle phase delay. becomes.

This output d passes through the rising edge change point detection circuit 82 and is fed back to the phase comparator 20 as a pulse delayed by 1/2 bit cycle from the bit cycle break.

The feedback pulse f is applied to the trigger terminal T in the phase comparator 20 of the JK flip-flop,
The output g is inverted and the pulse e which has passed through the AND gate 70 mentioned above is applied to the set input S to make the output Q=1.

When the frequency of the received data is higher than that of the phase controlled oscillator 60', the duty ratio of the pulse output of the phase comparator 20 becomes large, and therefore its average value also becomes large, raising the frequency b of the voltage controlled oscillator 40 and increasing the frequency of the input signal. Synchronize it with that.

The filter circuit 30 smoothes the output pulse of the phase comparator 20 and determines characteristics such as system stability, synchronization pull-in time, and jitter suppression.

The operation of the synchronization determination control circuit 90 is as follows.

The falling change point pulse train J of the Q output C of the flip-flop 80' is inhibited by the AND gate 94 by the signal of the Q output i of the set-reset flip-flop 93, and is not applied to the reset terminal R of the flip-flop 80'.

Further, the operation of the synchronization determination control circuit 90 will be explained in detail with reference to FIG.

In the figure, dotted lines indicate correct bit period divisions, and solid lines indicate incorrect bit period divisions, and an explanation will be given of corrective operations when synchronization occurs with an incorrect bit period division for some reason such as noise.

If there are consecutive "0"s in the received data, the bit period delimiter will remain incorrect, but if even one "1" appears,
If it is synchronized to the correct bit period break, time t
1, a change point pulse must exist in the received data, but if it is synchronized with the wrong bit period break, no change point pulse exists.

Therefore, flip-flop 93 remains set, and the point output C of flip-flop 80' at time t2
The falling change point pulse j passes through the AND gate 94,
Flip-flop 80' is reset.

To describe this operation in detail in terms of time, at time t2, the fall of the output b of the voltage controlled oscillator 40 causes the output C of the Q of the flip-flop 80' to become "0".

The fall of this Q output C is applied to the reset input R of the flip-flop 80' after the propagation delay time of the fall detection circuit 95, the AND gate 94, and the element, and the flip-flop 80' is reset and its output Q becomes "1". becomes.

This causes the phase of the output of the flip-flop 80' to be 1.
The phase comparator 20 detects only the change point pulse at the end of the correct bit synchronization, and the inhibition by the AND gate 70 of the change point pulse train of the received data is delayed by 1/2 bit period.
can be added to.

Therefore, the synchronization determination control circuit 90 causes "1" in the data.
” appears, it is detected whether the bits are correctly synchronized, and if it is incorrect, it is corrected.

Note that this bit synchronization correction operation is performed by applying 1/1 to the phase comparator 20.
Although a two-bit synchronous phase disturbance is given, the frequency fluctuation can be made sufficiently small by appropriately selecting the constants of the filter circuit 30, and does not particularly affect the circuit operation.

Next, problems encountered during synchronization pull-in operation will be explained.

The deviation between the free-running frequency of the phase-locked oscillator 60' and that of the received data is determined by the stability of the voltage-controlled oscillator 40, but the free-running frequency and the frequency of the received data can be matched with a deviation of several percent or less. .

Therefore, there is no particular problem in the operation of feeding back the output frequency of the voltage controlled oscillator 40 and inhibiting the changing point pulse train of the received data.

According to the embodiment shown in FIG. 5, the following effects (1) to (4) can be expected.

(1) Pulses that are not necessary for phase comparison are masked by the output of the phase-locked oscillator, so even if "1" continues, the free-running frequency does not return to the free-running frequency. Therefore, the time constant can be reduced, and the synchronization pull-in Time is short.

(2) Even when synchronizing to the wrong phase, the appearance of "1" automatically synchronizes to the correct phase and is stable.

As described above, the present invention provides a bit synchronization device that takes a short time to pull in synchronization and operates stably.

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining the transmission code format used in the present invention, Fig. 2 is a bit synchronization device using a conventional phase synchronization oscillator, Fig. 3 is an operation waveform diagram of Fig. 2, and Fig. 4 is a diagram for explaining the transmission code format used in the present invention. 5 is a diagram showing the principle configuration of the present invention, FIG. 5 is a circuit diagram of an embodiment of the present invention, and FIGS. 6 and 7 are operation waveform diagrams of FIG. 5. Explanation of symbols, 60'... Phase synchronized oscillator, 70
...Gate circuit, 80, 80'... Frequency dividing circuit, 90... Synchronization judgment control circuit. 165-

Claims (1)

[Claims] 1 Extracts bit synchronization information of a receiving circuit for data transmission using a two-phase modulation code as a transmission code format, and includes a change point detection circuit that converts change points of received data into a pulse train, a phase comparator, In the filter circuit and the voltage controlled oscillator, a first frequency dividing circuit divides the output of the voltage controlled oscillator and provides an output pulse to one of the phase comparators; a second frequency dividing circuit that obtains an output pulse having a certain phase relationship with respect to the output pulse, and logically multiplying the output pulse of the second frequency dividing circuit and the output pulse of the change point detection circuit, and performing the comparison. determining whether the voltage controlled oscillator is operating normally based on the output of the gate circuit output to the other input of the oscillator, the output of the change point detection circuit, the output of the gate circuit, and the output of the second frequency dividing circuit; A bit synchronization device using a phase synchronized oscillator, characterized in that a synchronization determination control circuit for controlling the second frequency dividing circuit is provided.